brcm80211: fmac: optimize chip core info management
Prepare for adding backplane interconnect type support Reviewed-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: Franky Lin <frankyl@broadcom.com> Signed-off-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Franky Lin
John W. Linville
parent
61213be4cc
commit
99ba15cd75
@ -28,6 +28,7 @@
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#include <linux/semaphore.h>
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#include <linux/firmware.h>
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#include <linux/module.h>
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#include <linux/bcma/bcma.h>
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#include <asm/unaligned.h>
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#include <defs.h>
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#include <brcmu_wifi.h>
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@ -614,10 +615,12 @@ static bool data_ok(struct brcmf_bus *bus)
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static void
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r_sdreg32(struct brcmf_bus *bus, u32 *regvar, u32 reg_offset, u32 *retryvar)
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{
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u8 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
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*retryvar = 0;
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do {
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*regvar = brcmf_sdcard_reg_read(bus->sdiodev,
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bus->ci->buscorebase + reg_offset, sizeof(u32));
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bus->ci->c_inf[idx].base + reg_offset,
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sizeof(u32));
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} while (brcmf_sdcard_regfail(bus->sdiodev) &&
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(++(*retryvar) <= retry_limit));
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if (*retryvar) {
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@ -632,10 +635,11 @@ r_sdreg32(struct brcmf_bus *bus, u32 *regvar, u32 reg_offset, u32 *retryvar)
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static void
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w_sdreg32(struct brcmf_bus *bus, u32 regval, u32 reg_offset, u32 *retryvar)
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{
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u8 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
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*retryvar = 0;
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do {
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brcmf_sdcard_reg_write(bus->sdiodev,
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bus->ci->buscorebase + reg_offset,
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bus->ci->c_inf[idx].base + reg_offset,
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sizeof(u32), regval);
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} while (brcmf_sdcard_regfail(bus->sdiodev) &&
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(++(*retryvar) <= retry_limit));
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@ -683,8 +687,8 @@ static int brcmf_sdbrcm_htclk(struct brcmf_bus *bus, bool on, bool pendok)
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return -EBADE;
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}
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if (pendok && ((bus->ci->buscoretype == PCMCIA_CORE_ID)
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&& (bus->ci->buscorerev == 9))) {
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if (pendok && ((bus->ci->c_inf[1].id == PCMCIA_CORE_ID)
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&& (bus->ci->c_inf[1].rev == 9))) {
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u32 dummy, retries;
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r_sdreg32(bus, &dummy,
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offsetof(struct sdpcmd_regs, clockctlstatus),
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@ -909,8 +913,8 @@ static int brcmf_sdbrcm_bussleep(struct brcmf_bus *bus, bool sleep)
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/* Force pad isolation off if possible
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(in case power never toggled) */
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if ((bus->ci->buscoretype == PCMCIA_CORE_ID)
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&& (bus->ci->buscorerev >= 10))
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if ((bus->ci->c_inf[1].id == PCMCIA_CORE_ID)
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&& (bus->ci->c_inf[1].rev >= 10))
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brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
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SBSDIO_DEVICE_CTL, 0, NULL);
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@ -3094,6 +3098,8 @@ static int brcmf_sdbrcm_download_state(struct brcmf_bus *bus, bool enter)
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{
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uint retries;
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int bcmerror = 0;
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u8 idx;
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struct chip_info *ci = bus->ci;
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/* To enter download state, disable ARM and reset SOCRAM.
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* To exit download state, simply reset ARM (default is RAM boot).
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@ -3101,10 +3107,11 @@ static int brcmf_sdbrcm_download_state(struct brcmf_bus *bus, bool enter)
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if (enter) {
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bus->alp_only = true;
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brcmf_sdio_chip_coredisable(bus->sdiodev,
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bus->ci->armcorebase);
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idx = brcmf_sdio_chip_getinfidx(ci, BCMA_CORE_ARM_CM3);
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brcmf_sdio_chip_coredisable(bus->sdiodev, ci->c_inf[idx].base);
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brcmf_sdio_chip_resetcore(bus->sdiodev, bus->ci->ramcorebase);
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idx = brcmf_sdio_chip_getinfidx(ci, BCMA_CORE_INTERNAL_MEM);
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brcmf_sdio_chip_resetcore(bus->sdiodev, ci->c_inf[idx].base);
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/* Clear the top bit of memory */
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if (bus->ramsize) {
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@ -3113,8 +3120,9 @@ static int brcmf_sdbrcm_download_state(struct brcmf_bus *bus, bool enter)
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(u8 *)&zeros, 4);
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}
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} else {
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idx = brcmf_sdio_chip_getinfidx(ci, BCMA_CORE_INTERNAL_MEM);
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if (!brcmf_sdio_chip_iscoreup(bus->sdiodev,
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bus->ci->ramcorebase)) {
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ci->c_inf[idx].base)) {
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brcmf_dbg(ERROR, "SOCRAM core is down after reset?\n");
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bcmerror = -EBADE;
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goto fail;
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@ -3129,7 +3137,8 @@ static int brcmf_sdbrcm_download_state(struct brcmf_bus *bus, bool enter)
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w_sdreg32(bus, 0xFFFFFFFF,
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offsetof(struct sdpcmd_regs, intstatus), &retries);
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brcmf_sdio_chip_resetcore(bus->sdiodev, bus->ci->armcorebase);
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idx = brcmf_sdio_chip_getinfidx(ci, BCMA_CORE_ARM_CM3);
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brcmf_sdio_chip_resetcore(bus->sdiodev, ci->c_inf[idx].base);
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/* Allow HT Clock now that the ARM is running. */
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bus->alp_only = false;
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@ -3711,6 +3720,7 @@ brcmf_sdbrcm_probe_attach(struct brcmf_bus *bus, u32 regsva)
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int err = 0;
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int reg_addr;
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u32 reg_val;
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u8 idx;
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bus->alp_only = true;
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@ -3764,7 +3774,8 @@ brcmf_sdbrcm_probe_attach(struct brcmf_bus *bus, u32 regsva)
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}
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/* Set core control so an SDIO reset does a backplane reset */
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reg_addr = bus->ci->buscorebase +
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idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
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reg_addr = bus->ci->c_inf[idx].base +
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offsetof(struct sdpcmd_regs, corecontrol);
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reg_val = brcmf_sdcard_reg_read(bus->sdiodev, reg_addr, sizeof(u32));
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brcmf_sdcard_reg_write(bus->sdiodev, reg_addr, sizeof(u32),
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@ -19,6 +19,7 @@
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#include <linux/netdevice.h>
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#include <linux/mmc/card.h>
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#include <linux/ssb/ssb_regs.h>
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#include <linux/bcma/bcma.h>
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#include <chipcommon.h>
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#include <brcm_hw_ids.h>
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@ -82,6 +83,18 @@ static const struct sdiod_drive_str sdiod_drive_strength_tab3[] = {
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0, 0x0}
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};
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u8
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brcmf_sdio_chip_getinfidx(struct chip_info *ci, u16 coreid)
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{
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u8 idx;
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for (idx = 0; idx < BRCMF_MAX_CORENUM; idx++)
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if (coreid == ci->c_inf[idx].id)
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return idx;
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return BRCMF_MAX_CORENUM;
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}
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static u32
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brcmf_sdio_chip_corerev(struct brcmf_sdio_dev *sdiodev,
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u32 corebase)
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@ -239,9 +252,10 @@ static int brcmf_sdio_chip_recognition(struct brcmf_sdio_dev *sdiodev,
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* For different chiptypes or old sdio hosts w/o chipcommon,
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* other ways of recognition should be added here.
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*/
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ci->cccorebase = regs;
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ci->c_inf[0].id = BCMA_CORE_CHIPCOMMON;
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ci->c_inf[0].base = regs;
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regdata = brcmf_sdcard_reg_read(sdiodev,
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CORE_CC_REG(ci->cccorebase, chipid), 4);
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CORE_CC_REG(ci->c_inf[0].base, chipid), 4);
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ci->chip = regdata & CID_ID_MASK;
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ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
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@ -250,9 +264,12 @@ static int brcmf_sdio_chip_recognition(struct brcmf_sdio_dev *sdiodev,
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/* Address of cores for new chips should be added here */
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switch (ci->chip) {
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case BCM4329_CHIP_ID:
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ci->buscorebase = BCM4329_CORE_BUS_BASE;
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ci->ramcorebase = BCM4329_CORE_SOCRAM_BASE;
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ci->armcorebase = BCM4329_CORE_ARM_BASE;
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ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
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ci->c_inf[1].base = BCM4329_CORE_BUS_BASE;
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ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM;
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ci->c_inf[2].base = BCM4329_CORE_SOCRAM_BASE;
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ci->c_inf[3].id = BCMA_CORE_ARM_CM3;
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ci->c_inf[3].base = BCM4329_CORE_ARM_BASE;
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ci->ramsize = BCM4329_RAMSIZE;
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break;
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default:
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@ -316,35 +333,39 @@ brcmf_sdio_chip_buscoresetup(struct brcmf_sdio_dev *sdiodev,
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struct chip_info *ci)
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{
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u32 regdata;
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u8 idx;
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/* get chipcommon rev */
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ci->ccrev = brcmf_sdio_chip_corerev(sdiodev, ci->cccorebase);
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ci->c_inf[0].rev =
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brcmf_sdio_chip_corerev(sdiodev, ci->c_inf[0].base);
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/* get chipcommon capabilites */
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ci->cccaps = brcmf_sdcard_reg_read(sdiodev,
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CORE_CC_REG(ci->cccorebase, capabilities), 4);
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ci->c_inf[0].caps =
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brcmf_sdcard_reg_read(sdiodev,
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CORE_CC_REG(ci->c_inf[0].base, capabilities), 4);
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/* get pmu caps & rev */
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if (ci->cccaps & CC_CAP_PMU) {
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if (ci->c_inf[0].caps & CC_CAP_PMU) {
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ci->pmucaps = brcmf_sdcard_reg_read(sdiodev,
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CORE_CC_REG(ci->cccorebase, pmucapabilities), 4);
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CORE_CC_REG(ci->c_inf[0].base, pmucapabilities), 4);
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ci->pmurev = ci->pmucaps & PCAP_REV_MASK;
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}
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ci->buscorerev = brcmf_sdio_chip_corerev(sdiodev, ci->buscorebase);
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ci->c_inf[1].rev = brcmf_sdio_chip_corerev(sdiodev, ci->c_inf[1].base);
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regdata = brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(ci->buscorebase, sbidhigh), 4);
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ci->buscoretype = (regdata & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT;
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CORE_SB(ci->c_inf[1].base, sbidhigh), 4);
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ci->c_inf[1].id = (regdata & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT;
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brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
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ci->ccrev, ci->pmurev, ci->buscorerev, ci->buscoretype);
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ci->c_inf[0].rev, ci->pmurev,
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ci->c_inf[1].rev, ci->c_inf[1].id);
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/*
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* Make sure any on-chip ARM is off (in case strapping is wrong),
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* or downloaded code was already running.
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*/
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brcmf_sdio_chip_coredisable(sdiodev, ci->armcorebase);
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idx = brcmf_sdio_chip_getinfidx(ci, BCMA_CORE_ARM_CM3);
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brcmf_sdio_chip_coredisable(sdiodev, ci->c_inf[idx].base);
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}
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int brcmf_sdio_chip_attach(struct brcmf_sdio_dev *sdiodev,
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@ -371,9 +392,9 @@ int brcmf_sdio_chip_attach(struct brcmf_sdio_dev *sdiodev,
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brcmf_sdio_chip_buscoresetup(sdiodev, ci);
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brcmf_sdcard_reg_write(sdiodev,
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CORE_CC_REG(ci->cccorebase, gpiopullup), 4, 0);
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CORE_CC_REG(ci->c_inf[0].base, gpiopullup), 4, 0);
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brcmf_sdcard_reg_write(sdiodev,
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CORE_CC_REG(ci->cccorebase, gpiopulldown), 4, 0);
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CORE_CC_REG(ci->c_inf[0].base, gpiopulldown), 4, 0);
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*ci_ptr = ci;
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return 0;
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@ -410,7 +431,7 @@ brcmf_sdio_chip_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
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u32 str_shift = 0;
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char chn[8];
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if (!(ci->cccaps & CC_CAP_PMU))
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if (!(ci->c_inf[0].caps & CC_CAP_PMU))
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return;
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switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) {
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@ -450,15 +471,15 @@ brcmf_sdio_chip_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
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}
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brcmf_sdcard_reg_write(sdiodev,
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CORE_CC_REG(ci->cccorebase, chipcontrol_addr),
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CORE_CC_REG(ci->c_inf[0].base, chipcontrol_addr),
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4, 1);
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cc_data_temp = brcmf_sdcard_reg_read(sdiodev,
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CORE_CC_REG(ci->cccorebase, chipcontrol_addr), 4);
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CORE_CC_REG(ci->c_inf[0].base, chipcontrol_addr), 4);
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cc_data_temp &= ~str_mask;
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drivestrength_sel <<= str_shift;
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cc_data_temp |= drivestrength_sel;
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brcmf_sdcard_reg_write(sdiodev,
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CORE_CC_REG(ci->cccorebase, chipcontrol_addr),
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CORE_CC_REG(ci->c_inf[0].base, chipcontrol_addr),
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4, cc_data_temp);
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brcmf_dbg(INFO, "SDIO: %dmA drive strength selected, set to 0x%08x\n",
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@ -52,17 +52,22 @@
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#define SBSDIO_CLKAV(regval, alponly) \
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(SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
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#define BRCMF_MAX_CORENUM 6
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struct chip_core_info {
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u16 id;
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u16 rev;
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u32 base;
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u32 wrapbase;
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u32 caps;
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};
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struct chip_info {
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u32 chip;
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u32 chiprev;
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u32 cccorebase;
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u32 ccrev;
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u32 cccaps;
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u32 buscorebase; /* 32 bits backplane bus address */
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u32 buscorerev;
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u32 buscoretype;
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u32 ramcorebase;
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u32 armcorebase;
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/* core info */
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/* always put chipcommon core at 0, bus core at 1 */
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struct chip_core_info c_inf[BRCMF_MAX_CORENUM];
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u32 pmurev;
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u32 pmucaps;
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u32 ramsize;
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@ -120,5 +125,7 @@ extern void brcmf_sdio_chip_detach(struct chip_info **ci_ptr);
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extern void brcmf_sdio_chip_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
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struct chip_info *ci,
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u32 drivestrength);
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extern u8 brcmf_sdio_chip_getinfidx(struct chip_info *ci, u16 coreid);
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#endif /* _BRCMFMAC_SDIO_CHIP_H_ */
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