thermal: exynos: remove identical values from exynos*_tmu_registers structures
There is no need for abstracting configuration for registers that are identical on all SoC types. There should be no functional changes caused by this patch. Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Amit Daniel Kachhap <amit.daniel@samsung.com> Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
This commit is contained in:
parent
9c7a87f146
commit
99d67fb993
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@ -174,7 +174,7 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
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trim_info = readl(data->base + reg->triminfo_data);
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trim_info = readl(data->base + reg->triminfo_data);
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}
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}
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data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
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data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
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data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
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data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) &
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EXYNOS_TMU_TEMP_MASK);
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EXYNOS_TMU_TEMP_MASK);
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if (!data->temp_error1 ||
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if (!data->temp_error1 ||
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@ -184,7 +184,7 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
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if (!data->temp_error2)
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if (!data->temp_error2)
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data->temp_error2 =
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data->temp_error2 =
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(pdata->efuse_value >> reg->triminfo_85_shift) &
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(pdata->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) &
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EXYNOS_TMU_TEMP_MASK;
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EXYNOS_TMU_TEMP_MASK;
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rising_threshold = readl(data->base + reg->threshold_th0);
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rising_threshold = readl(data->base + reg->threshold_th0);
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@ -274,11 +274,11 @@ static void exynos_tmu_control(struct platform_device *pdev, bool on)
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if (pdata->test_mux)
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if (pdata->test_mux)
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con |= (pdata->test_mux << reg->test_mux_addr_shift);
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con |= (pdata->test_mux << reg->test_mux_addr_shift);
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con &= ~(reg->buf_vref_sel_mask << reg->buf_vref_sel_shift);
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con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK << EXYNOS_TMU_REF_VOLTAGE_SHIFT);
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con |= pdata->reference_voltage << reg->buf_vref_sel_shift;
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con |= pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT;
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con &= ~(reg->buf_slope_sel_mask << reg->buf_slope_sel_shift);
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con &= ~(EXYNOS_TMU_BUF_SLOPE_SEL_MASK << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT);
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con |= (pdata->gain << reg->buf_slope_sel_shift);
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con |= (pdata->gain << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT);
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if (pdata->noise_cancel_mode) {
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if (pdata->noise_cancel_mode) {
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con &= ~(reg->therm_trip_mode_mask <<
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con &= ~(reg->therm_trip_mode_mask <<
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@ -287,7 +287,7 @@ static void exynos_tmu_control(struct platform_device *pdev, bool on)
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}
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}
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if (on) {
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if (on) {
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con |= (1 << reg->core_en_shift);
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con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
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interrupt_en =
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interrupt_en =
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pdata->trigger_enable[3] << reg->inten_rise3_shift |
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pdata->trigger_enable[3] << reg->inten_rise3_shift |
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pdata->trigger_enable[2] << reg->inten_rise2_shift |
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pdata->trigger_enable[2] << reg->inten_rise2_shift |
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@ -297,7 +297,7 @@ static void exynos_tmu_control(struct platform_device *pdev, bool on)
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interrupt_en |=
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interrupt_en |=
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interrupt_en << reg->inten_fall0_shift;
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interrupt_en << reg->inten_fall0_shift;
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} else {
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} else {
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con &= ~(1 << reg->core_en_shift);
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con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
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interrupt_en = 0; /* Disable all interrupts */
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interrupt_en = 0; /* Disable all interrupts */
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}
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}
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writel(interrupt_en, data->base + reg->tmu_inten);
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writel(interrupt_en, data->base + reg->tmu_inten);
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@ -77,20 +77,12 @@ enum soc_type {
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* bitfields. The register validity, offsets and bitfield values may vary
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* bitfields. The register validity, offsets and bitfield values may vary
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* slightly across different exynos SOC's.
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* slightly across different exynos SOC's.
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* @triminfo_data: register containing 2 pont trimming data
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* @triminfo_data: register containing 2 pont trimming data
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* @triminfo_25_shift: shift bit of the 25 C trim value in triminfo_data reg.
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* @triminfo_85_shift: shift bit of the 85 C trim value in triminfo_data reg.
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* @triminfo_ctrl: trim info controller register.
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* @triminfo_ctrl: trim info controller register.
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* @tmu_ctrl: TMU main controller register.
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* @tmu_ctrl: TMU main controller register.
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* @test_mux_addr_shift: shift bits of test mux address.
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* @test_mux_addr_shift: shift bits of test mux address.
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* @buf_vref_sel_shift: shift bits of reference voltage in tmu_ctrl register.
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* @buf_vref_sel_mask: mask bits of reference voltage in tmu_ctrl register.
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* @therm_trip_mode_shift: shift bits of tripping mode in tmu_ctrl register.
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* @therm_trip_mode_shift: shift bits of tripping mode in tmu_ctrl register.
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* @therm_trip_mode_mask: mask bits of tripping mode in tmu_ctrl register.
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* @therm_trip_mode_mask: mask bits of tripping mode in tmu_ctrl register.
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* @therm_trip_en_shift: shift bits of tripping enable in tmu_ctrl register.
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* @therm_trip_en_shift: shift bits of tripping enable in tmu_ctrl register.
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* @buf_slope_sel_shift: shift bits of amplifier gain value in tmu_ctrl
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register.
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* @buf_slope_sel_mask: mask bits of amplifier gain value in tmu_ctrl register.
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* @core_en_shift: shift bits of TMU core enable bit in tmu_ctrl register.
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* @tmu_status: register drescribing the TMU status.
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* @tmu_status: register drescribing the TMU status.
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* @tmu_cur_temp: register containing the current temperature of the TMU.
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* @tmu_cur_temp: register containing the current temperature of the TMU.
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* @threshold_temp: register containing the base threshold level.
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* @threshold_temp: register containing the base threshold level.
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@ -119,22 +111,15 @@ enum soc_type {
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*/
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*/
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struct exynos_tmu_registers {
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struct exynos_tmu_registers {
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u32 triminfo_data;
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u32 triminfo_data;
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u32 triminfo_25_shift;
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u32 triminfo_85_shift;
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u32 triminfo_ctrl;
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u32 triminfo_ctrl;
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u32 triminfo_ctrl1;
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u32 triminfo_ctrl1;
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u32 tmu_ctrl;
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u32 tmu_ctrl;
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u32 test_mux_addr_shift;
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u32 test_mux_addr_shift;
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u32 buf_vref_sel_shift;
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u32 buf_vref_sel_mask;
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u32 therm_trip_mode_shift;
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u32 therm_trip_mode_shift;
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u32 therm_trip_mode_mask;
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u32 therm_trip_mode_mask;
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u32 therm_trip_en_shift;
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u32 therm_trip_en_shift;
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u32 buf_slope_sel_shift;
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u32 buf_slope_sel_mask;
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u32 core_en_shift;
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u32 tmu_status;
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u32 tmu_status;
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@ -27,14 +27,7 @@
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#if defined(CONFIG_CPU_EXYNOS4210)
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#if defined(CONFIG_CPU_EXYNOS4210)
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static const struct exynos_tmu_registers exynos4210_tmu_registers = {
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static const struct exynos_tmu_registers exynos4210_tmu_registers = {
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.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
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.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
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.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
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.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
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.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
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.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
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.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
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.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
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.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
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.tmu_status = EXYNOS_TMU_REG_STATUS,
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.tmu_status = EXYNOS_TMU_REG_STATUS,
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.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
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.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
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.threshold_temp = EXYNOS4210_TMU_REG_THRESHOLD_TEMP,
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.threshold_temp = EXYNOS4210_TMU_REG_THRESHOLD_TEMP,
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@ -94,18 +87,11 @@ struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
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#if defined(CONFIG_SOC_EXYNOS3250)
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#if defined(CONFIG_SOC_EXYNOS3250)
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static const struct exynos_tmu_registers exynos3250_tmu_registers = {
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static const struct exynos_tmu_registers exynos3250_tmu_registers = {
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.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
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.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
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.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
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.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
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.test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT,
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.test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT,
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.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
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.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
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.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
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.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
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.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
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.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
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.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
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.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
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.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
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.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
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.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
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.tmu_status = EXYNOS_TMU_REG_STATUS,
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.tmu_status = EXYNOS_TMU_REG_STATUS,
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.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
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.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
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.threshold_th0 = EXYNOS_THD_TEMP_RISE,
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.threshold_th0 = EXYNOS_THD_TEMP_RISE,
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@ -183,19 +169,12 @@ struct exynos_tmu_init_data const exynos3250_default_tmu_data = {
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#if defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250)
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#if defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250)
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static const struct exynos_tmu_registers exynos4412_tmu_registers = {
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static const struct exynos_tmu_registers exynos4412_tmu_registers = {
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.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
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.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
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.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
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.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
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.triminfo_ctrl = EXYNOS_TMU_TRIMINFO_CON,
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.triminfo_ctrl = EXYNOS_TMU_TRIMINFO_CON,
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
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.test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT,
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.test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT,
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.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
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.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
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.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
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.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
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.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
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.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
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.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
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.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
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.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
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.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
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.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
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.tmu_status = EXYNOS_TMU_REG_STATUS,
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.tmu_status = EXYNOS_TMU_REG_STATUS,
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.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
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.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
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.threshold_th0 = EXYNOS_THD_TEMP_RISE,
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.threshold_th0 = EXYNOS_THD_TEMP_RISE,
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@ -286,18 +265,11 @@ struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
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#if defined(CONFIG_SOC_EXYNOS5260)
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#if defined(CONFIG_SOC_EXYNOS5260)
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static const struct exynos_tmu_registers exynos5260_tmu_registers = {
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static const struct exynos_tmu_registers exynos5260_tmu_registers = {
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.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
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.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
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.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
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.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL1,
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL1,
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.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
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.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
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.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
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.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
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.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
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.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
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.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
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.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
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.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
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.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
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.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
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.tmu_status = EXYNOS_TMU_REG_STATUS,
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.tmu_status = EXYNOS_TMU_REG_STATUS,
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.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
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.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
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.threshold_th0 = EXYNOS_THD_TEMP_RISE,
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.threshold_th0 = EXYNOS_THD_TEMP_RISE,
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@ -378,17 +350,10 @@ struct exynos_tmu_init_data const exynos5260_default_tmu_data = {
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#if defined(CONFIG_SOC_EXYNOS5420)
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#if defined(CONFIG_SOC_EXYNOS5420)
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static const struct exynos_tmu_registers exynos5420_tmu_registers = {
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static const struct exynos_tmu_registers exynos5420_tmu_registers = {
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.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
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.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
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.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
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.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
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.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
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.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
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.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
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.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
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.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
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.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
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.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
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.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
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.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
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.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
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.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
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.tmu_status = EXYNOS_TMU_REG_STATUS,
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.tmu_status = EXYNOS_TMU_REG_STATUS,
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.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
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.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
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.threshold_th0 = EXYNOS_THD_TEMP_RISE,
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.threshold_th0 = EXYNOS_THD_TEMP_RISE,
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@ -477,17 +442,10 @@ struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
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#if defined(CONFIG_SOC_EXYNOS5440)
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#if defined(CONFIG_SOC_EXYNOS5440)
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static const struct exynos_tmu_registers exynos5440_tmu_registers = {
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static const struct exynos_tmu_registers exynos5440_tmu_registers = {
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.triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
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.triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
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.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
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.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
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.tmu_ctrl = EXYNOS5440_TMU_S0_7_CTRL,
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.tmu_ctrl = EXYNOS5440_TMU_S0_7_CTRL,
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.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
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.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
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.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
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.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
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.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
|
.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
|
||||||
.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
|
.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
|
||||||
.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
|
|
||||||
.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
|
|
||||||
.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
|
|
||||||
.tmu_status = EXYNOS5440_TMU_S0_7_STATUS,
|
.tmu_status = EXYNOS5440_TMU_S0_7_STATUS,
|
||||||
.tmu_cur_temp = EXYNOS5440_TMU_S0_7_TEMP,
|
.tmu_cur_temp = EXYNOS5440_TMU_S0_7_TEMP,
|
||||||
.threshold_th0 = EXYNOS5440_TMU_S0_7_TH0,
|
.threshold_th0 = EXYNOS5440_TMU_S0_7_TH0,
|
||||||
|
|
Loading…
Reference in New Issue