Merge remote-tracking branches 'asoc/topic/cs35l35', 'asoc/topic/cs53l30', 'asoc/topic/da7213', 'asoc/topic/dio2125' and 'asoc/topic/dwc' into asoc-next
This commit is contained in:
Mark Brown
commit
99dd3c53f6
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@ -0,0 +1,180 @@
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CS35L35 Boosted Speaker Amplifier
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Required properties:
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- compatible : "cirrus,cs35l35"
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- reg : the I2C address of the device for I2C
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- VA-supply, VP-supply : power supplies for the device,
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as covered in
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Documentation/devicetree/bindings/regulator/regulator.txt.
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- interrupt-parent : Specifies the phandle of the interrupt controller to
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which the IRQs from CS35L35 are delivered to.
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- interrupts : IRQ line info CS35L35.
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(See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
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for further information relating to interrupt properties)
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Optional properties:
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- reset-gpios : gpio used to reset the amplifier
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- cirrus,stereo-config : Boolean to determine if there are 2 AMPs for a
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Stereo configuration
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- cirrus,audio-channel : Set Location of Audio Signal on Serial Port
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0 = Data Packet received on Left I2S Channel
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1 = Data Packet received on Right I2S Channel
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- cirrus,advisory-channel : Set Location of Advisory Signal on Serial Port
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0 = Data Packet received on Left I2S Channel
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1 = Data Packet received on Right I2S Channel
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- cirrus,shared-boost : Boolean to enable ClassH tracking of Advisory Signal
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if 2 Devices share Boost BST_CTL
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- cirrus,external-boost : Boolean to specify the device is using an external
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boost supply, note that sharing a boost from another cs35l35 would constitute
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using an external supply for the slave device
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- cirrus,sp-drv-strength : Value for setting the Serial Port drive strength
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Table 3-10 of the datasheet lists drive-strength specifications
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0 = 1x (Default)
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1 = .5x
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- cirrus,sp-drv-unused : Determines how unused slots should be driven on the
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Serial Port.
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0 - Hi-Z
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2 - Drive 0's (Default)
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3 - Drive 1's
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- cirrus,bst-pdn-fet-on : Boolean to determine if the Boost PDN control
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powers down with a rectification FET On or Off. If VSPK is supplied
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externally then FET is off.
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- cirrus,boost-ctl-millivolt : Boost Voltage Value. Configures the boost
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converter's output voltage in mV. The range is from 2600mV to 9000mV with
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increments of 100mV.
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(Default) VP
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- cirrus,boost-peak-milliamp : Boost-converter peak current limit in mA.
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Configures the peak current by monitoring the current through the boost FET.
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Range starts at 1680mA and goes to a maximum of 4480mA with increments of
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110mA.
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(Default) 2.46 Amps
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- cirrus,amp-gain-zc : Boolean to determine if to use Amplifier gain-change
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zero-cross
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Optional H/G Algorithm sub-node:
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The cs35l35 node can have a single "cirrus,classh-internal-algo" sub-node
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that will disable automatic control of the internal H/G Algorithm.
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It is strongly recommended that the Datasheet be referenced when adjusting
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or using these Class H Algorithm controls over the internal Algorithm.
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Serious damage can occur to the Device and surrounding components.
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- cirrus,classh-internal-algo : Sub-node for the Internal Class H Algorithm
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See Section 4.3 Internal Class H Algorithm in the Datasheet.
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If not used, the device manages the ClassH Algorithm internally.
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Optional properties for the "cirrus,classh-internal-algo" Sub-node
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Section 7.29 Class H Control
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- cirrus,classh-bst-overide : Boolean
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- cirrus,classh-bst-max-limit
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- cirrus,classh-mem-depth
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Section 7.30 Class H Headroom Control
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- cirrus,classh-headroom
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Section 7.31 Class H Release Rate
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- cirrus,classh-release-rate
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Section 7.32 Class H Weak FET Drive Control
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- cirrus,classh-wk-fet-disable
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- cirrus,classh-wk-fet-delay
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- cirrus,classh-wk-fet-thld
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Section 7.34 Class H VP Control
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- cirrus,classh-vpch-auto
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- cirrus,classh-vpch-rate
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- cirrus,classh-vpch-man
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Optional Monitor Signal Format sub-node:
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The cs35l35 node can have a single "cirrus,monitor-signal-format" sub-node
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for adjusting the Depth, Location and Frame of the Monitoring Signals
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for Algorithms.
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See Sections 4.8.2 through 4.8.4 Serial-Port Control in the Datasheet
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-cirrus,monitor-signal-format : Sub-node for the Monitor Signaling Formating
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on the I2S Port. Each of the 3 8 bit values in the array contain the settings
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for depth, location, and frame.
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If not used, the defaults for the 6 monitor signals is used.
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Sections 7.44 - 7.53 lists values for the depth, location, and frame
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for each monitoring signal.
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- cirrus,imon : 4 8 bit values to set the depth, location, frame and ADC
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scale of the IMON monitor signal.
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- cirrus,vmon : 3 8 bit values to set the depth, location, and frame
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of the VMON monitor signal.
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- cirrus,vpmon : 3 8 bit values to set the depth, location, and frame
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of the VPMON monitor signal.
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- cirrus,vbstmon : 3 8 bit values to set the depth, location, and frame
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of the VBSTMON monitor signal
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- cirrus,vpbrstat : 3 8 bit values to set the depth, location, and frame
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of the VPBRSTAT monitor signal
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- cirrus,zerofill : 3 8 bit values to set the depth, location, and frame\
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of the ZEROFILL packet in the monitor signal
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Example:
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cs35l35: cs35l35@20 {
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compatible = "cirrus,cs35l35";
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reg = <0x20>;
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VA-supply = <&dummy_vreg>;
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VP-supply = <&dummy_vreg>;
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reset-gpios = <&axi_gpio 54 0>;
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interrupt-parent = <&gpio8>;
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interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
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cirrus,boost-ctl-millivolt = <9000>;
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cirrus,stereo-config;
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cirrus,audio-channel = <0x00>;
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cirrus,advisory-channel = <0x01>;
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cirrus,shared-boost;
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cirrus,classh-internal-algo {
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cirrus,classh-bst-overide;
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cirrus,classh-bst-max-limit = <0x01>;
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cirrus,classh-mem-depth = <0x01>;
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cirrus,classh-release-rate = <0x08>;
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cirrus,classh-headroom-millivolt = <0x0B>;
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cirrus,classh-wk-fet-disable = <0x01>;
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cirrus,classh-wk-fet-delay = <0x04>;
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cirrus,classh-wk-fet-thld = <0x01>;
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cirrus,classh-vpch-auto = <0x01>;
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cirrus,classh-vpch-rate = <0x02>;
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cirrus,classh-vpch-man = <0x05>;
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};
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/* Depth, Location, Frame */
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cirrus,monitor-signal-format {
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cirrus,imon = /bits/ 8 <0x03 0x00 0x01>;
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cirrus,vmon = /bits/ 8 <0x03 0x00 0x00>;
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cirrus,vpmon = /bits/ 8 <0x03 0x04 0x00>;
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cirrus,vbstmon = /bits/ 8 <0x03 0x04 0x01>;
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cirrus,vpbrstat = /bits/ 8 <0x00 0x04 0x00>;
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cirrus,zerofill = /bits/ 8 <0x00 0x00 0x00>;
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};
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};
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@ -0,0 +1,12 @@
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DIO2125 Audio Driver
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Required properties:
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- compatible : "dioo,dio2125"
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- enable-gpios : the gpio connected to the enable pin of the dio2125
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Example:
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amp: analog-amplifier {
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compatible = "dioo,dio2125";
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enable-gpios = <&gpio GPIOH_3 0>;
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};
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@ -0,0 +1,108 @@
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/*
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* linux/sound/cs35l35.h -- Platform data for CS35l35
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*
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* Copyright (c) 2016 Cirrus Logic Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __CS35L35_H
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#define __CS35L35_H
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struct classh_cfg {
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/*
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* Class H Algorithm Control Variables
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* You can either have it done
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* automatically or you can adjust
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* these variables for tuning
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*
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* if you do not enable the internal algorithm
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* you will get a set of mixer controls for
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* Class H tuning
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*
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* Section 4.3 of the datasheet
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*/
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bool classh_bst_override;
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bool classh_algo_enable;
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int classh_bst_max_limit;
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int classh_mem_depth;
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int classh_release_rate;
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int classh_headroom;
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int classh_wk_fet_disable;
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int classh_wk_fet_delay;
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int classh_wk_fet_thld;
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int classh_vpch_auto;
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int classh_vpch_rate;
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int classh_vpch_man;
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};
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struct monitor_cfg {
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/*
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* Signal Monitor Data
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* highly configurable signal monitoring
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* data positioning and different types of
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* monitoring data.
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*
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* Section 4.8.2 - 4.8.4 of the datasheet
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*/
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bool is_present;
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bool imon_specs;
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bool vmon_specs;
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bool vpmon_specs;
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bool vbstmon_specs;
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bool vpbrstat_specs;
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bool zerofill_specs;
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u8 imon_dpth;
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u8 imon_loc;
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u8 imon_frm;
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u8 imon_scale;
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u8 vmon_dpth;
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u8 vmon_loc;
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u8 vmon_frm;
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u8 vpmon_dpth;
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u8 vpmon_loc;
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u8 vpmon_frm;
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u8 vbstmon_dpth;
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u8 vbstmon_loc;
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u8 vbstmon_frm;
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u8 vpbrstat_dpth;
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u8 vpbrstat_loc;
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u8 vpbrstat_frm;
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u8 zerofill_dpth;
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u8 zerofill_loc;
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u8 zerofill_frm;
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};
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struct cs35l35_platform_data {
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/* Stereo (2 Device) */
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bool stereo;
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/* serial port drive strength */
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int sp_drv_str;
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/* serial port drive in unused slots */
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int sp_drv_unused;
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/* Boost Power Down with FET */
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bool bst_pdn_fet_on;
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/* Boost Voltage : used if ClassH Algo Enabled */
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int bst_vctl;
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/* Boost Converter Peak Current CTRL */
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int bst_ipk;
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/* Amp Gain Zero Cross */
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bool gain_zc;
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/* Audio Input Location */
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int aud_channel;
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/* Advisory Input Location */
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int adv_channel;
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/* Shared Boost for stereo */
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bool shared_bst;
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/* Specifies this amp is using an external boost supply */
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bool ext_bst;
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/* ClassH Algorithm */
|
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struct classh_cfg classh_algo;
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/* Monitor Config */
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struct monitor_cfg mon_cfg;
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};
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#endif /* __CS35L35_H */
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@ -49,6 +49,7 @@ config SND_SOC_ALL_CODECS
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|||
select SND_SOC_CS35L32 if I2C
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||||
select SND_SOC_CS35L33 if I2C
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||||
select SND_SOC_CS35L34 if I2C
|
||||
select SND_SOC_CS35L35 if I2C
|
||||
select SND_SOC_CS42L42 if I2C
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select SND_SOC_CS42L51_I2C if I2C
|
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select SND_SOC_CS42L52 if I2C && INPUT
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|
|
@ -69,6 +70,7 @@ config SND_SOC_ALL_CODECS
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select SND_SOC_DA7219 if I2C
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select SND_SOC_DA732X if I2C
|
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select SND_SOC_DA9055 if I2C
|
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select SND_SOC_DIO2125
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select SND_SOC_DMIC
|
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select SND_SOC_ES8328_SPI if SPI_MASTER
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select SND_SOC_ES8328_I2C if I2C
|
||||
|
|
@ -410,6 +412,10 @@ config SND_SOC_CS35L34
|
|||
tristate "Cirrus Logic CS35L34 CODEC"
|
||||
depends on I2C
|
||||
|
||||
config SND_SOC_CS35L35
|
||||
tristate "Cirrus Logic CS35L35 CODEC"
|
||||
depends on I2C
|
||||
|
||||
config SND_SOC_CS42L42
|
||||
tristate "Cirrus Logic CS42L42 CODEC"
|
||||
depends on I2C
|
||||
|
|
@ -518,6 +524,10 @@ config SND_SOC_DA732X
|
|||
config SND_SOC_DA9055
|
||||
tristate
|
||||
|
||||
config SND_SOC_DIO2125
|
||||
tristate "Dioo DIO2125 Amplifier"
|
||||
select GPIOLIB
|
||||
|
||||
config SND_SOC_DMIC
|
||||
tristate
|
||||
|
||||
|
|
|
|||
|
|
@ -39,6 +39,7 @@ snd-soc-cq93vc-objs := cq93vc.o
|
|||
snd-soc-cs35l32-objs := cs35l32.o
|
||||
snd-soc-cs35l33-objs := cs35l33.o
|
||||
snd-soc-cs35l34-objs := cs35l34.o
|
||||
snd-soc-cs35l35-objs := cs35l35.o
|
||||
snd-soc-cs42l42-objs := cs42l42.o
|
||||
snd-soc-cs42l51-objs := cs42l51.o
|
||||
snd-soc-cs42l51-i2c-objs := cs42l51-i2c.o
|
||||
|
|
@ -221,6 +222,7 @@ snd-soc-wm9712-objs := wm9712.o
|
|||
snd-soc-wm9713-objs := wm9713.o
|
||||
snd-soc-wm-hubs-objs := wm_hubs.o
|
||||
# Amp
|
||||
snd-soc-dio2125-objs := dio2125.o
|
||||
snd-soc-max9877-objs := max9877.o
|
||||
snd-soc-max98504-objs := max98504.o
|
||||
snd-soc-tpa6130a2-objs := tpa6130a2.o
|
||||
|
|
@ -269,6 +271,7 @@ obj-$(CONFIG_SND_SOC_CQ0093VC) += snd-soc-cq93vc.o
|
|||
obj-$(CONFIG_SND_SOC_CS35L32) += snd-soc-cs35l32.o
|
||||
obj-$(CONFIG_SND_SOC_CS35L33) += snd-soc-cs35l33.o
|
||||
obj-$(CONFIG_SND_SOC_CS35L34) += snd-soc-cs35l34.o
|
||||
obj-$(CONFIG_SND_SOC_CS35L35) += snd-soc-cs35l35.o
|
||||
obj-$(CONFIG_SND_SOC_CS42L42) += snd-soc-cs42l42.o
|
||||
obj-$(CONFIG_SND_SOC_CS42L51) += snd-soc-cs42l51.o
|
||||
obj-$(CONFIG_SND_SOC_CS42L51_I2C) += snd-soc-cs42l51-i2c.o
|
||||
|
|
@ -448,6 +451,7 @@ obj-$(CONFIG_SND_SOC_WM_ADSP) += snd-soc-wm-adsp.o
|
|||
obj-$(CONFIG_SND_SOC_WM_HUBS) += snd-soc-wm-hubs.o
|
||||
|
||||
# Amp
|
||||
obj-$(CONFIG_SND_SOC_DIO2125) += snd-soc-dio2125.o
|
||||
obj-$(CONFIG_SND_SOC_MAX9877) += snd-soc-max9877.o
|
||||
obj-$(CONFIG_SND_SOC_MAX98504) += snd-soc-max98504.o
|
||||
obj-$(CONFIG_SND_SOC_TPA6130A2) += snd-soc-tpa6130a2.o
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,294 @@
|
|||
/*
|
||||
* cs35l35.h -- CS35L35 ALSA SoC audio driver
|
||||
*
|
||||
* Copyright 2016 Cirrus Logic, Inc.
|
||||
*
|
||||
* Author: Brian Austin <brian.austin@cirrus.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __CS35L35_H__
|
||||
#define __CS35L35_H__
|
||||
|
||||
#define CS35L35_FIRSTREG 0x01
|
||||
#define CS35L35_LASTREG 0x7E
|
||||
#define CS35L35_CHIP_ID 0x00035A35
|
||||
#define CS35L35_DEVID_AB 0x01 /* Device ID A & B [RO] */
|
||||
#define CS35L35_DEVID_CD 0x02 /* Device ID C & D [RO] */
|
||||
#define CS35L35_DEVID_E 0x03 /* Device ID E [RO] */
|
||||
#define CS35L35_FAB_ID 0x04 /* Fab ID [RO] */
|
||||
#define CS35L35_REV_ID 0x05 /* Revision ID [RO] */
|
||||
#define CS35L35_PWRCTL1 0x06 /* Power Ctl 1 */
|
||||
#define CS35L35_PWRCTL2 0x07 /* Power Ctl 2 */
|
||||
#define CS35L35_PWRCTL3 0x08 /* Power Ctl 3 */
|
||||
#define CS35L35_CLK_CTL1 0x0A /* Clocking Ctl 1 */
|
||||
#define CS35L35_CLK_CTL2 0x0B /* Clocking Ctl 2 */
|
||||
#define CS35L35_CLK_CTL3 0x0C /* Clocking Ctl 3 */
|
||||
#define CS35L35_SP_FMT_CTL1 0x0D /* Serial Port Format CTL1 */
|
||||
#define CS35L35_SP_FMT_CTL2 0x0E /* Serial Port Format CTL2 */
|
||||
#define CS35L35_SP_FMT_CTL3 0x0F /* Serial Port Format CTL3 */
|
||||
#define CS35L35_MAG_COMP_CTL 0x13 /* Magnitude Comp CTL */
|
||||
#define CS35L35_AMP_INP_DRV_CTL 0x14 /* Amp Input Drive Ctl */
|
||||
#define CS35L35_AMP_DIG_VOL_CTL 0x15 /* Amplifier Dig Volume Ctl */
|
||||
#define CS35L35_AMP_DIG_VOL 0x16 /* Amplifier Dig Volume */
|
||||
#define CS35L35_ADV_DIG_VOL 0x17 /* Advisory Digital Volume */
|
||||
#define CS35L35_PROTECT_CTL 0x18 /* Amp Gain - Prot Ctl Param */
|
||||
#define CS35L35_AMP_GAIN_AUD_CTL 0x19 /* Amp Serial Port Gain Ctl */
|
||||
#define CS35L35_AMP_GAIN_PDM_CTL 0x1A /* Amplifier Gain PDM Ctl */
|
||||
#define CS35L35_AMP_GAIN_ADV_CTL 0x1B /* Amplifier Gain Ctl */
|
||||
#define CS35L35_GPI_CTL 0x1C /* GPI Ctl */
|
||||
#define CS35L35_BST_CVTR_V_CTL 0x1D /* Boost Conv Voltage Ctl */
|
||||
#define CS35L35_BST_PEAK_I 0x1E /* Boost Conv Peak Current */
|
||||
#define CS35L35_BST_RAMP_CTL 0x20 /* Boost Conv Soft Ramp Ctl */
|
||||
#define CS35L35_BST_CONV_COEF_1 0x21 /* Boost Conv Coefficients 1 */
|
||||
#define CS35L35_BST_CONV_COEF_2 0x22 /* Boost Conv Coefficients 2 */
|
||||
#define CS35L35_BST_CONV_SLOPE_COMP 0x23 /* Boost Conv Slope Comp */
|
||||
#define CS35L35_BST_CONV_SW_FREQ 0x24 /* Boost Conv L BST SW Freq */
|
||||
#define CS35L35_CLASS_H_CTL 0x30 /* CLS H Control */
|
||||
#define CS35L35_CLASS_H_HEADRM_CTL 0x31 /* CLS H Headroom Ctl */
|
||||
#define CS35L35_CLASS_H_RELEASE_RATE 0x32 /* CLS H Release Rate */
|
||||
#define CS35L35_CLASS_H_FET_DRIVE_CTL 0x33 /* CLS H Weak FET Drive Ctl */
|
||||
#define CS35L35_CLASS_H_VP_CTL 0x34 /* CLS H VP Ctl */
|
||||
#define CS35L35_CLASS_H_STATUS 0x38 /* CLS H Status */
|
||||
#define CS35L35_VPBR_CTL 0x3A /* VPBR Ctl */
|
||||
#define CS35L35_VPBR_VOL_CTL 0x3B /* VPBR Volume Ctl */
|
||||
#define CS35L35_VPBR_TIMING_CTL 0x3C /* VPBR Timing Ctl */
|
||||
#define CS35L35_VPBR_MODE_VOL_CTL 0x3D /* VPBR Mode/Attack Vol Ctl */
|
||||
#define CS35L35_VPBR_ATTEN_STATUS 0x4B /* VPBR Attenuation Status */
|
||||
#define CS35L35_SPKR_MON_CTL 0x4E /* Speaker Monitoring Ctl */
|
||||
#define CS35L35_IMON_SCALE_CTL 0x51 /* IMON Scale Ctl */
|
||||
#define CS35L35_AUDIN_RXLOC_CTL 0x52 /* Audio Input RX Loc Ctl */
|
||||
#define CS35L35_ADVIN_RXLOC_CTL 0x53 /* Advisory Input RX Loc Ctl */
|
||||
#define CS35L35_VMON_TXLOC_CTL 0x54 /* VMON TX Loc Ctl */
|
||||
#define CS35L35_IMON_TXLOC_CTL 0x55 /* IMON TX Loc Ctl */
|
||||
#define CS35L35_VPMON_TXLOC_CTL 0x56 /* VPMON TX Loc Ctl */
|
||||
#define CS35L35_VBSTMON_TXLOC_CTL 0x57 /* VBSTMON TX Loc Ctl */
|
||||
#define CS35L35_VPBR_STATUS_TXLOC_CTL 0x58 /* VPBR Status TX Loc Ctl */
|
||||
#define CS35L35_ZERO_FILL_LOC_CTL 0x59 /* Zero Fill Loc Ctl */
|
||||
#define CS35L35_AUDIN_DEPTH_CTL 0x5A /* Audio Input Depth Ctl */
|
||||
#define CS35L35_SPKMON_DEPTH_CTL 0x5B /* SPK Mon Output Depth Ctl */
|
||||
#define CS35L35_SUPMON_DEPTH_CTL 0x5C /* Supply Mon Out Depth Ctl */
|
||||
#define CS35L35_ZEROFILL_DEPTH_CTL 0x5D /* Zero Fill Mon Output Ctl */
|
||||
#define CS35L35_MULT_DEV_SYNCH1 0x62 /* Multidevice Synch */
|
||||
#define CS35L35_MULT_DEV_SYNCH2 0x63 /* Multidevice Synch 2 */
|
||||
#define CS35L35_PROT_RELEASE_CTL 0x64 /* Protection Release Ctl */
|
||||
#define CS35L35_DIAG_MODE_REG_LOCK 0x68 /* Diagnostic Mode Reg Lock */
|
||||
#define CS35L35_DIAG_MODE_CTL_1 0x69 /* Diagnostic Mode Ctl 1 */
|
||||
#define CS35L35_DIAG_MODE_CTL_2 0x6A /* Diagnostic Mode Ctl 2 */
|
||||
#define CS35L35_INT_MASK_1 0x70 /* Interrupt Mask 1 */
|
||||
#define CS35L35_INT_MASK_2 0x71 /* Interrupt Mask 2 */
|
||||
#define CS35L35_INT_MASK_3 0x72 /* Interrupt Mask 3 */
|
||||
#define CS35L35_INT_MASK_4 0x73 /* Interrupt Mask 4 */
|
||||
#define CS35L35_INT_STATUS_1 0x74 /* Interrupt Status 1 */
|
||||
#define CS35L35_INT_STATUS_2 0x75 /* Interrupt Status 2 */
|
||||
#define CS35L35_INT_STATUS_3 0x76 /* Interrupt Status 3 */
|
||||
#define CS35L35_INT_STATUS_4 0x77 /* Interrupt Status 4 */
|
||||
#define CS35L35_PLL_STATUS 0x78 /* PLL Status */
|
||||
#define CS35L35_OTP_TRIM_STATUS 0x7E /* OTP Trim Status */
|
||||
|
||||
#define CS35L35_MAX_REGISTER 0x7F
|
||||
|
||||
/* CS35L35_PWRCTL1 */
|
||||
#define CS35L35_SFT_RST 0x80
|
||||
#define CS35L35_DISCHG_FLT 0x02
|
||||
#define CS35L35_PDN_ALL 0x01
|
||||
|
||||
/* CS35L35_PWRCTL2 */
|
||||
#define CS35L35_PDN_VMON 0x80
|
||||
#define CS35L35_PDN_IMON 0x40
|
||||
#define CS35L35_PDN_CLASSH 0x20
|
||||
#define CS35L35_PDN_VPBR 0x10
|
||||
#define CS35L35_PDN_BST 0x04
|
||||
#define CS35L35_PDN_AMP 0x01
|
||||
|
||||
/* CS35L35_PWRCTL3 */
|
||||
#define CS35L35_PDN_VBSTMON_OUT 0x10
|
||||
#define CS35L35_PDN_VMON_OUT 0x08
|
||||
|
||||
#define CS35L35_AUDIN_DEPTH_MASK 0x03
|
||||
#define CS35L35_AUDIN_DEPTH_SHIFT 0
|
||||
#define CS35L35_ADVIN_DEPTH_MASK 0x0C
|
||||
#define CS35L35_ADVIN_DEPTH_SHIFT 2
|
||||
#define CS35L35_SDIN_DEPTH_8 0x01
|
||||
#define CS35L35_SDIN_DEPTH_16 0x02
|
||||
#define CS35L35_SDIN_DEPTH_24 0x03
|
||||
|
||||
#define CS35L35_SDOUT_DEPTH_8 0x01
|
||||
#define CS35L35_SDOUT_DEPTH_12 0x02
|
||||
#define CS35L35_SDOUT_DEPTH_16 0x03
|
||||
|
||||
#define CS35L35_AUD_IN_LR_MASK 0x80
|
||||
#define CS35L35_AUD_IN_LR_SHIFT 7
|
||||
#define CS35L35_ADV_IN_LR_MASK 0x80
|
||||
#define CS35L35_ADV_IN_LR_SHIFT 7
|
||||
#define CS35L35_AUD_IN_LOC_MASK 0x0F
|
||||
#define CS35L35_AUD_IN_LOC_SHIFT 0
|
||||
#define CS35L35_ADV_IN_LOC_MASK 0x0F
|
||||
#define CS35L35_ADV_IN_LOC_SHIFT 0
|
||||
|
||||
#define CS35L35_IMON_DEPTH_MASK 0x03
|
||||
#define CS35L35_IMON_DEPTH_SHIFT 0
|
||||
#define CS35L35_VMON_DEPTH_MASK 0x0C
|
||||
#define CS35L35_VMON_DEPTH_SHIFT 2
|
||||
#define CS35L35_VBSTMON_DEPTH_MASK 0x03
|
||||
#define CS35L35_VBSTMON_DEPTH_SHIFT 0
|
||||
#define CS35L35_VPMON_DEPTH_MASK 0x0C
|
||||
#define CS35L35_VPMON_DEPTH_SHIFT 2
|
||||
#define CS35L35_VPBRSTAT_DEPTH_MASK 0x30
|
||||
#define CS35L35_VPBRSTAT_DEPTH_SHIFT 4
|
||||
#define CS35L35_ZEROFILL_DEPTH_MASK 0x03
|
||||
#define CS35L35_ZEROFILL_DEPTH_SHIFT 0x00
|
||||
|
||||
#define CS35L35_MON_TXLOC_MASK 0x3F
|
||||
#define CS35L35_MON_TXLOC_SHIFT 0
|
||||
#define CS35L35_MON_FRM_MASK 0x80
|
||||
#define CS35L35_MON_FRM_SHIFT 7
|
||||
|
||||
#define CS35L35_IMON_SCALE_MASK 0xF8
|
||||
#define CS35L35_IMON_SCALE_SHIFT 3
|
||||
|
||||
#define CS35L35_MS_MASK 0x80
|
||||
#define CS35L35_MS_SHIFT 7
|
||||
#define CS35L35_SPMODE_MASK 0x40
|
||||
#define CS35L35_SP_DRV_MASK 0x10
|
||||
#define CS35L35_SP_DRV_SHIFT 4
|
||||
#define CS35L35_CLK_CTL2_MASK 0xFF
|
||||
#define CS35L35_PDM_MODE_MASK 0x40
|
||||
#define CS35L35_PDM_MODE_SHIFT 6
|
||||
#define CS35L35_CLK_SOURCE_MASK 0x03
|
||||
#define CS35L35_CLK_SOURCE_SHIFT 0
|
||||
#define CS35L35_CLK_SOURCE_MCLK 0
|
||||
#define CS35L35_CLK_SOURCE_SCLK 1
|
||||
#define CS35L35_CLK_SOURCE_PDM 2
|
||||
|
||||
#define CS35L35_SP_SCLKS_MASK 0x0F
|
||||
#define CS35L35_SP_SCLKS_SHIFT 0x00
|
||||
#define CS35L35_SP_SCLKS_16FS 0x03
|
||||
#define CS35L35_SP_SCLKS_32FS 0x07
|
||||
#define CS35L35_SP_SCLKS_48FS 0x0B
|
||||
#define CS35L35_SP_SCLKS_64FS 0x0F
|
||||
#define CS35L35_SP_RATE_MASK 0xC0
|
||||
|
||||
#define CS35L35_PDN_BST_MASK 0x06
|
||||
#define CS35L35_PDN_BST_FETON_SHIFT 1
|
||||
#define CS35L35_PDN_BST_FETOFF_SHIFT 2
|
||||
#define CS35L35_PWR2_PDN_MASK 0xE0
|
||||
#define CS35L35_PWR3_PDN_MASK 0x1E
|
||||
#define CS35L35_PDN_ALL_MASK 0x01
|
||||
#define CS35L35_DISCHG_FILT_MASK 0x02
|
||||
#define CS35L35_DISCHG_FILT_SHIFT 1
|
||||
#define CS35L35_MCLK_DIS_MASK 0x04
|
||||
#define CS35L35_MCLK_DIS_SHIFT 2
|
||||
|
||||
#define CS35L35_BST_CTL_MASK 0x7F
|
||||
#define CS35L35_BST_CTL_SHIFT 0
|
||||
#define CS35L35_BST_IPK_MASK 0x1F
|
||||
#define CS35L35_BST_IPK_SHIFT 0
|
||||
#define CS35L35_AMP_MUTE_MASK 0x20
|
||||
#define CS35L35_AMP_MUTE_SHIFT 5
|
||||
#define CS35L35_AMP_GAIN_ZC_MASK 0x10
|
||||
#define CS35L35_AMP_GAIN_ZC_SHIFT 4
|
||||
|
||||
#define CS35L35_AMP_DIGSFT_MASK 0x02
|
||||
#define CS35L35_AMP_DIGSFT_SHIFT 1
|
||||
|
||||
/* CS35L35_SP_FMT_CTL3 */
|
||||
#define CS35L35_SP_I2S_DRV_MASK 0x03
|
||||
#define CS35L35_SP_I2S_DRV_SHIFT 0
|
||||
|
||||
/* Class H Algorithm Control */
|
||||
#define CS35L35_CH_STEREO_MASK 0x40
|
||||
#define CS35L35_CH_STEREO_SHIFT 6
|
||||
#define CS35L35_CH_BST_OVR_MASK 0x04
|
||||
#define CS35L35_CH_BST_OVR_SHIFT 2
|
||||
#define CS35L35_CH_BST_LIM_MASK 0x08
|
||||
#define CS35L35_CH_BST_LIM_SHIFT 3
|
||||
#define CS35L35_CH_MEM_DEPTH_MASK 0x01
|
||||
#define CS35L35_CH_MEM_DEPTH_SHIFT 0
|
||||
#define CS35L35_CH_HDRM_CTL_MASK 0x3F
|
||||
#define CS35L35_CH_HDRM_CTL_SHIFT 0
|
||||
#define CS35L35_CH_REL_RATE_MASK 0xFF
|
||||
#define CS35L35_CH_REL_RATE_SHIFT 0
|
||||
#define CS35L35_CH_WKFET_DIS_MASK 0x80
|
||||
#define CS35L35_CH_WKFET_DIS_SHIFT 7
|
||||
#define CS35L35_CH_WKFET_DEL_MASK 0x70
|
||||
#define CS35L35_CH_WKFET_DEL_SHIFT 4
|
||||
#define CS35L35_CH_WKFET_THLD_MASK 0x0F
|
||||
#define CS35L35_CH_WKFET_THLD_SHIFT 0
|
||||
#define CS35L35_CH_VP_AUTO_MASK 0x80
|
||||
#define CS35L35_CH_VP_AUTO_SHIFT 7
|
||||
#define CS35L35_CH_VP_RATE_MASK 0x60
|
||||
#define CS35L35_CH_VP_RATE_SHIFT 5
|
||||
#define CS35L35_CH_VP_MAN_MASK 0x1F
|
||||
#define CS35L35_CH_VP_MAN_SHIFT 0
|
||||
|
||||
/* CS35L35_PROT_RELEASE_CTL */
|
||||
#define CS35L35_CAL_ERR_RLS 0x80
|
||||
#define CS35L35_SHORT_RLS 0x04
|
||||
#define CS35L35_OTW_RLS 0x02
|
||||
#define CS35L35_OTE_RLS 0x01
|
||||
|
||||
/* INT Mask Registers */
|
||||
#define CS35L35_INT1_CRIT_MASK 0x38
|
||||
#define CS35L35_INT2_CRIT_MASK 0xEF
|
||||
#define CS35L35_INT3_CRIT_MASK 0xEE
|
||||
#define CS35L35_INT4_CRIT_MASK 0xFF
|
||||
|
||||
/* PDN DONE Masks */
|
||||
#define CS35L35_M_PDN_DONE_SHIFT 4
|
||||
#define CS35L35_M_PDN_DONE_MASK 0x10
|
||||
|
||||
/* CS35L35_INT_1 */
|
||||
#define CS35L35_CAL_ERR 0x80
|
||||
#define CS35L35_OTP_ERR 0x40
|
||||
#define CS35L35_LRCLK_ERR 0x20
|
||||
#define CS35L35_SPCLK_ERR 0x10
|
||||
#define CS35L35_MCLK_ERR 0x08
|
||||
#define CS35L35_AMP_SHORT 0x04
|
||||
#define CS35L35_OTW 0x02
|
||||
#define CS35L35_OTE 0x01
|
||||
|
||||
/* CS35L35_INT_2 */
|
||||
#define CS35L35_PDN_DONE 0x10
|
||||
#define CS35L35_VPBR_ERR 0x02
|
||||
#define CS35L35_VPBR_CLR 0x01
|
||||
|
||||
/* CS35L35_INT_3 */
|
||||
#define CS35L35_BST_HIGH 0x10
|
||||
#define CS35L35_BST_HIGH_FLAG 0x08
|
||||
#define CS35L35_BST_IPK_FLAG 0x04
|
||||
#define CS35L35_LBST_SHORT 0x01
|
||||
|
||||
/* CS35L35_INT_4 */
|
||||
#define CS35L35_VMON_OVFL 0x08
|
||||
#define CS35L35_IMON_OVFL 0x04
|
||||
|
||||
#define CS35L35_FORMATS (SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | \
|
||||
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
|
||||
|
||||
struct cs35l35_private {
|
||||
struct device *dev;
|
||||
struct cs35l35_platform_data pdata;
|
||||
struct regmap *regmap;
|
||||
struct regulator_bulk_data supplies[2];
|
||||
int num_supplies;
|
||||
int sysclk;
|
||||
int sclk;
|
||||
bool pdm_mode;
|
||||
bool i2s_mode;
|
||||
bool slave_mode;
|
||||
/* GPIO for /RST */
|
||||
struct gpio_desc *reset_gpio;
|
||||
struct completion pdn_done;
|
||||
};
|
||||
|
||||
static const char * const cs35l35_supplies[] = {
|
||||
"VA",
|
||||
"VP",
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -1130,6 +1130,7 @@ MODULE_DEVICE_TABLE(i2c, cs53l30_id);
|
|||
static struct i2c_driver cs53l30_i2c_driver = {
|
||||
.driver = {
|
||||
.name = "cs53l30",
|
||||
.of_match_table = cs53l30_of_match,
|
||||
.pm = &cs53l30_runtime_pm,
|
||||
},
|
||||
.id_table = cs53l30_id,
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/acpi.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/i2c.h>
|
||||
|
|
@ -1528,12 +1529,23 @@ static int da7213_set_bias_level(struct snd_soc_codec *codec,
|
|||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF)
|
||||
/* DT */
|
||||
static const struct of_device_id da7213_of_match[] = {
|
||||
{ .compatible = "dlg,da7213", },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, da7213_of_match);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ACPI
|
||||
static const struct acpi_device_id da7213_acpi_match[] = {
|
||||
{ "DLGS7212", 0},
|
||||
{ "DLGS7213", 0},
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(acpi, da7213_acpi_match);
|
||||
#endif
|
||||
|
||||
static enum da7213_micbias_voltage
|
||||
da7213_of_micbias_lvl(struct snd_soc_codec *codec, u32 val)
|
||||
|
|
@ -1844,6 +1856,7 @@ static struct i2c_driver da7213_i2c_driver = {
|
|||
.driver = {
|
||||
.name = "da7213",
|
||||
.of_match_table = of_match_ptr(da7213_of_match),
|
||||
.acpi_match_table = ACPI_PTR(da7213_acpi_match),
|
||||
},
|
||||
.probe = da7213_i2c_probe,
|
||||
.remove = da7213_remove,
|
||||
|
|
|
|||
|
|
@ -0,0 +1,120 @@
|
|||
/*
|
||||
* Copyright (c) 2017 BayLibre, SAS.
|
||||
* Author: Jerome Brunet <jbrunet@baylibre.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, see <http://www.gnu.org/licenses/>.
|
||||
* The full GNU General Public License is included in this distribution
|
||||
* in the file called COPYING.
|
||||
*/
|
||||
|
||||
#include <linux/gpio/consumer.h>
|
||||
#include <linux/module.h>
|
||||
#include <sound/soc.h>
|
||||
|
||||
#define DRV_NAME "dio2125"
|
||||
|
||||
struct dio2125 {
|
||||
struct gpio_desc *gpiod_enable;
|
||||
};
|
||||
|
||||
static int drv_event(struct snd_soc_dapm_widget *w,
|
||||
struct snd_kcontrol *control, int event)
|
||||
{
|
||||
struct snd_soc_component *c = snd_soc_dapm_to_component(w->dapm);
|
||||
struct dio2125 *priv = snd_soc_component_get_drvdata(c);
|
||||
int val;
|
||||
|
||||
switch (event) {
|
||||
case SND_SOC_DAPM_POST_PMU:
|
||||
val = 1;
|
||||
break;
|
||||
case SND_SOC_DAPM_PRE_PMD:
|
||||
val = 0;
|
||||
break;
|
||||
default:
|
||||
WARN(1, "Unexpected event");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
gpiod_set_value_cansleep(priv->gpiod_enable, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct snd_soc_dapm_widget dio2125_dapm_widgets[] = {
|
||||
SND_SOC_DAPM_INPUT("INL"),
|
||||
SND_SOC_DAPM_INPUT("INR"),
|
||||
SND_SOC_DAPM_OUT_DRV_E("DRV", SND_SOC_NOPM, 0, 0, NULL, 0, drv_event,
|
||||
(SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD)),
|
||||
SND_SOC_DAPM_OUTPUT("OUTL"),
|
||||
SND_SOC_DAPM_OUTPUT("OUTR"),
|
||||
};
|
||||
|
||||
static const struct snd_soc_dapm_route dio2125_dapm_routes[] = {
|
||||
{ "DRV", NULL, "INL" },
|
||||
{ "DRV", NULL, "INR" },
|
||||
{ "OUTL", NULL, "DRV" },
|
||||
{ "OUTR", NULL, "DRV" },
|
||||
};
|
||||
|
||||
static const struct snd_soc_component_driver dio2125_component_driver = {
|
||||
.dapm_widgets = dio2125_dapm_widgets,
|
||||
.num_dapm_widgets = ARRAY_SIZE(dio2125_dapm_widgets),
|
||||
.dapm_routes = dio2125_dapm_routes,
|
||||
.num_dapm_routes = ARRAY_SIZE(dio2125_dapm_routes),
|
||||
};
|
||||
|
||||
static int dio2125_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct dio2125 *priv;
|
||||
int err;
|
||||
|
||||
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (priv == NULL)
|
||||
return -ENOMEM;
|
||||
platform_set_drvdata(pdev, priv);
|
||||
|
||||
priv->gpiod_enable = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
|
||||
if (IS_ERR(priv->gpiod_enable)) {
|
||||
err = PTR_ERR(priv->gpiod_enable);
|
||||
if (err != -EPROBE_DEFER)
|
||||
dev_err(dev, "Failed to get 'enable' gpio: %d", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
return devm_snd_soc_register_component(dev, &dio2125_component_driver,
|
||||
NULL, 0);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
static const struct of_device_id dio2125_ids[] = {
|
||||
{ .compatible = "dioo,dio2125", },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, dio2125_ids);
|
||||
#endif
|
||||
|
||||
static struct platform_driver dio2125_driver = {
|
||||
.driver = {
|
||||
.name = DRV_NAME,
|
||||
.of_match_table = of_match_ptr(dio2125_ids),
|
||||
},
|
||||
.probe = dio2125_probe,
|
||||
};
|
||||
|
||||
module_platform_driver(dio2125_driver);
|
||||
|
||||
MODULE_DESCRIPTION("ASoC DIO2125 output driver");
|
||||
MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -8,10 +8,10 @@ config SND_DESIGNWARE_I2S
|
|||
maximum of 8 channels each for play and record.
|
||||
|
||||
config SND_DESIGNWARE_PCM
|
||||
tristate "PCM PIO extension for I2S driver"
|
||||
bool "PCM PIO extension for I2S driver"
|
||||
depends on SND_DESIGNWARE_I2S
|
||||
help
|
||||
Say Y, M or N if you want to add a custom ALSA extension that registers
|
||||
Say Y or N if you want to add a custom ALSA extension that registers
|
||||
a PCM and uses PIO to transfer data.
|
||||
|
||||
This functionality is specially suited for I2S devices that don't have
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
# SYNOPSYS Platform Support
|
||||
obj-$(CONFIG_SND_DESIGNWARE_I2S) += designware_i2s.o
|
||||
ifdef CONFIG_SND_DESIGNWARE_PCM
|
||||
obj-$(CONFIG_SND_DESIGNWARE_I2S) += designware_pcm.o
|
||||
endif
|
||||
|
||||
designware_i2s-y := dwc-i2s.o
|
||||
designware_i2s-$(CONFIG_SND_DESIGNWARE_PCM) += dwc-pcm.o
|
||||
|
|
|
|||
|
|
@ -129,13 +129,11 @@ void dw_pcm_push_tx(struct dw_i2s_dev *dev)
|
|||
{
|
||||
dw_pcm_transfer(dev, true);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(dw_pcm_push_tx);
|
||||
|
||||
void dw_pcm_pop_rx(struct dw_i2s_dev *dev)
|
||||
{
|
||||
dw_pcm_transfer(dev, false);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(dw_pcm_pop_rx);
|
||||
|
||||
static int dw_pcm_open(struct snd_pcm_substream *substream)
|
||||
{
|
||||
|
|
@ -281,4 +279,3 @@ int dw_pcm_register(struct platform_device *pdev)
|
|||
{
|
||||
return devm_snd_soc_register_platform(&pdev->dev, &dw_pcm_platform);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(dw_pcm_register);
|
||||
Loading…
Reference in New Issue