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Merge branch 'devel-stable' into for-linus 

Conflicts:
	arch/arm/Kconfig
	arch/arm/mach-ns9xxx/include/mach/uncompress.h
This commit is contained in:
Russell King 2011-05-23 19:28:04 +01:00
parent ec19628d72 dc7ad3b3d5
commit 9a55d9752d
212 changed files with 3861 additions and 7712 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/Kconfig
View File

@ -469,7 +469,7 @@ config ARCH_IXP4XX
config ARCH_DOVE
bool "Marvell Dove"
select CPU_V6K
select CPU_V7
select PCI
select ARCH_REQUIRE_GPIOLIB
select GENERIC_CLOCKEVENTS
@ -850,6 +850,7 @@ config ARCH_DAVINCI
select HAVE_IDE
select CLKDEV_LOOKUP
select GENERIC_ALLOCATOR
select GENERIC_IRQ_CHIP
select ARCH_HAS_HOLES_MEMORYMODEL
help
Support for TI's DaVinci platform.
@ -1027,6 +1028,7 @@ config PLAT_IOP
config PLAT_ORION
bool
select CLKSRC_MMIO
select GENERIC_IRQ_CHIP
select HAVE_SCHED_CLOCK
config PLAT_PXA

3
arch/arm/Makefile
View File

@ -158,9 +158,8 @@ machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0
machine-$(CONFIG_ARCH_MX1) := imx
machine-$(CONFIG_ARCH_MX2) := imx
machine-$(CONFIG_ARCH_MX25) := imx
machine-$(CONFIG_ARCH_MX3) := mx3
machine-$(CONFIG_ARCH_MX3) := imx
machine-$(CONFIG_ARCH_MX5) := mx5
machine-$(CONFIG_ARCH_MXC91231) := mxc91231
machine-$(CONFIG_ARCH_MXS) := mxs
machine-$(CONFIG_ARCH_NETX) := netx
machine-$(CONFIG_ARCH_NOMADIK) := nomadik

17
arch/arm/boot/compressed/Makefile
View File

@ -98,8 +98,6 @@ endif
ccflags-y := -fpic -fno-builtin
asflags-y := -Wa,-march=all
# Provide size of uncompressed kernel to the decompressor via a linker symbol.
LDFLAGS_vmlinux = --defsym _image_size=$(shell stat -c "%s" $(obj)/../Image)
# Supply ZRELADDR to the decompressor via a linker symbol.
ifneq ($(CONFIG_AUTO_ZRELADDR),y)
LDFLAGS_vmlinux += --defsym zreladdr=$(ZRELADDR)
@ -122,10 +120,23 @@ lib1funcs = $(obj)/lib1funcs.o
$(obj)/lib1funcs.S: $(srctree)/arch/$(SRCARCH)/lib/lib1funcs.S FORCE
$(call cmd,shipped)
# We need to prevent any GOTOFF relocs being used with references
# to symbols in the .bss section since we cannot relocate them
# independently from the rest at run time. This can be achieved by
# ensuring that no private .bss symbols exist, as global symbols
# always have a GOT entry which is what we need.
# The .data section is already discarded by the linker script so no need
# to bother about it here.
check_for_bad_syms = \
bad_syms=$$($(CROSS_COMPILE)nm $@ | sed -n 's/^.\{8\} [bc] \(.*\)/\1/p') && \
[ -z "$$bad_syms" ] || \
( echo "following symbols must have non local/private scope:" >&2; \
echo "$$bad_syms" >&2; rm -f $@; false )
$(obj)/vmlinux: $(obj)/vmlinux.lds $(obj)/$(HEAD) $(obj)/piggy.$(suffix_y).o \
$(addprefix $(obj)/, $(OBJS)) $(lib1funcs) FORCE
$(call if_changed,ld)
@:
@$(check_for_bad_syms)
$(obj)/piggy.$(suffix_y): $(obj)/../Image FORCE
$(call if_changed,$(suffix_y))

4
arch/arm/boot/compressed/decompress.c
View File

@ -44,7 +44,7 @@ extern void error(char *);
#include "../../../../lib/decompress_unlzma.c"
#endif
void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x))
int do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x))
{
decompress(input, len, NULL, NULL, output, NULL, error);
return decompress(input, len, NULL, NULL, output, NULL, error);
}

30
arch/arm/boot/compressed/head.S
View File

@ -179,7 +179,7 @@ not_angel:
bl cache_on
restart: adr r0, LC0
ldmia r0, {r1, r2, r3, r6, r9, r11, r12}
ldmia r0, {r1, r2, r3, r6, r10, r11, r12}
ldr sp, [r0, #28]
/*
@ -188,6 +188,20 @@ restart: adr r0, LC0
*/
sub r0, r0, r1 @ calculate the delta offset
add r6, r6, r0 @ _edata
add r10, r10, r0 @ inflated kernel size location
/*
* The kernel build system appends the size of the
* decompressed kernel at the end of the compressed data
* in little-endian form.
*/
ldrb r9, [r10, #0]
ldrb lr, [r10, #1]
orr r9, r9, lr, lsl #8
ldrb lr, [r10, #2]
ldrb r10, [r10, #3]
orr r9, r9, lr, lsl #16
orr r9, r9, r10, lsl #24
#ifndef CONFIG_ZBOOT_ROM
/* malloc space is above the relocated stack (64k max) */
@ -347,10 +361,10 @@ LC0: .word LC0 @ r1
.word __bss_start @ r2
.word _end @ r3
.word _edata @ r6
.word _image_size @ r9
.word input_data_end - 4 @ r10 (inflated size location)
.word _got_start @ r11
.word _got_end @ ip
.word user_stack_end @ sp
.word .L_user_stack_end @ sp
.size LC0, . - LC0
#ifdef CONFIG_ARCH_RPC
@ -763,12 +777,6 @@ proc_types:
W(b) __armv4_mmu_cache_off
W(b) __armv6_mmu_cache_flush
.word 0x560f5810 @ Marvell PJ4 ARMv6
.word 0xff0ffff0
W(b) __armv4_mmu_cache_on
W(b) __armv4_mmu_cache_off
W(b) __armv6_mmu_cache_flush
.word 0x000f0000 @ new CPU Id
.word 0x000f0000
W(b) __armv7_mmu_cache_on
@ -1094,5 +1102,5 @@ reloc_code_end:
.align
.section ".stack", "aw", %nobits
user_stack: .space 4096
user_stack_end:
.L_user_stack: .space 4096
.L_user_stack_end:

24
arch/arm/boot/compressed/misc.c
View File

@ -26,8 +26,6 @@ unsigned int __machine_arch_type;
#include <linux/linkage.h>
#include <asm/string.h>
#include <asm/unaligned.h>
static void putstr(const char *ptr);
extern void error(char *x);
@ -139,13 +137,12 @@ void *memcpy(void *__dest, __const void *__src, size_t __n)
}
/*
* gzip delarations
* gzip declarations
*/
extern char input_data[];
extern char input_data_end[];
unsigned char *output_data;
unsigned long output_ptr;
unsigned long free_mem_ptr;
unsigned long free_mem_end_ptr;
@ -170,15 +167,15 @@ asmlinkage void __div0(void)
error("Attempting division by 0!");
}
extern void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x));
extern int do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x));
unsigned long
void
decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
unsigned long free_mem_ptr_end_p,
int arch_id)
{
unsigned char *tmp;
int ret;
output_data = (unsigned char *)output_start;
free_mem_ptr = free_mem_ptr_p;
@ -187,12 +184,11 @@ decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
arch_decomp_setup();
tmp = (unsigned char *) (((unsigned long)input_data_end) - 4);
output_ptr = get_unaligned_le32(tmp);
putstr("Uncompressing Linux...");
do_decompress(input_data, input_data_end - input_data,
output_data, error);
putstr(" done, booting the kernel.\n");
return output_ptr;
ret = do_decompress(input_data, input_data_end - input_data,
output_data, error);
if (ret)
error("decompressor returned an error");
else
putstr(" done, booting the kernel.\n");
}

84
arch/arm/common/gic.c
View File

@ -49,7 +49,7 @@ struct gic_chip_data {
* Default make them NULL.
*/
struct irq_chip gic_arch_extn = {
.irq_ack = NULL,
.irq_eoi = NULL,
.irq_mask = NULL,
.irq_unmask = NULL,
.irq_retrigger = NULL,
@ -84,21 +84,12 @@ static inline unsigned int gic_irq(struct irq_data *d)
/*
* Routines to acknowledge, disable and enable interrupts
*/
static void gic_ack_irq(struct irq_data *d)
{
spin_lock(&irq_controller_lock);
if (gic_arch_extn.irq_ack)
gic_arch_extn.irq_ack(d);
writel(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
spin_unlock(&irq_controller_lock);
}
static void gic_mask_irq(struct irq_data *d)
{
u32 mask = 1 << (d->irq % 32);
spin_lock(&irq_controller_lock);
writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
if (gic_arch_extn.irq_mask)
gic_arch_extn.irq_mask(d);
spin_unlock(&irq_controller_lock);
@ -111,10 +102,21 @@ static void gic_unmask_irq(struct irq_data *d)
spin_lock(&irq_controller_lock);
if (gic_arch_extn.irq_unmask)
gic_arch_extn.irq_unmask(d);
writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
spin_unlock(&irq_controller_lock);
}
static void gic_eoi_irq(struct irq_data *d)
{
if (gic_arch_extn.irq_eoi) {
spin_lock(&irq_controller_lock);
gic_arch_extn.irq_eoi(d);
spin_unlock(&irq_controller_lock);
}
writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
}
static int gic_set_type(struct irq_data *d, unsigned int type)
{
void __iomem *base = gic_dist_base(d);
@ -138,7 +140,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
if (gic_arch_extn.irq_set_type)
gic_arch_extn.irq_set_type(d, type);
val = readl(base + GIC_DIST_CONFIG + confoff);
val = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
if (type == IRQ_TYPE_LEVEL_HIGH)
val &= ~confmask;
else if (type == IRQ_TYPE_EDGE_RISING)
@ -148,15 +150,15 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
* As recommended by the spec, disable the interrupt before changing
* the configuration
*/
if (readl(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
writel(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
enabled = true;
}
writel(val, base + GIC_DIST_CONFIG + confoff);
writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);
if (enabled)
writel(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
spin_unlock(&irq_controller_lock);
@ -188,8 +190,8 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
spin_lock(&irq_controller_lock);
d->node = cpu;
val = readl(reg) & ~mask;
writel(val | bit, reg);
val = readl_relaxed(reg) & ~mask;
writel_relaxed(val | bit, reg);
spin_unlock(&irq_controller_lock);
return 0;
@ -218,11 +220,10 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
unsigned int cascade_irq, gic_irq;
unsigned long status;
/* primary controller ack'ing */
chip->irq_ack(&desc->irq_data);
chained_irq_enter(chip, desc);
spin_lock(&irq_controller_lock);
status = readl(chip_data->cpu_base + GIC_CPU_INTACK);
status = readl_relaxed(chip_data->cpu_base + GIC_CPU_INTACK);
spin_unlock(&irq_controller_lock);
gic_irq = (status & 0x3ff);
@ -236,15 +237,14 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
generic_handle_irq(cascade_irq);
out:
/* primary controller unmasking */
chip->irq_unmask(&desc->irq_data);
chained_irq_exit(chip, desc);
}
static struct irq_chip gic_chip = {
.name = "GIC",
.irq_ack = gic_ack_irq,
.irq_mask = gic_mask_irq,
.irq_unmask = gic_unmask_irq,
.irq_eoi = gic_eoi_irq,
.irq_set_type = gic_set_type,
.irq_retrigger = gic_retrigger,
#ifdef CONFIG_SMP
@ -272,13 +272,13 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
cpumask |= cpumask << 8;
cpumask |= cpumask << 16;
writel(0, base + GIC_DIST_CTRL);
writel_relaxed(0, base + GIC_DIST_CTRL);
/*
* Find out how many interrupts are supported.
* The GIC only supports up to 1020 interrupt sources.
*/
gic_irqs = readl(base + GIC_DIST_CTR) & 0x1f;
gic_irqs = readl_relaxed(base + GIC_DIST_CTR) & 0x1f;
gic_irqs = (gic_irqs + 1) * 32;
if (gic_irqs > 1020)
gic_irqs = 1020;
@ -287,26 +287,26 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
* Set all global interrupts to be level triggered, active low.
*/
for (i = 32; i < gic_irqs; i += 16)
writel(0, base + GIC_DIST_CONFIG + i * 4 / 16);
writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16);
/*
* Set all global interrupts to this CPU only.
*/
for (i = 32; i < gic_irqs; i += 4)
writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
/*
* Set priority on all global interrupts.
*/
for (i = 32; i < gic_irqs; i += 4)
writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
/*
* Disable all interrupts. Leave the PPI and SGIs alone
* as these enables are banked registers.
*/
for (i = 32; i < gic_irqs; i += 32)
writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
/*
* Limit number of interrupts registered to the platform maximum
@ -319,12 +319,12 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
* Setup the Linux IRQ subsystem.
*/
for (i = irq_start; i < irq_limit; i++) {
irq_set_chip_and_handler(i, &gic_chip, handle_level_irq);
irq_set_chip_and_handler(i, &gic_chip, handle_fasteoi_irq);
irq_set_chip_data(i, gic);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
writel(1, base + GIC_DIST_CTRL);
writel_relaxed(1, base + GIC_DIST_CTRL);
}
static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
@ -337,17 +337,17 @@ static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
* Deal with the banked PPI and SGI interrupts - disable all
* PPI interrupts, ensure all SGI interrupts are enabled.
*/
writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
/*
* Set priority on PPI and SGI interrupts
*/
for (i = 0; i < 32; i += 4)
writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
writel(0xf0, base + GIC_CPU_PRIMASK);
writel(1, base + GIC_CPU_CTRL);
writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
writel_relaxed(1, base + GIC_CPU_CTRL);
}
void __init gic_init(unsigned int gic_nr, unsigned int irq_start,
@ -391,7 +391,13 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
{
unsigned long map = *cpus_addr(*mask);
/*
* Ensure that stores to Normal memory are visible to the
* other CPUs before issuing the IPI.
*/
dsb();
/* this always happens on GIC0 */
writel(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
writel_relaxed(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
}
#endif

12
arch/arm/configs/dove_defconfig
View File

@ -8,8 +8,6 @@ CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_DOVE=y
CONFIG_MACH_DOVE_DB=y
CONFIG_CPU_V6=y
CONFIG_CPU_32v6K=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_AEABI=y
@ -44,7 +42,6 @@ CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=1
# CONFIG_MISC_DEVICES is not set
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y
# CONFIG_SCSI_LOWLEVEL is not set
@ -59,12 +56,12 @@ CONFIG_INPUT_EVDEV=y
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_MOUSE_PS2 is not set
# CONFIG_SERIO is not set
CONFIG_LEGACY_PTY_COUNT=16
# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_SERIAL_8250_PCI is not set
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
CONFIG_LEGACY_PTY_COUNT=16
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
@ -72,12 +69,10 @@ CONFIG_I2C_MV64XXX=y
CONFIG_SPI=y
CONFIG_SPI_ORION=y
# CONFIG_HWMON is not set
# CONFIG_VGA_CONSOLE is not set
CONFIG_USB=y
CONFIG_USB_DEVICEFS=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_ROOT_HUB_TT=y
CONFIG_USB_EHCI_TT_NEWSCHED=y
CONFIG_USB_STORAGE=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_MV=y
@ -86,7 +81,6 @@ CONFIG_MV_XOR=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
# CONFIG_EXT3_FS_XATTR is not set
CONFIG_INOTIFY=y
CONFIG_ISO9660_FS=y
CONFIG_JOLIET=y
CONFIG_UDF_FS=m
@ -110,23 +104,19 @@ CONFIG_DEBUG_KERNEL=y
CONFIG_TIMER_STATS=y
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DEBUG_INFO=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_ERRORS=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_ECB=m
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_MD4=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_BLOWFISH=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_TEA=y
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_DEFLATE=y

1
arch/arm/configs/mx1_defconfig
View File

@ -15,6 +15,7 @@ CONFIG_ARCH_MXC=y
CONFIG_ARCH_MX1=y
CONFIG_ARCH_MX1ADS=y
CONFIG_MACH_SCB9328=y
CONFIG_MACH_APF9328=y
CONFIG_MXC_IRQ_PRIOR=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y

2
arch/arm/configs/mx51_defconfig
View File

@ -13,7 +13,7 @@ CONFIG_MODULE_SRCVERSION_ALL=y
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_MXC=y
CONFIG_ARCH_MX5=y
CONFIG_ARCH_MX51=y
CONFIG_MACH_MX51_BABBAGE=y
CONFIG_MACH_MX51_3DS=y
CONFIG_MACH_EUKREA_CPUIMX51=y

5
arch/arm/mach-davinci/include/mach/uncompress.h
View File

@ -25,8 +25,7 @@
#include <mach/serial.h>
static u32 *uart;
static u32 *uart_info = (u32 *)(DAVINCI_UART_INFO);
u32 *uart;
/* PORT_16C550A, in polled non-fifo mode */
static void putc(char c)
@ -44,6 +43,8 @@ static inline void flush(void)
static inline void set_uart_info(u32 phys, void * __iomem virt)
{
u32 *uart_info = (u32 *)(DAVINCI_UART_INFO);
uart = (u32 *)phys;
uart_info[0] = phys;
uart_info[1] = (u32)virt;

89
arch/arm/mach-davinci/irq.c
View File

@ -29,8 +29,6 @@
#include <mach/common.h>
#include <asm/mach/irq.h>
#define IRQ_BIT(irq) ((irq) & 0x1f)
#define FIQ_REG0_OFFSET 0x0000
#define FIQ_REG1_OFFSET 0x0004
#define IRQ_REG0_OFFSET 0x0008
@ -42,78 +40,33 @@
#define IRQ_INTPRI0_REG_OFFSET 0x0030
#define IRQ_INTPRI7_REG_OFFSET 0x004C
static inline unsigned int davinci_irq_readl(int offset)
{
return __raw_readl(davinci_intc_base + offset);
}
static inline void davinci_irq_writel(unsigned long value, int offset)
{
__raw_writel(value, davinci_intc_base + offset);
}
/* Disable interrupt */
static void davinci_mask_irq(struct irq_data *d)
static __init void
davinci_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
{
unsigned int mask;
u32 l;
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
mask = 1 << IRQ_BIT(d->irq);
gc = irq_alloc_generic_chip("AINTC", 1, irq_start, base, handle_edge_irq);
ct = gc->chip_types;
ct->chip.irq_ack = irq_gc_ack;
ct->chip.irq_mask = irq_gc_mask_clr_bit;
ct->chip.irq_unmask = irq_gc_mask_set_bit;
if (d->irq > 31) {
l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
l &= ~mask;
davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
} else {
l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
l &= ~mask;
davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
}
ct->regs.ack = IRQ_REG0_OFFSET;
ct->regs.mask = IRQ_ENT_REG0_OFFSET;
irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
IRQ_NOREQUEST | IRQ_NOPROBE, 0);
}
/* Enable interrupt */
static void davinci_unmask_irq(struct irq_data *d)
{
unsigned int mask;
u32 l;
mask = 1 << IRQ_BIT(d->irq);
if (d->irq > 31) {
l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
l |= mask;
davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
} else {
l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
l |= mask;
davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
}
}
/* EOI interrupt */
static void davinci_ack_irq(struct irq_data *d)
{
unsigned int mask;
mask = 1 << IRQ_BIT(d->irq);
if (d->irq > 31)
davinci_irq_writel(mask, IRQ_REG1_OFFSET);
else
davinci_irq_writel(mask, IRQ_REG0_OFFSET);
}
static struct irq_chip davinci_irq_chip_0 = {
.name = "AINTC",
.irq_ack = davinci_ack_irq,
.irq_mask = davinci_mask_irq,
.irq_unmask = davinci_unmask_irq,
};
/* ARM Interrupt Controller Initialization */
void __init davinci_irq_init(void)
{
unsigned i;
unsigned i, j;
const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios;
davinci_intc_type = DAVINCI_INTC_TYPE_AINTC;
@ -144,7 +97,6 @@ void __init davinci_irq_init(void)
davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) {
unsigned j;
u32 pri;
for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++)
@ -152,13 +104,8 @@ void __init davinci_irq_init(void)
davinci_irq_writel(pri, i);
}
/* set up genirq dispatch for ARM INTC */
for (i = 0; i < davinci_soc_info.intc_irq_num; i++) {
irq_set_chip(i, &davinci_irq_chip_0);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
if (i != IRQ_TINT1_TINT34)
irq_set_handler(i, handle_edge_irq);
else
irq_set_handler(i, handle_level_irq);
}
for (i = 0, j = 0; i < davinci_soc_info.intc_irq_num; i += 32, j += 0x04)
davinci_alloc_gc(davinci_intc_base + j, i, 32);
irq_set_handler(IRQ_TINT1_TINT34, handle_level_irq);
}

616
arch/arm/mach-dove/common.c
View File

@ -16,10 +16,8 @@
#include <linux/serial_8250.h>
#include <linux/clk.h>
#include <linux/mbus.h>
#include <linux/mv643xx_eth.h>
#include <linux/mv643xx_i2c.h>
#include <linux/ata_platform.h>
#include <linux/spi/orion_spi.h>
#include <linux/serial_8250.h>
#include <linux/gpio.h>
#include <asm/page.h>
#include <asm/setup.h>
@ -32,11 +30,12 @@
#include <mach/bridge-regs.h>
#include <asm/mach/arch.h>
#include <linux/irq.h>
#include <plat/mv_xor.h>
#include <plat/ehci-orion.h>
#include <plat/time.h>
#include <plat/common.h>
#include "common.h"
static int get_tclk(void);
/*****************************************************************************
* I/O Address Mapping
****************************************************************************/
@ -69,464 +68,107 @@ void __init dove_map_io(void)
iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
}
/*****************************************************************************
* EHCI
****************************************************************************/
static struct orion_ehci_data dove_ehci_data = {
.dram = &dove_mbus_dram_info,
.phy_version = EHCI_PHY_NA,
};
static u64 ehci_dmamask = DMA_BIT_MASK(32);
/*****************************************************************************
* EHCI0
****************************************************************************/
static struct resource dove_ehci0_resources[] = {
{
.start = DOVE_USB0_PHYS_BASE,
.end = DOVE_USB0_PHYS_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_DOVE_USB0,
.end = IRQ_DOVE_USB0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dove_ehci0 = {
.name = "orion-ehci",
.id = 0,
.dev = {
.dma_mask = &ehci_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &dove_ehci_data,
},
.resource = dove_ehci0_resources,
.num_resources = ARRAY_SIZE(dove_ehci0_resources),
};
void __init dove_ehci0_init(void)
{
platform_device_register(&dove_ehci0);
orion_ehci_init(&dove_mbus_dram_info,
DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0);
}
/*****************************************************************************
* EHCI1
****************************************************************************/
static struct resource dove_ehci1_resources[] = {
{
.start = DOVE_USB1_PHYS_BASE,
.end = DOVE_USB1_PHYS_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_DOVE_USB1,
.end = IRQ_DOVE_USB1,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dove_ehci1 = {
.name = "orion-ehci",
.id = 1,
.dev = {
.dma_mask = &ehci_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &dove_ehci_data,
},
.resource = dove_ehci1_resources,
.num_resources = ARRAY_SIZE(dove_ehci1_resources),
};
void __init dove_ehci1_init(void)
{
platform_device_register(&dove_ehci1);
orion_ehci_1_init(&dove_mbus_dram_info,
DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
}
/*****************************************************************************
* GE00
****************************************************************************/
struct mv643xx_eth_shared_platform_data dove_ge00_shared_data = {
.t_clk = 0,
.dram = &dove_mbus_dram_info,
};
static struct resource dove_ge00_shared_resources[] = {
{
.name = "ge00 base",
.start = DOVE_GE00_PHYS_BASE + 0x2000,
.end = DOVE_GE00_PHYS_BASE + SZ_16K - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device dove_ge00_shared = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 0,
.dev = {
.platform_data = &dove_ge00_shared_data,
},
.num_resources = 1,
.resource = dove_ge00_shared_resources,
};
static struct resource dove_ge00_resources[] = {
{
.name = "ge00 irq",
.start = IRQ_DOVE_GE00_SUM,
.end = IRQ_DOVE_GE00_SUM,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dove_ge00 = {
.name = MV643XX_ETH_NAME,
.id = 0,
.num_resources = 1,
.resource = dove_ge00_resources,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
{
eth_data->shared = &dove_ge00_shared;
dove_ge00.dev.platform_data = eth_data;
platform_device_register(&dove_ge00_shared);
platform_device_register(&dove_ge00);
orion_ge00_init(eth_data, &dove_mbus_dram_info,
DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM,
0, get_tclk());
}
/*****************************************************************************
* SoC RTC
****************************************************************************/
static struct resource dove_rtc_resource[] = {
{
.start = DOVE_RTC_PHYS_BASE,
.end = DOVE_RTC_PHYS_BASE + 32 - 1,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_DOVE_RTC,
.flags = IORESOURCE_IRQ,
}
};
void __init dove_rtc_init(void)
{
platform_device_register_simple("rtc-mv", -1, dove_rtc_resource, 2);
orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
}
/*****************************************************************************
* SATA
****************************************************************************/
static struct resource dove_sata_resources[] = {
{
.name = "sata base",
.start = DOVE_SATA_PHYS_BASE,
.end = DOVE_SATA_PHYS_BASE + 0x5000 - 1,
.flags = IORESOURCE_MEM,
}, {
.name = "sata irq",
.start = IRQ_DOVE_SATA,
.end = IRQ_DOVE_SATA,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dove_sata = {
.name = "sata_mv",
.id = 0,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(dove_sata_resources),
.resource = dove_sata_resources,
};
void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
{
sata_data->dram = &dove_mbus_dram_info;
dove_sata.dev.platform_data = sata_data;
platform_device_register(&dove_sata);
orion_sata_init(sata_data, &dove_mbus_dram_info,
DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
}
/*****************************************************************************
* UART0
****************************************************************************/
static struct plat_serial8250_port dove_uart0_data[] = {
{
.mapbase = DOVE_UART0_PHYS_BASE,
.membase = (char *)DOVE_UART0_VIRT_BASE,
.irq = IRQ_DOVE_UART_0,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = 0,
}, {
},
};
static struct resource dove_uart0_resources[] = {
{
.start = DOVE_UART0_PHYS_BASE,
.end = DOVE_UART0_PHYS_BASE + SZ_256 - 1,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_DOVE_UART_0,
.end = IRQ_DOVE_UART_0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dove_uart0 = {
.name = "serial8250",
.id = 0,
.dev = {
.platform_data = dove_uart0_data,
},
.resource = dove_uart0_resources,
.num_resources = ARRAY_SIZE(dove_uart0_resources),
};
void __init dove_uart0_init(void)
{
platform_device_register(&dove_uart0);
orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
IRQ_DOVE_UART_0, get_tclk());
}
/*****************************************************************************
* UART1
****************************************************************************/
static struct plat_serial8250_port dove_uart1_data[] = {
{
.mapbase = DOVE_UART1_PHYS_BASE,
.membase = (char *)DOVE_UART1_VIRT_BASE,
.irq = IRQ_DOVE_UART_1,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = 0,
}, {
},
};
static struct resource dove_uart1_resources[] = {
{
.start = DOVE_UART1_PHYS_BASE,
.end = DOVE_UART1_PHYS_BASE + SZ_256 - 1,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_DOVE_UART_1,
.end = IRQ_DOVE_UART_1,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dove_uart1 = {
.name = "serial8250",
.id = 1,
.dev = {
.platform_data = dove_uart1_data,
},
.resource = dove_uart1_resources,
.num_resources = ARRAY_SIZE(dove_uart1_resources),
};
void __init dove_uart1_init(void)
{
platform_device_register(&dove_uart1);
orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
IRQ_DOVE_UART_1, get_tclk());
}
/*****************************************************************************
* UART2
****************************************************************************/
static struct plat_serial8250_port dove_uart2_data[] = {
{
.mapbase = DOVE_UART2_PHYS_BASE,
.membase = (char *)DOVE_UART2_VIRT_BASE,
.irq = IRQ_DOVE_UART_2,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = 0,
}, {
},
};
static struct resource dove_uart2_resources[] = {
{
.start = DOVE_UART2_PHYS_BASE,
.end = DOVE_UART2_PHYS_BASE + SZ_256 - 1,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_DOVE_UART_2,
.end = IRQ_DOVE_UART_2,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dove_uart2 = {
.name = "serial8250",
.id = 2,
.dev = {
.platform_data = dove_uart2_data,
},
.resource = dove_uart2_resources,
.num_resources = ARRAY_SIZE(dove_uart2_resources),
};
void __init dove_uart2_init(void)
{
platform_device_register(&dove_uart2);
orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
IRQ_DOVE_UART_2, get_tclk());
}
/*****************************************************************************
* UART3
****************************************************************************/
static struct plat_serial8250_port dove_uart3_data[] = {
{
.mapbase = DOVE_UART3_PHYS_BASE,
.membase = (char *)DOVE_UART3_VIRT_BASE,
.irq = IRQ_DOVE_UART_3,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = 0,
}, {
},
};
static struct resource dove_uart3_resources[] = {
{
.start = DOVE_UART3_PHYS_BASE,
.end = DOVE_UART3_PHYS_BASE + SZ_256 - 1,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_DOVE_UART_3,
.end = IRQ_DOVE_UART_3,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dove_uart3 = {
.name = "serial8250",
.id = 3,
.dev = {
.platform_data = dove_uart3_data,
},
.resource = dove_uart3_resources,
.num_resources = ARRAY_SIZE(dove_uart3_resources),
};
void __init dove_uart3_init(void)
{
platform_device_register(&dove_uart3);
orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
IRQ_DOVE_UART_3, get_tclk());
}
/*****************************************************************************
* SPI0
* SPI
****************************************************************************/
static struct orion_spi_info dove_spi0_data = {
.tclk = 0,
};
static struct resource dove_spi0_resources[] = {
{
.start = DOVE_SPI0_PHYS_BASE,
.end = DOVE_SPI0_PHYS_BASE + SZ_512 - 1,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_DOVE_SPI0,
.end = IRQ_DOVE_SPI0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dove_spi0 = {
.name = "orion_spi",
.id = 0,
.resource = dove_spi0_resources,
.dev = {
.platform_data = &dove_spi0_data,
},
.num_resources = ARRAY_SIZE(dove_spi0_resources),
};
void __init dove_spi0_init(void)
{
platform_device_register(&dove_spi0);
orion_spi_init(DOVE_SPI0_PHYS_BASE, get_tclk());
}
/*****************************************************************************
* SPI1
****************************************************************************/
static struct orion_spi_info dove_spi1_data = {
.tclk = 0,
};
static struct resource dove_spi1_resources[] = {
{
.start = DOVE_SPI1_PHYS_BASE,
.end = DOVE_SPI1_PHYS_BASE + SZ_512 - 1,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_DOVE_SPI1,
.end = IRQ_DOVE_SPI1,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dove_spi1 = {
.name = "orion_spi",
.id = 1,
.resource = dove_spi1_resources,
.dev = {
.platform_data = &dove_spi1_data,
},
.num_resources = ARRAY_SIZE(dove_spi1_resources),
};
void __init dove_spi1_init(void)
{
platform_device_register(&dove_spi1);
orion_spi_init(DOVE_SPI1_PHYS_BASE, get_tclk());
}
/*****************************************************************************
* I2C
****************************************************************************/
static struct mv64xxx_i2c_pdata dove_i2c_data = {
.freq_m = 10, /* assumes 166 MHz TCLK gets 94.3kHz */
.freq_n = 3,
.timeout = 1000, /* Default timeout of 1 second */
};
static struct resource dove_i2c_resources[] = {
{
.name = "i2c base",
.start = DOVE_I2C_PHYS_BASE,
.end = DOVE_I2C_PHYS_BASE + 0x20 - 1,
.flags = IORESOURCE_MEM,
}, {
.name = "i2c irq",
.start = IRQ_DOVE_I2C,
.end = IRQ_DOVE_I2C,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dove_i2c = {
.name = MV64XXX_I2C_CTLR_NAME,
.id = 0,
.num_resources = ARRAY_SIZE(dove_i2c_resources),
.resource = dove_i2c_resources,
.dev = {
.platform_data = &dove_i2c_data,
},
};
void __init dove_i2c_init(void)
{
platform_device_register(&dove_i2c);
orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
}
/*****************************************************************************
@ -553,209 +195,23 @@ struct sys_timer dove_timer = {
.init = dove_timer_init,
};
/*****************************************************************************
* XOR
****************************************************************************/
static struct mv_xor_platform_shared_data dove_xor_shared_data = {
.dram = &dove_mbus_dram_info,
};
/*****************************************************************************
* XOR 0
****************************************************************************/
static u64 dove_xor0_dmamask = DMA_BIT_MASK(32);
static struct resource dove_xor0_shared_resources[] = {
{
.name = "xor 0 low",
.start = DOVE_XOR0_PHYS_BASE,
.end = DOVE_XOR0_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
}, {
.name = "xor 0 high",
.start = DOVE_XOR0_HIGH_PHYS_BASE,
.end = DOVE_XOR0_HIGH_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device dove_xor0_shared = {
.name = MV_XOR_SHARED_NAME,
.id = 0,
.dev = {
.platform_data = &dove_xor_shared_data,
},
.num_resources = ARRAY_SIZE(dove_xor0_shared_resources),
.resource = dove_xor0_shared_resources,
};
static struct resource dove_xor00_resources[] = {
[0] = {
.start = IRQ_DOVE_XOR_00,
.end = IRQ_DOVE_XOR_00,
.flags = IORESOURCE_IRQ,
},
};
static struct mv_xor_platform_data dove_xor00_data = {
.shared = &dove_xor0_shared,
.hw_id = 0,
.pool_size = PAGE_SIZE,
};
static struct platform_device dove_xor00_channel = {
.name = MV_XOR_NAME,
.id = 0,
.num_resources = ARRAY_SIZE(dove_xor00_resources),
.resource = dove_xor00_resources,
.dev = {
.dma_mask = &dove_xor0_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(64),
.platform_data = &dove_xor00_data,
},
};
static struct resource dove_xor01_resources[] = {
[0] = {
.start = IRQ_DOVE_XOR_01,
.end = IRQ_DOVE_XOR_01,
.flags = IORESOURCE_IRQ,
},
};
static struct mv_xor_platform_data dove_xor01_data = {
.shared = &dove_xor0_shared,
.hw_id = 1,
.pool_size = PAGE_SIZE,
};
static struct platform_device dove_xor01_channel = {
.name = MV_XOR_NAME,
.id = 1,
.num_resources = ARRAY_SIZE(dove_xor01_resources),
.resource = dove_xor01_resources,
.dev = {
.dma_mask = &dove_xor0_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(64),
.platform_data = &dove_xor01_data,
},
};
void __init dove_xor0_init(void)
{
platform_device_register(&dove_xor0_shared);
/*
* two engines can't do memset simultaneously, this limitation
* satisfied by removing memset support from one of the engines.
*/
dma_cap_set(DMA_MEMCPY, dove_xor00_data.cap_mask);
dma_cap_set(DMA_XOR, dove_xor00_data.cap_mask);
platform_device_register(&dove_xor00_channel);
dma_cap_set(DMA_MEMCPY, dove_xor01_data.cap_mask);
dma_cap_set(DMA_MEMSET, dove_xor01_data.cap_mask);
dma_cap_set(DMA_XOR, dove_xor01_data.cap_mask);
platform_device_register(&dove_xor01_channel);
orion_xor0_init(&dove_mbus_dram_info,
DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
}
/*****************************************************************************
* XOR 1
****************************************************************************/
static u64 dove_xor1_dmamask = DMA_BIT_MASK(32);
static struct resource dove_xor1_shared_resources[] = {
{
.name = "xor 0 low",
.start = DOVE_XOR1_PHYS_BASE,
.end = DOVE_XOR1_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
}, {
.name = "xor 0 high",
.start = DOVE_XOR1_HIGH_PHYS_BASE,
.end = DOVE_XOR1_HIGH_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device dove_xor1_shared = {
.name = MV_XOR_SHARED_NAME,
.id = 1,
.dev = {
.platform_data = &dove_xor_shared_data,
},
.num_resources = ARRAY_SIZE(dove_xor1_shared_resources),
.resource = dove_xor1_shared_resources,
};
static struct resource dove_xor10_resources[] = {
[0] = {
.start = IRQ_DOVE_XOR_10,
.end = IRQ_DOVE_XOR_10,
.flags = IORESOURCE_IRQ,
},
};
static struct mv_xor_platform_data dove_xor10_data = {
.shared = &dove_xor1_shared,
.hw_id = 0,
.pool_size = PAGE_SIZE,
};
static struct platform_device dove_xor10_channel = {
.name = MV_XOR_NAME,
.id = 2,
.num_resources = ARRAY_SIZE(dove_xor10_resources),
.resource = dove_xor10_resources,
.dev = {
.dma_mask = &dove_xor1_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(64),
.platform_data = &dove_xor10_data,
},
};
static struct resource dove_xor11_resources[] = {
[0] = {
.start = IRQ_DOVE_XOR_11,
.end = IRQ_DOVE_XOR_11,
.flags = IORESOURCE_IRQ,
},
};
static struct mv_xor_platform_data dove_xor11_data = {
.shared = &dove_xor1_shared,
.hw_id = 1,
.pool_size = PAGE_SIZE,
};
static struct platform_device dove_xor11_channel = {
.name = MV_XOR_NAME,
.id = 3,
.num_resources = ARRAY_SIZE(dove_xor11_resources),
.resource = dove_xor11_resources,
.dev = {
.dma_mask = &dove_xor1_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(64),
.platform_data = &dove_xor11_data,
},
};
void __init dove_xor1_init(void)
{
platform_device_register(&dove_xor1_shared);
/*
* two engines can't do memset simultaneously, this limitation
* satisfied by removing memset support from one of the engines.
*/
dma_cap_set(DMA_MEMCPY, dove_xor10_data.cap_mask);
dma_cap_set(DMA_XOR, dove_xor10_data.cap_mask);
platform_device_register(&dove_xor10_channel);
dma_cap_set(DMA_MEMCPY, dove_xor11_data.cap_mask);
dma_cap_set(DMA_MEMSET, dove_xor11_data.cap_mask);
dma_cap_set(DMA_XOR, dove_xor11_data.cap_mask);
platform_device_register(&dove_xor11_channel);
orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
}
/*****************************************************************************
@ -833,14 +289,6 @@ void __init dove_init(void)
#endif
dove_setup_cpu_mbus();
dove_ge00_shared_data.t_clk = tclk;
dove_uart0_data[0].uartclk = tclk;
dove_uart1_data[0].uartclk = tclk;
dove_uart2_data[0].uartclk = tclk;
dove_uart3_data[0].uartclk = tclk;
dove_spi0_data.tclk = tclk;
dove_spi1_data.tclk = tclk;
/* internal devices that every board has */
dove_rtc_init();
dove_xor0_init();

134
arch/arm/mach-dove/mpp.c
View File

@ -11,24 +11,17 @@
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <plat/mpp.h>
#include <mach/dove.h>
#include "mpp.h"
#define MPP_NR_REGS 4
#define MPP_CTRL(i) ((i) == 3 ? \
DOVE_MPP_CTRL4_VIRT_BASE : \
DOVE_MPP_VIRT_BASE + (i) * 4)
#define PMU_SIG_REGS 2
#define PMU_SIG_CTRL(i) (DOVE_PMU_SIG_CTRL + (i) * 4)
struct dove_mpp_grp {
int start;
int end;
};
static struct dove_mpp_grp dove_mpp_grp[] = {
/* Map a group to a range of GPIO pins in that group */
static const struct dove_mpp_grp dove_mpp_grp[] = {
[MPP_24_39] = {
.start = 24,
.end = 39,
@ -38,8 +31,8 @@ static struct dove_mpp_grp dove_mpp_grp[] = {
.end = 45,
},
[MPP_46_51] = {
.start = 40,
.end = 45,
.start = 46,
.end = 51,
},
[MPP_58_61] = {
.start = 58,
@ -51,6 +44,8 @@ static struct dove_mpp_grp dove_mpp_grp[] = {
},
};
/* Enable gpio for a range of pins. mode should be a combination of
GPIO_OUTPUT_OK | GPIO_INPUT_OK */
static void dove_mpp_gpio_mode(int start, int end, int gpio_mode)
{
int i;
@ -59,24 +54,17 @@ static void dove_mpp_gpio_mode(int start, int end, int gpio_mode)
orion_gpio_set_valid(i, gpio_mode);
}
/* Dump all the extra MPP registers. The platform code will dump the
registers for pins 0-23. */
static void dove_mpp_dump_regs(void)
{
#ifdef DEBUG
int i;
pr_debug("PMU_CTRL4_CTRL: %08x\n",
readl(DOVE_MPP_CTRL4_VIRT_BASE));
pr_debug("MPP_CTRL regs:");
for (i = 0; i < MPP_NR_REGS; i++)
printk(" %08x", readl(MPP_CTRL(i)));
printk("\n");
pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n",
readl(DOVE_PMU_MPP_GENERAL_CTRL));
pr_debug("PMU_SIG_CTRL regs:");
for (i = 0; i < PMU_SIG_REGS; i++)
printk(" %08x", readl(PMU_SIG_CTRL(i)));
printk("\n");
pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n", readl(DOVE_PMU_MPP_GENERAL_CTRL));
pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE));
#endif
}
static void dove_mpp_cfg_nfc(int sel)
@ -92,7 +80,7 @@ static void dove_mpp_cfg_nfc(int sel)
static void dove_mpp_cfg_au1(int sel)
{
u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1);
u32 mpp_gen_ctrl = readl(DOVE_MPP_GENERAL_VIRT_BASE);
u32 global_cfg_2 = readl(DOVE_GLOBAL_CONFIG_2);
@ -128,82 +116,46 @@ static void dove_mpp_cfg_au1(int sel)
writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2);
}
static void dove_mpp_conf_grp(int num, int sel, u32 *mpp_ctrl)
/* Configure the group registers, enabling GPIO if sel indicates the
pin is to be used for GPIO */
static void dove_mpp_conf_grp(unsigned int *mpp_grp_list)
{
int start = dove_mpp_grp[num].start;
int end = dove_mpp_grp[num].end;
int gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0;
u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
int gpio_mode;
*mpp_ctrl &= ~(0x1 << num);
*mpp_ctrl |= sel << num;
for ( ; *mpp_grp_list; mpp_grp_list++) {
unsigned int num = MPP_NUM(*mpp_grp_list);
unsigned int sel = MPP_SEL(*mpp_grp_list);
dove_mpp_gpio_mode(start, end, gpio_mode);
}
void __init dove_mpp_conf(unsigned int *mpp_list)
{
u32 mpp_ctrl[MPP_NR_REGS];
u32 pmu_mpp_ctrl = 0;
u32 pmu_sig_ctrl[PMU_SIG_REGS];
int i;
for (i = 0; i < MPP_NR_REGS; i++)
mpp_ctrl[i] = readl(MPP_CTRL(i));
for (i = 0; i < PMU_SIG_REGS; i++)
pmu_sig_ctrl[i] = readl(PMU_SIG_CTRL(i));
pmu_mpp_ctrl = readl(DOVE_PMU_MPP_GENERAL_CTRL);
dove_mpp_dump_regs();
for ( ; *mpp_list != MPP_END; mpp_list++) {
unsigned int num = MPP_NUM(*mpp_list);
unsigned int sel = MPP_SEL(*mpp_list);
int shift, gpio_mode;
if (num > MPP_MAX) {
pr_err("dove: invalid MPP number (%u)\n", num);
if (num > MPP_GRP_MAX) {
pr_err("dove: invalid MPP GRP number (%u)\n", num);
continue;
}
if (*mpp_list & MPP_NFC_MASK) {
dove_mpp_cfg_nfc(sel);
continue;
}
mpp_ctrl4 &= ~(0x1 << num);
mpp_ctrl4 |= sel << num;
if (*mpp_list & MPP_AU1_MASK) {
dove_mpp_cfg_au1(sel);
continue;
}
if (*mpp_list & MPP_GRP_MASK) {
dove_mpp_conf_grp(num, sel, &mpp_ctrl[3]);
continue;
}
shift = (num & 7) << 2;
if (*mpp_list & MPP_PMU_MASK) {
pmu_mpp_ctrl |= (0x1 << num);
pmu_sig_ctrl[num / 8] &= ~(0xf << shift);
pmu_sig_ctrl[num / 8] |= 0xf << shift;
gpio_mode = 0;
} else {
mpp_ctrl[num / 8] &= ~(0xf << shift);
mpp_ctrl[num / 8] |= sel << shift;
gpio_mode = GPIO_OUTPUT_OK | GPIO_INPUT_OK;
}
orion_gpio_set_valid(num, gpio_mode);
gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0;
dove_mpp_gpio_mode(dove_mpp_grp[num].start,
dove_mpp_grp[num].end, gpio_mode);
}
writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE);
}
for (i = 0; i < MPP_NR_REGS; i++)
writel(mpp_ctrl[i], MPP_CTRL(i));
/* Configure the various MPP pins on Dove */
void __init dove_mpp_conf(unsigned int *mpp_list,
unsigned int *mpp_grp_list,
unsigned int grp_au1_52_57,
unsigned int grp_nfc_64_71)
{
dove_mpp_dump_regs();
for (i = 0; i < PMU_SIG_REGS; i++)
writel(pmu_sig_ctrl[i], PMU_SIG_CTRL(i));
/* Use platform code for pins 0-23 */
orion_mpp_conf(mpp_list, 0, MPP_MAX, DOVE_MPP_VIRT_BASE);
writel(pmu_mpp_ctrl, DOVE_PMU_MPP_GENERAL_CTRL);
dove_mpp_conf_grp(mpp_grp_list);
dove_mpp_cfg_au1(grp_au1_52_57);
dove_mpp_cfg_nfc(grp_nfc_64_71);
dove_mpp_dump_regs();
}

308
arch/arm/mach-dove/mpp.h
View File

@ -1,178 +1,150 @@
#ifndef __ARCH_DOVE_MPP_CODED_H
#define __ARCH_DOVE_MPP_CODED_H
#define MPP(_num, _mode, _pmu, _grp, _au1, _nfc) ( \
/* MPP/group number */ ((_num) & 0xff) | \
/* MPP select value */ (((_mode) & 0xf) << 8) | \
/* MPP PMU */ ((!!(_pmu)) << 12) | \
/* group flag */ ((!!(_grp)) << 13) | \
/* AU1 flag */ ((!!(_au1)) << 14) | \
/* NFCE flag */ ((!!(_nfc)) << 15))
#define MPP(_num, _sel, _in, _out) ( \
/* MPP number */ ((_num) & 0xff) | \
/* MPP select value */ (((_sel) & 0xf) << 8) | \
/* may be input signal */ ((!!(_in)) << 12) | \
/* may be output signal */ ((!!(_out)) << 13))
#define MPP_MAX 71
#define MPP0_GPIO0 MPP(0, 0x0, 1, 1)
#define MPP0_UA2_RTSn MPP(0, 0x2, 0, 0)
#define MPP0_SDIO0_CD MPP(0, 0x3, 0, 0)
#define MPP0_LCD0_PWM MPP(0, 0xf, 0, 0)
#define MPP_NUM(x) ((x) & 0xff)
#define MPP_SEL(x) (((x) >> 8) & 0xf)
#define MPP1_GPIO1 MPP(1, 0x0, 1, 1)
#define MPP1_UA2_CTSn MPP(1, 0x2, 0, 0)
#define MPP1_SDIO0_WP MPP(1, 0x3, 0, 0)
#define MPP1_LCD1_PWM MPP(1, 0xf, 0, 0)
#define MPP_PMU_MASK MPP(0, 0x0, 1, 0, 0, 0)
#define MPP_GRP_MASK MPP(0, 0x0, 0, 1, 0, 0)
#define MPP_AU1_MASK MPP(0, 0x0, 0, 0, 1, 0)
#define MPP_NFC_MASK MPP(0, 0x0, 0, 0, 0, 1)
#define MPP2_GPIO2 MPP(2, 0x0, 1, 1)
#define MPP2_SATA_PRESENT MPP(2, 0x1, 0, 0)
#define MPP2_UA2_TXD MPP(2, 0x2, 0, 0)
#define MPP2_SDIO0_BUS_POWER MPP(2, 0x3, 0, 0)
#define MPP2_UA_RTSn1 MPP(2, 0x4, 0, 0)
#define MPP_END MPP(0xff, 0xf, 1, 1, 1, 1)
#define MPP3_GPIO3 MPP(3, 0x0, 1, 1)
#define MPP3_SATA_ACT MPP(3, 0x1, 0, 0)
#define MPP3_UA2_RXD MPP(3, 0x2, 0, 0)
#define MPP3_SDIO0_LED_CTRL MPP(3, 0x3, 0, 0)
#define MPP3_UA_CTSn1 MPP(3, 0x4, 0, 0)
#define MPP3_SPI_LCD_CS1 MPP(3, 0xf, 0, 0)
#define MPP_PMU_DRIVE_0 0x1
#define MPP_PMU_DRIVE_1 0x2
#define MPP_PMU_SDI 0x3
#define MPP_PMU_CPU_PWRDWN 0x4
#define MPP_PMU_STBY_PWRDWN 0x5
#define MPP_PMU_CORE_PWR_GOOD 0x8
#define MPP_PMU_BAT_FAULT 0xa
#define MPP_PMU_EXT0_WU 0xb
#define MPP_PMU_EXT1_WU 0xc
#define MPP_PMU_EXT2_WU 0xd
#define MPP_PMU_BLINK 0xe
#define MPP_PMU(_num, _mode) MPP((_num), MPP_PMU_##_mode, 1, 0, 0, 0)
#define MPP4_GPIO4 MPP(4, 0x0, 1, 1)
#define MPP4_UA3_RTSn MPP(4, 0x2, 0, 0)
#define MPP4_SDIO1_CD MPP(4, 0x3, 0, 0)
#define MPP4_SPI_1_MISO MPP(4, 0x4, 0, 0)
#define MPP_PIN(_num, _mode) MPP((_num), (_mode), 0, 0, 0, 0)
#define MPP_GRP(_grp, _mode) MPP((_grp), (_mode), 0, 1, 0, 0)
#define MPP_GRP_AU1(_mode) MPP(0, (_mode), 0, 0, 1, 0)
#define MPP_GRP_NFC(_mode) MPP(0, (_mode), 0, 0, 0, 1)
#define MPP5_GPIO5 MPP(5, 0x0, 1, 1)
#define MPP5_UA3_CTSn MPP(5, 0x2, 0, 0)
#define MPP5_SDIO1_WP MPP(5, 0x3, 0, 0)
#define MPP5_SPI_1_CS MPP(5, 0x4, 0, 0)
#define MPP0_GPIO0 MPP_PIN(0, 0x0)
#define MPP0_UA2_RTSn MPP_PIN(0, 0x2)
#define MPP0_SDIO0_CD MPP_PIN(0, 0x3)
#define MPP0_LCD0_PWM MPP_PIN(0, 0xf)
#define MPP6_GPIO6 MPP(6, 0x0, 1, 1)
#define MPP6_UA3_TXD MPP(6, 0x2, 0, 0)
#define MPP6_SDIO1_BUS_POWER MPP(6, 0x3, 0, 0)
#define MPP6_SPI_1_MOSI MPP(6, 0x4, 0, 0)
#define MPP1_GPIO1 MPP_PIN(1, 0x0)
#define MPP1_UA2_CTSn MPP_PIN(1, 0x2)
#define MPP1_SDIO0_WP MPP_PIN(1, 0x3)
#define MPP1_LCD1_PWM MPP_PIN(1, 0xf)
#define MPP7_GPIO7 MPP(7, 0x0, 1, 1)
#define MPP7_UA3_RXD MPP(7, 0x2, 0, 0)
#define MPP7_SDIO1_LED_CTRL MPP(7, 0x3, 0, 0)
#define MPP7_SPI_1_SCK MPP(7, 0x4, 0, 0)
#define MPP2_GPIO2 MPP_PIN(2, 0x0)
#define MPP2_SATA_PRESENT MPP_PIN(2, 0x1)
#define MPP2_UA2_TXD MPP_PIN(2, 0x2)
#define MPP2_SDIO0_BUS_POWER MPP_PIN(2, 0x3)
#define MPP2_UA_RTSn1 MPP_PIN(2, 0x4)
#define MPP8_GPIO8 MPP(8, 0x0, 1, 1)
#define MPP8_WD_RST_OUT MPP(8, 0x1, 0, 0)
#define MPP3_GPIO3 MPP_PIN(3, 0x0)
#define MPP3_SATA_ACT MPP_PIN(3, 0x1)
#define MPP3_UA2_RXD MPP_PIN(3, 0x2)
#define MPP3_SDIO0_LED_CTRL MPP_PIN(3, 0x3)
#define MPP3_UA_CTSn1 MPP_PIN(3, 0x4)
#define MPP3_SPI_LCD_CS1 MPP_PIN(3, 0xf)
#define MPP9_GPIO9 MPP(9, 0x0, 1, 1)
#define MPP9_PEX1_CLKREQn MPP(9, 0x5, 0, 0)
#define MPP4_GPIO4 MPP_PIN(4, 0x0)
#define MPP4_UA3_RTSn MPP_PIN(4, 0x2)
#define MPP4_SDIO1_CD MPP_PIN(4, 0x3)
#define MPP4_SPI_1_MISO MPP_PIN(4, 0x4)
#define MPP10_GPIO10 MPP(10, 0x0, 1, 1)
#define MPP10_SSP_SCLK MPP(10, 0x5, 0, 0)
#define MPP5_GPIO5 MPP_PIN(5, 0x0)
#define MPP5_UA3_CTSn MPP_PIN(5, 0x2)
#define MPP5_SDIO1_WP MPP_PIN(5, 0x3)
#define MPP5_SPI_1_CS MPP_PIN(5, 0x4)
#define MPP11_GPIO11 MPP(11, 0x0, 1, 1)
#define MPP11_SATA_PRESENT MPP(11, 0x1, 0, 0)
#define MPP11_SATA_ACT MPP(11, 0x2, 0, 0)
#define MPP11_SDIO0_LED_CTRL MPP(11, 0x3, 0, 0)
#define MPP11_SDIO1_LED_CTRL MPP(11, 0x4, 0, 0)
#define MPP11_PEX0_CLKREQn MPP(11, 0x5, 0, 0)
#define MPP6_GPIO6 MPP_PIN(6, 0x0)
#define MPP6_UA3_TXD MPP_PIN(6, 0x2)
#define MPP6_SDIO1_BUS_POWER MPP_PIN(6, 0x3)
#define MPP6_SPI_1_MOSI MPP_PIN(6, 0x4)
#define MPP12_GPIO12 MPP(12, 0x0, 1, 1)
#define MPP12_SATA_ACT MPP(12, 0x1, 0, 0)
#define MPP12_UA2_RTSn MPP(12, 0x2, 0, 0)
#define MPP12_AD0_I2S_EXT_MCLK MPP(12, 0x3, 0, 0)
#define MPP12_SDIO1_CD MPP(12, 0x4, 0, 0)
#define MPP7_GPIO7 MPP_PIN(7, 0x0)
#define MPP7_UA3_RXD MPP_PIN(7, 0x2)
#define MPP7_SDIO1_LED_CTRL MPP_PIN(7, 0x3)
#define MPP7_SPI_1_SCK MPP_PIN(7, 0x4)
#define MPP13_GPIO13 MPP(13, 0x0, 1, 1)
#define MPP13_UA2_CTSn MPP(13, 0x2, 0, 0)
#define MPP13_AD1_I2S_EXT_MCLK MPP(13, 0x3, 0, 0)
#define MPP13_SDIO1WP MPP(13, 0x4, 0, 0)
#define MPP13_SSP_EXTCLK MPP(13, 0x5, 0, 0)
#define MPP8_GPIO8 MPP_PIN(8, 0x0)
#define MPP8_WD_RST_OUT MPP_PIN(8, 0x1)
#define MPP14_GPIO14 MPP(14, 0x0, 1, 1)
#define MPP14_UA2_TXD MPP(14, 0x2, 0, 0)
#define MPP14_SDIO1_BUS_POWER MPP(14, 0x4, 0, 0)
#define MPP14_SSP_RXD MPP(14, 0x5, 0, 0)
#define MPP9_GPIO9 MPP_PIN(9, 0x0)
#define MPP9_PEX1_CLKREQn MPP_PIN(9, 0x5)
#define MPP15_GPIO15 MPP(15, 0x0, 1, 1)
#define MPP15_UA2_RXD MPP(15, 0x2, 0, 0)
#define MPP15_SDIO1_LED_CTRL MPP(15, 0x4, 0, 0)
#define MPP15_SSP_SFRM MPP(15, 0x5, 0, 0)
#define MPP10_GPIO10 MPP_PIN(10, 0x0)
#define MPP10_SSP_SCLK MPP_PIN(10, 0x5)
#define MPP16_GPIO16 MPP(16, 0x0, 1, 1)
#define MPP16_UA3_RTSn MPP(16, 0x2, 0, 0)
#define MPP16_SDIO0_CD MPP(16, 0x3, 0, 0)
#define MPP16_SPI_LCD_CS1 MPP(16, 0x4, 0, 0)
#define MPP16_AC97_SDATA_IN1 MPP(16, 0x5, 0, 0)
#define MPP11_GPIO11 MPP_PIN(11, 0x0)
#define MPP11_SATA_PRESENT MPP_PIN(11, 0x1)
#define MPP11_SATA_ACT MPP_PIN(11, 0x2)
#define MPP11_SDIO0_LED_CTRL MPP_PIN(11, 0x3)
#define MPP11_SDIO1_LED_CTRL MPP_PIN(11, 0x4)
#define MPP11_PEX0_CLKREQn MPP_PIN(11, 0x5)
#define MPP17_GPIO17 MPP(17, 0x0, 1, 1)
#define MPP17_AC97_SYSCLK_OUT MPP(17, 0x1, 0, 0)
#define MPP17_UA3_CTSn MPP(17, 0x2, 0, 0)
#define MPP17_SDIO0_WP MPP(17, 0x3, 0, 0)
#define MPP17_TW_SDA2 MPP(17, 0x4, 0, 0)
#define MPP17_AC97_SDATA_IN2 MPP(17, 0x5, 0, 0)
#define MPP12_GPIO12 MPP_PIN(12, 0x0)
#define MPP12_SATA_ACT MPP_PIN(12, 0x1)
#define MPP12_UA2_RTSn MPP_PIN(12, 0x2)
#define MPP12_AD0_I2S_EXT_MCLK MPP_PIN(12, 0x3)
#define MPP12_SDIO1_CD MPP_PIN(12, 0x4)
#define MPP18_GPIO18 MPP(18, 0x0, 1, 1)
#define MPP18_UA3_TXD MPP(18, 0x2, 0, 0)
#define MPP18_SDIO0_BUS_POWER MPP(18, 0x3, 0, 0)
#define MPP18_LCD0_PWM MPP(18, 0x4, 0, 0)
#define MPP18_AC_SDATA_IN3 MPP(18, 0x5, 0, 0)
#define MPP13_GPIO13 MPP_PIN(13, 0x0)
#define MPP13_UA2_CTSn MPP_PIN(13, 0x2)
#define MPP13_AD1_I2S_EXT_MCLK MPP_PIN(13, 0x3)
#define MPP13_SDIO1WP MPP_PIN(13, 0x4)
#define MPP13_SSP_EXTCLK MPP_PIN(13, 0x5)
#define MPP19_GPIO19 MPP(19, 0x0, 1, 1)
#define MPP19_UA3_RXD MPP(19, 0x2, 0, 0)
#define MPP19_SDIO0_LED_CTRL MPP(19, 0x3, 0, 0)
#define MPP19_TW_SCK2 MPP(19, 0x4, 0, 0)
#define MPP14_GPIO14 MPP_PIN(14, 0x0)
#define MPP14_UA2_TXD MPP_PIN(14, 0x2)
#define MPP14_SDIO1_BUS_POWER MPP_PIN(14, 0x4)
#define MPP14_SSP_RXD MPP_PIN(14, 0x5)
#define MPP20_GPIO20 MPP(20, 0x0, 1, 1)
#define MPP20_AC97_SYSCLK_OUT MPP(20, 0x1, 0, 0)
#define MPP20_SPI_LCD_MISO MPP(20, 0x2, 0, 0)
#define MPP20_SDIO1_CD MPP(20, 0x3, 0, 0)
#define MPP20_SDIO0_CD MPP(20, 0x5, 0, 0)
#define MPP20_SPI_1_MISO MPP(20, 0x6, 0, 0)
#define MPP15_GPIO15 MPP_PIN(15, 0x0)
#define MPP15_UA2_RXD MPP_PIN(15, 0x2)
#define MPP15_SDIO1_LED_CTRL MPP_PIN(15, 0x4)
#define MPP15_SSP_SFRM MPP_PIN(15, 0x5)
#define MPP21_GPIO21 MPP(21, 0x0, 1, 1)
#define MPP21_UA1_RTSn MPP(21, 0x1, 0, 0)
#define MPP21_SPI_LCD_CS0 MPP(21, 0x2, 0, 0)
#define MPP21_SDIO1_WP MPP(21, 0x3, 0, 0)
#define MPP21_SSP_SFRM MPP(21, 0x4, 0, 0)
#define MPP21_SDIO0_WP MPP(21, 0x5, 0, 0)
#define MPP21_SPI_1_CS MPP(21, 0x6, 0, 0)
#define MPP16_GPIO16 MPP_PIN(16, 0x0)
#define MPP16_UA3_RTSn MPP_PIN(16, 0x2)
#define MPP16_SDIO0_CD MPP_PIN(16, 0x3)
#define MPP16_SPI_LCD_CS1 MPP_PIN(16, 0x4)
#define MPP16_AC97_SDATA_IN1 MPP_PIN(16, 0x5)
#define MPP22_GPIO22 MPP(22, 0x0, 1, 1)
#define MPP22_UA1_CTSn MPP(22, 0x1, 0, 0)
#define MPP22_SPI_LCD_MOSI MPP(22, 0x2, 0, 0)
#define MPP22_SDIO1_BUS_POWER MPP(22, 0x3, 0, 0)
#define MPP22_SSP_TXD MPP(22, 0x4, 0, 0)
#define MPP22_SDIO0_BUS_POWER MPP(22, 0x5, 0, 0)
#define MPP22_SPI_1_MOSI MPP(22, 0x6, 0, 0)
#define MPP17_GPIO17 MPP_PIN(17, 0x0)
#define MPP17_AC97_SYSCLK_OUT MPP_PIN(17, 0x1)
#define MPP17_UA3_CTSn MPP_PIN(17, 0x2)
#define MPP17_SDIO0_WP MPP_PIN(17, 0x3)
#define MPP17_TW_SDA2 MPP_PIN(17, 0x4)
#define MPP17_AC97_SDATA_IN2 MPP_PIN(17, 0x5)
#define MPP23_GPIO23 MPP(23, 0x0, 1, 1)
#define MPP23_SPI_LCD_SCK MPP(23, 0x2, 0, 0)
#define MPP23_SDIO1_LED_CTRL MPP(23, 0x3, 0, 0)
#define MPP23_SSP_SCLK MPP(23, 0x4, 0, 0)
#define MPP23_SDIO0_LED_CTRL MPP(23, 0x5, 0, 0)
#define MPP23_SPI_1_SCK MPP(23, 0x6, 0, 0)
#define MPP18_GPIO18 MPP_PIN(18, 0x0)
#define MPP18_UA3_TXD MPP_PIN(18, 0x2)
#define MPP18_SDIO0_BUS_POWER MPP_PIN(18, 0x3)
#define MPP18_LCD0_PWM MPP_PIN(18, 0x4)
#define MPP18_AC_SDATA_IN3 MPP_PIN(18, 0x5)
#define MPP_MAX 23
#define MPP19_GPIO19 MPP_PIN(19, 0x0)
#define MPP19_UA3_RXD MPP_PIN(19, 0x2)
#define MPP19_SDIO0_LED_CTRL MPP_PIN(19, 0x3)
#define MPP19_TW_SCK2 MPP_PIN(19, 0x4)
#define MPP20_GPIO20 MPP_PIN(20, 0x0)
#define MPP20_AC97_SYSCLK_OUT MPP_PIN(20, 0x1)
#define MPP20_SPI_LCD_MISO MPP_PIN(20, 0x2)
#define MPP20_SDIO1_CD MPP_PIN(20, 0x3)
#define MPP20_SDIO0_CD MPP_PIN(20, 0x5)
#define MPP20_SPI_1_MISO MPP_PIN(20, 0x6)
#define MPP21_GPIO21 MPP_PIN(21, 0x0)
#define MPP21_UA1_RTSn MPP_PIN(21, 0x1)
#define MPP21_SPI_LCD_CS0 MPP_PIN(21, 0x2)
#define MPP21_SDIO1_WP MPP_PIN(21, 0x3)
#define MPP21_SSP_SFRM MPP_PIN(21, 0x4)
#define MPP21_SDIO0_WP MPP_PIN(21, 0x5)
#define MPP21_SPI_1_CS MPP_PIN(21, 0x6)
#define MPP22_GPIO22 MPP_PIN(22, 0x0)
#define MPP22_UA1_CTSn MPP_PIN(22, 0x1)
#define MPP22_SPI_LCD_MOSI MPP_PIN(22, 0x2)
#define MPP22_SDIO1_BUS_POWER MPP_PIN(22, 0x3)
#define MPP22_SSP_TXD MPP_PIN(22, 0x4)
#define MPP22_SDIO0_BUS_POWER MPP_PIN(22, 0x5)
#define MPP22_SPI_1_MOSI MPP_PIN(22, 0x6)
#define MPP23_GPIO23 MPP_PIN(23, 0x0)
#define MPP23_SPI_LCD_SCK MPP_PIN(23, 0x2)
#define MPP23_SDIO1_LED_CTRL MPP_PIN(23, 0x3)
#define MPP23_SSP_SCLK MPP_PIN(23, 0x4)
#define MPP23_SDIO0_LED_CTRL MPP_PIN(23, 0x5)
#define MPP23_SPI_1_SCK MPP_PIN(23, 0x6)
#define MPP_GRP(_grp, _mode) MPP((_grp), (_mode), 0, 0)
/* for MPP groups _num is a group index */
enum dove_mpp_grp_idx {
@ -181,40 +153,44 @@ enum dove_mpp_grp_idx {
MPP_46_51 = 1,
MPP_58_61 = 5,
MPP_62_63 = 4,
MPP_GRP_MAX = 5,
};
#define MPP24_39_GPIO MPP_GRP(MPP_24_39, 0x1)
#define MPP24_39_CAM MPP_GRP(MPP_24_39, 0x0)
#define MPP_GRP_24_39_GPIO MPP_GRP(MPP_24_39, 0x1)
#define MPP_GRP_24_39_CAM MPP_GRP(MPP_24_39, 0x0)
#define MPP40_45_GPIO MPP_GRP(MPP_40_45, 0x1)
#define MPP40_45_SD0 MPP_GRP(MPP_40_45, 0x0)
#define MPP_GRP_40_45_GPIO MPP_GRP(MPP_40_45, 0x1)
#define MPP_GRP_40_45_SD0 MPP_GRP(MPP_40_45, 0x0)
#define MPP46_51_GPIO MPP_GRP(MPP_46_51, 0x1)
#define MPP46_51_SD1 MPP_GRP(MPP_46_51, 0x0)
#define MPP_GRP_46_51_GPIO MPP_GRP(MPP_46_51, 0x1)
#define MPP_GRP_46_51_SD1 MPP_GRP(MPP_46_51, 0x0)
#define MPP58_61_GPIO MPP_GRP(MPP_58_61, 0x1)
#define MPP58_61_SPI MPP_GRP(MPP_58_61, 0x0)
#define MPP_GRP_58_61_GPIO MPP_GRP(MPP_58_61, 0x1)
#define MPP_GRP_58_61_SPI MPP_GRP(MPP_58_61, 0x0)
#define MPP62_63_GPIO MPP_GRP(MPP_62_63, 0x1)
#define MPP62_63_UA1 MPP_GRP(MPP_62_63, 0x0)
#define MPP_GRP_62_63_GPIO MPP_GRP(MPP_62_63, 0x1)
#define MPP_GRP_62_63_UA1 MPP_GRP(MPP_62_63, 0x0)
/* The MPP[64:71] control differs from other groups */
#define MPP64_71_GPO MPP_GRP_NFC(0x1)
#define MPP64_71_NFC MPP_GRP_NFC(0x0)
#define MPP_GRP_NFC_64_71_GPO 0x1
#define MPP_GRP_NFC_64_71_NFC 0x0
/*
* The MPP[52:57] functionality is encoded by 4 bits in different
* registers. The _num field in this case encodes those bits in
* correspodence with Table 135 of 88AP510 Functional specification
*/
#define MPP52_57_AU1 MPP_GRP_AU1(0x0)
#define MPP52_57_AU1_GPIO57 MPP_GRP_AU1(0x2)
#define MPP52_57_GPIO MPP_GRP_AU1(0xa)
#define MPP52_57_TW_GPIO MPP_GRP_AU1(0xb)
#define MPP52_57_AU1_SSP MPP_GRP_AU1(0xc)
#define MPP52_57_SSP_GPIO MPP_GRP_AU1(0xe)
#define MPP52_57_SSP_TW MPP_GRP_AU1(0xf)
#define MPP_GRP_AU1_52_57_AU1 0x0
#define MPP_GRP_AU1_52_57_AU1_GPIO57 0x2
#define MPP_GRP_AU1_52_57_GPIO 0xa
#define MPP_GRP_AU1_52_57_TW_GPIO 0xb
#define MPP_GRP_AU1_52_57_AU1_SSP 0xc
#define MPP_GRP_AU1_52_57_SSP_GPIO 0xe
#define MPP_GRP_AU1_52_57_SSP_TW 0xf
void dove_mpp_conf(unsigned int *mpp_list);
void dove_mpp_conf(unsigned int *mpp_list,
unsigned int *mpp_grp_list,
unsigned int grp_au1_52_57,
unsigned int grp_nfc_64_71);
#endif /* __ARCH_DOVE_MPP_CODED_H */

6
arch/arm/mach-exynos4/irq-combiner.c
View File

@ -59,8 +59,7 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
unsigned int cascade_irq, combiner_irq;
unsigned long status;
/* primary controller ack'ing */
chip->irq_ack(&desc->irq_data);
chained_irq_enter(chip, desc);
spin_lock(&irq_controller_lock);
status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
@ -79,8 +78,7 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
generic_handle_irq(cascade_irq);
out:
/* primary controller unmasking */
chip->irq_unmask(&desc->irq_data);
chained_irq_exit(chip, desc);
}
static struct irq_chip combiner_chip = {

2
arch/arm/mach-gemini/include/mach/uncompress.h
View File

@ -16,7 +16,7 @@
#include <linux/serial_reg.h>
#include <mach/hardware.h>
static volatile unsigned long *UART = (unsigned long *)GEMINI_UART_BASE;
static volatile unsigned long * const UART = (unsigned long *)GEMINI_UART_BASE;
/*
* The following code assumes the serial port has already been

286
arch/arm/mach-imx/Kconfig
View File

@ -1,5 +1,15 @@
config IMX_HAVE_DMA_V1
bool
#
# ARCH_MX31 and ARCH_MX35 are left for compatibility
# Some usages assume that having one of them implies not having (e.g.) ARCH_MX2.
# To easily distinguish good and reviewed from unreviewed usages new (and IMHO
# more sensible) names are used: SOC_IMX31 and SOC_IMX35
config ARCH_MX31
bool
config ARCH_MX35
bool
config SOC_IMX1
bool
@ -31,6 +41,24 @@ config SOC_IMX27
select IMX_HAVE_IOMUX_V1
select MXC_AVIC
config SOC_IMX31
bool
select CPU_V6
select IMX_HAVE_PLATFORM_MXC_RNGA
select ARCH_MXC_AUDMUX_V2
select ARCH_MX31
select MXC_AVIC
config SOC_IMX35
bool
select CPU_V6
select ARCH_MXC_IOMUX_V3
select ARCH_MXC_AUDMUX_V2
select HAVE_EPIT
select ARCH_MX35
select MXC_AVIC
if ARCH_MX1
comment "MX1 platforms:"
@ -40,6 +68,7 @@ config MACH_MXLADS
config ARCH_MX1ADS
bool "MX1ADS platform"
select MACH_MXLADS
select SOC_IMX1
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
help
@ -51,6 +80,13 @@ config MACH_SCB9328
help
Say Y here if you are using a Synertronixx scb9328 board
config MACH_APF9328
bool "APF9328"
select SOC_IMX1
select IMX_HAVE_PLATFORM_IMX_UART
help
Say Yes here if you are using the Armadeus APF9328 development board
endif
if ARCH_MX2
@ -129,6 +165,7 @@ choice
config MACH_EUKREA_MBIMXSD25_BASEBOARD
bool "Eukrea MBIMXSD development board"
select IMX_HAVE_PLATFORM_GPIO_KEYS
select IMX_HAVE_PLATFORM_IMX_SSI
help
This adds board specific devices that can be found on Eukrea's
@ -254,6 +291,7 @@ config MACH_MX27_3DS
config MACH_IMX27_VISSTRIM_M10
bool "Vista Silicon i.MX27 Visstrim_m10"
select SOC_IMX27
select IMX_HAVE_PLATFORM_GPIO_KEYS
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IMX_UART
@ -314,3 +352,251 @@ config MACH_IMX27IPCAM
configurations for the board and its peripherals.
endif
if ARCH_MX3
comment "MX31 platforms:"
config MACH_MX31ADS
bool "Support MX31ADS platforms"
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IMX_UART
default y
help
Include support for MX31ADS platform. This includes specific
configurations for the board and its peripherals.
config MACH_MX31ADS_WM1133_EV1
bool "Support Wolfson Microelectronics 1133-EV1 module"
depends on MACH_MX31ADS
depends on MFD_WM8350_I2C
depends on REGULATOR_WM8350
select MFD_WM8350_CONFIG_MODE_0
select MFD_WM8352_CONFIG_MODE_0
help
Include support for the Wolfson Microelectronics 1133-EV1 PMU
and audio module for the MX31ADS platform.
config MACH_MX31LILLY
bool "Support MX31 LILLY-1131 platforms (INCO startec)"
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_IPU_CORE
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_ULPI if USB_ULPI
help
Include support for mx31 based LILLY1131 modules. This includes
specific configurations for the board and its peripherals.
config MACH_MX31LITE
bool "Support MX31 LITEKIT (LogicPD)"
select SOC_IMX31
select MXC_ULPI if USB_ULPI
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_MXC_RTC
select IMX_HAVE_PLATFORM_SPI_IMX
help
Include support for MX31 LITEKIT platform. This includes specific
configurations for the board and its peripherals.
config MACH_PCM037
bool "Support Phytec pcm037 (i.MX31) platforms"
select SOC_IMX31
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_IPU_CORE
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_MXC_W1
select MXC_ULPI if USB_ULPI
help
Include support for Phytec pcm037 platform. This includes
specific configurations for the board and its peripherals.
config MACH_PCM037_EET
bool "Support pcm037 EET board extensions"
depends on MACH_PCM037
select IMX_HAVE_PLATFORM_GPIO_KEYS
select IMX_HAVE_PLATFORM_SPI_IMX
help
Add support for PCM037 EET baseboard extensions. If you are using the
OLED display with EET, use "video=mx3fb:CMEL-OLED" kernel
command-line parameter.
config MACH_MX31_3DS
bool "Support MX31PDK (3DS)"
select SOC_IMX31
select MXC_DEBUG_BOARD
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_KEYPAD
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_IPU_CORE
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_ULPI if USB_ULPI
help
Include support for MX31PDK (3DS) platform. This includes specific
configurations for the board and its peripherals.
config MACH_MX31_3DS_MXC_NAND_USE_BBT
bool "Make the MXC NAND driver use the in flash Bad Block Table"
depends on MACH_MX31_3DS
depends on MTD_NAND_MXC
help
Enable this if you want that the MXC NAND driver uses the in flash
Bad Block Table to know what blocks are bad instead of scanning the
entire flash looking for bad block markers.
config MACH_MX31MOBOARD
bool "Support mx31moboard platforms (EPFL Mobots group)"
select SOC_IMX31
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_IPU_CORE
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_ULPI if USB_ULPI
help
Include support for mx31moboard platform. This includes specific
configurations for the board and its peripherals.
config MACH_QONG
bool "Support Dave/DENX QongEVB-LITE platform"
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_UART
help
Include support for Dave/DENX QongEVB-LITE platform. This includes
specific configurations for the board and its peripherals.
config MACH_ARMADILLO5X0
bool "Support Atmark Armadillo-500 Development Base Board"
select SOC_IMX31
select IMX_HAVE_PLATFORM_GPIO_KEYS
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_IPU_CORE
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
select MXC_ULPI if USB_ULPI
help
Include support for Atmark Armadillo-500 platform. This includes
specific configurations for the board and its peripherals.
config MACH_KZM_ARM11_01
bool "Support KZM-ARM11-01(Kyoto Microcomputer)"
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_UART
help
Include support for KZM-ARM11-01. This includes specific
configurations for the board and its peripherals.
config MACH_BUG
bool "Support Buglabs BUGBase platform"
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_UART
default y
help
Include support for BUGBase 1.3 platform. This includes specific
configurations for the board and its peripherals.
comment "MX35 platforms:"
config MACH_PCM043
bool "Support Phytec pcm043 (i.MX35) platforms"
select SOC_IMX35
select IMX_HAVE_PLATFORM_FLEXCAN
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_IPU_CORE
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select MXC_ULPI if USB_ULPI
help
Include support for Phytec pcm043 platform. This includes
specific configurations for the board and its peripherals.
config MACH_MX35_3DS
bool "Support MX35PDK platform"
select SOC_IMX35
select MXC_DEBUG_BOARD
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
help
Include support for MX35PDK platform. This includes specific
configurations for the board and its peripherals.
config MACH_EUKREA_CPUIMX35
bool "Support Eukrea CPUIMX35 Platform"
select SOC_IMX35
select IMX_HAVE_PLATFORM_FLEXCAN
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select MXC_ULPI if USB_ULPI
help
Include support for Eukrea CPUIMX35 platform. This includes
specific configurations for the board and its peripherals.
choice
prompt "Baseboard"
depends on MACH_EUKREA_CPUIMX35
default MACH_EUKREA_MBIMXSD35_BASEBOARD
config MACH_EUKREA_MBIMXSD35_BASEBOARD
bool "Eukrea MBIMXSD development board"
select IMX_HAVE_PLATFORM_GPIO_KEYS
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IPU_CORE
help
This adds board specific devices that can be found on Eukrea's
MBIMXSD evaluation board.
endchoice
config MACH_VPR200
bool "Support VPR200 platform"
select SOC_IMX35
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_GPIO_KEYS
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IPU_CORE
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
help
Include support for VPR200 platform. This includes specific
configurations for the board and its peripherals.
endif

40
arch/arm/mach-imx/Makefile
View File

@ -1,9 +1,3 @@
#
# Makefile for the linux kernel.
#
# Object file lists.
obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o
@ -14,18 +8,27 @@ obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o ehci-imx25.o
obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o
obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
# Support for CMOS sensor interface
obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
obj-$(CONFIG_SOC_IMX31) += mm-imx31.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o
obj-$(CONFIG_SOC_IMX35) += mm-imx35.o cpu-imx35.o clock-imx35.o ehci-imx35.o
obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
# Support for CMOS sensor interface
obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
# i.MX1 based machines
obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o
obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
obj-$(CONFIG_MACH_APF9328) += mach-apf9328.o
# i.MX21 based machines
obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
# i.MX25 based machines
obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX25) += mach-eukrea_cpuimx25.o
obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd25-baseboard.o
# i.MX27 based machines
obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
@ -37,3 +40,24 @@ obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o
obj-$(CONFIG_MACH_IMX27IPCAM) += mach-imx27ipcam.o
# i.MX31 based machines
obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o
obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o
obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o
obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o
obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o
obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o
obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \
mx31moboard-marxbot.o mx31moboard-smartbot.o
obj-$(CONFIG_MACH_QONG) += mach-qong.o
obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o
obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o
obj-$(CONFIG_MACH_BUG) += mach-bug.o
# i.MX35 based machines
obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o
obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX35) += mach-cpuimx35.o
obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o
obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o

4
arch/arm/mach-imx/Makefile.boot
View File

@ -13,3 +13,7 @@ initrd_phys-$(CONFIG_ARCH_MX25) := 0x80800000
zreladdr-$(CONFIG_MACH_MX27) := 0xA0008000
params_phys-$(CONFIG_MACH_MX27) := 0xA0000100
initrd_phys-$(CONFIG_MACH_MX27) := 0xA0800000
zreladdr-$(CONFIG_ARCH_MX3) := 0x80008000
params_phys-$(CONFIG_ARCH_MX3) := 0x80000100
initrd_phys-$(CONFIG_ARCH_MX3) := 0x80800000

56
arch/arm/mach-imx/cache-l2x0.c Normal file
View File

@ -0,0 +1,56 @@
/*
* Copyright (C) 2009-2010 Pengutronix
* Sascha Hauer <s.hauer@pengutronix.de>
* Juergen Beisert <j.beisert@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <asm/hardware/cache-l2x0.h>
#include <mach/hardware.h>
static int mxc_init_l2x0(void)
{
void __iomem *l2x0_base;
void __iomem *clkctl_base;
if (!cpu_is_mx31() && !cpu_is_mx35())
return 0;
/*
* First of all, we must repair broken chip settings. There are some
* i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
* misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
* Workaraound is to setup the correct register setting prior enabling the
* L2 cache. This should not hurt already working CPUs, as they are using the
* same value.
*/
#define L2_MEM_VAL 0x10
clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
if (clkctl_base != NULL) {
writel(0x00000515, clkctl_base + L2_MEM_VAL);
iounmap(clkctl_base);
} else {
pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
}
l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
if (IS_ERR(l2x0_base)) {
printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
PTR_ERR(l2x0_base));
return 0;
}
l2x0_init(l2x0_base, 0x00030024, 0x00000000);
return 0;
}
arch_initcall(mxc_init_l2x0);

3
arch/arm/mach-mx3/clock-imx31.c → arch/arm/mach-imx/clock-imx31.c
View File

@ -32,7 +32,7 @@
#include <mach/mx31.h>
#include <mach/common.h>
#include "crm_regs.h"
#include "crmregs-imx31.h"
#define PRE_DIV_MIN_FREQ 10000000 /* Minimum Frequency after Predivider */
@ -627,4 +627,3 @@ int __init mx31_clocks_init(unsigned long fref)
return 0;
}

1
arch/arm/mach-mx3/clock-imx35.c → arch/arm/mach-imx/clock-imx35.c
View File

@ -547,4 +547,3 @@ int __init mx35_clocks_init()
return 0;
}

38
arch/arm/mach-mx3/cpu.c → arch/arm/mach-imx/cpu-imx31.c
View File

@ -1,5 +1,5 @@
/*
* MX3 CPU type detection
* MX31 CPU type detection
*
* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
*
@ -17,14 +17,12 @@
unsigned int mx31_cpu_rev;
EXPORT_SYMBOL(mx31_cpu_rev);
struct mx3_cpu_type {
static struct {
u8 srev;
const char *name;
const char *v;
unsigned int rev;
};
static struct mx3_cpu_type mx31_cpu_type[] __initdata = {
} mx31_cpu_type[] __initdata = {
{ .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = IMX_CHIP_REVISION_1_0 },
{ .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 },
{ .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 },
@ -57,33 +55,3 @@ void __init mx31_read_cpu_rev(void)
printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev);
}
unsigned int mx35_cpu_rev;
EXPORT_SYMBOL(mx35_cpu_rev);
void __init mx35_read_cpu_rev(void)
{
u32 rev;
char *srev;
rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));
switch (rev) {
case 0x00:
mx35_cpu_rev = IMX_CHIP_REVISION_1_0;
srev = "1.0";
break;
case 0x10:
mx35_cpu_rev = IMX_CHIP_REVISION_2_0;
srev = "2.0";
break;
case 0x11:
mx35_cpu_rev = IMX_CHIP_REVISION_2_1;
srev = "2.1";
break;
default:
mx35_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
srev = "unknown";
}
printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev);
}

44
arch/arm/mach-imx/cpu-imx35.c Normal file
View File

@ -0,0 +1,44 @@
/*
* MX35 CPU type detection
*
* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/module.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/iim.h>
unsigned int mx35_cpu_rev;
EXPORT_SYMBOL(mx35_cpu_rev);
void __init mx35_read_cpu_rev(void)
{
u32 rev;
char *srev;
rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));
switch (rev) {
case 0x00:
mx35_cpu_rev = IMX_CHIP_REVISION_1_0;
srev = "1.0";
break;
case 0x10:
mx35_cpu_rev = IMX_CHIP_REVISION_2_0;
srev = "2.0";
break;
case 0x11:
mx35_cpu_rev = IMX_CHIP_REVISION_2_1;
srev = "2.1";
break;
default:
mx35_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
srev = "unknown";
}
printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev);
}

0
arch/arm/mach-mx3/crm_regs.h → arch/arm/mach-imx/crmregs-imx31.h
View File

8
arch/arm/mach-imx/devices-imx1.h
View File

@ -9,21 +9,21 @@
#include <mach/mx1.h>
#include <mach/devices-common.h>
extern const struct imx_imx_fb_data imx1_imx_fb_data __initconst;
extern const struct imx_imx_fb_data imx1_imx_fb_data;
#define imx1_add_imx_fb(pdata) \
imx_add_imx_fb(&imx1_imx_fb_data, pdata)
extern const struct imx_imx_i2c_data imx1_imx_i2c_data __initconst;
extern const struct imx_imx_i2c_data imx1_imx_i2c_data;
#define imx1_add_imx_i2c(pdata) \
imx_add_imx_i2c(&imx1_imx_i2c_data, pdata)
extern const struct imx_imx_uart_3irq_data imx1_imx_uart_data[] __initconst;
extern const struct imx_imx_uart_3irq_data imx1_imx_uart_data[];
#define imx1_add_imx_uart(id, pdata) \
imx_add_imx_uart_3irq(&imx1_imx_uart_data[id], pdata)
#define imx1_add_imx_uart0(pdata) imx1_add_imx_uart(0, pdata)
#define imx1_add_imx_uart1(pdata) imx1_add_imx_uart(1, pdata)
extern const struct imx_spi_imx_data imx1_cspi_data[] __initconst;
extern const struct imx_spi_imx_data imx1_cspi_data[];
#define imx1_add_cspi(id, pdata) \
imx_add_spi_imx(&imx1_cspi_data[id], pdata)

22
arch/arm/mach-imx/devices-imx21.h
View File

@ -9,31 +9,31 @@
#include <mach/mx21.h>
#include <mach/devices-common.h>
extern const struct imx_imx21_hcd_data imx21_imx21_hcd_data __initconst;
extern const struct imx_imx21_hcd_data imx21_imx21_hcd_data;
#define imx21_add_imx21_hcd(pdata) \
imx_add_imx21_hcd(&imx21_imx21_hcd_data, pdata)
extern const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst;
extern const struct imx_imx2_wdt_data imx21_imx2_wdt_data;
#define imx21_add_imx2_wdt(pdata) \
imx_add_imx2_wdt(&imx21_imx2_wdt_data)
extern const struct imx_imx_fb_data imx21_imx_fb_data __initconst;
extern const struct imx_imx_fb_data imx21_imx_fb_data;
#define imx21_add_imx_fb(pdata) \
imx_add_imx_fb(&imx21_imx_fb_data, pdata)
extern const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst;
extern const struct imx_imx_i2c_data imx21_imx_i2c_data;
#define imx21_add_imx_i2c(pdata) \
imx_add_imx_i2c(&imx21_imx_i2c_data, pdata)
extern const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst;
extern const struct imx_imx_keypad_data imx21_imx_keypad_data;
#define imx21_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx21_imx_keypad_data, pdata)
extern const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst;
extern const struct imx_imx_ssi_data imx21_imx_ssi_data[];
#define imx21_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx21_imx_ssi_data[id], pdata)
extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst;
extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[];
#define imx21_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx21_imx_uart_data[id], pdata)
#define imx21_add_imx_uart0(pdata) imx21_add_imx_uart(0, pdata)
@ -41,19 +41,19 @@ extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst;
#define imx21_add_imx_uart2(pdata) imx21_add_imx_uart(2, pdata)
#define imx21_add_imx_uart3(pdata) imx21_add_imx_uart(3, pdata)
extern const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst;
extern const struct imx_mxc_mmc_data imx21_mxc_mmc_data[];
#define imx21_add_mxc_mmc(id, pdata) \
imx_add_mxc_mmc(&imx21_mxc_mmc_data[id], pdata)
extern const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst;
extern const struct imx_mxc_nand_data imx21_mxc_nand_data;
#define imx21_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx21_mxc_nand_data, pdata)
extern const struct imx_mxc_w1_data imx21_mxc_w1_data __initconst;
extern const struct imx_mxc_w1_data imx21_mxc_w1_data;
#define imx21_add_mxc_w1(pdata) \
imx_add_mxc_w1(&imx21_mxc_w1_data)
extern const struct imx_spi_imx_data imx21_cspi_data[] __initconst;
extern const struct imx_spi_imx_data imx21_cspi_data[];
#define imx21_add_cspi(id, pdata) \
imx_add_spi_imx(&imx21_cspi_data[id], pdata)
#define imx21_add_spi_imx0(pdata) imx21_add_cspi(0, pdata)

35
arch/arm/mach-imx/devices-imx25.h
View File

@ -9,48 +9,48 @@
#include <mach/mx25.h>
#include <mach/devices-common.h>
extern const struct imx_fec_data imx25_fec_data __initconst;
extern const struct imx_fec_data imx25_fec_data;
#define imx25_add_fec(pdata) \
imx_add_fec(&imx25_fec_data, pdata)
extern const struct imx_flexcan_data imx25_flexcan_data[] __initconst;
extern const struct imx_flexcan_data imx25_flexcan_data[];
#define imx25_add_flexcan(id, pdata) \
imx_add_flexcan(&imx25_flexcan_data[id], pdata)
#define imx25_add_flexcan0(pdata) imx25_add_flexcan(0, pdata)
#define imx25_add_flexcan1(pdata) imx25_add_flexcan(1, pdata)
extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst;
extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data;
#define imx25_add_fsl_usb2_udc(pdata) \
imx_add_fsl_usb2_udc(&imx25_fsl_usb2_udc_data, pdata)
extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst;
extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data;
#define imx25_add_imxdi_rtc(pdata) \
imx_add_imxdi_rtc(&imx25_imxdi_rtc_data)
extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst;
extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data;
#define imx25_add_imx2_wdt(pdata) \
imx_add_imx2_wdt(&imx25_imx2_wdt_data)
extern const struct imx_imx_fb_data imx25_imx_fb_data __initconst;
extern const struct imx_imx_fb_data imx25_imx_fb_data;
#define imx25_add_imx_fb(pdata) \
imx_add_imx_fb(&imx25_imx_fb_data, pdata)
extern const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst;
extern const struct imx_imx_i2c_data imx25_imx_i2c_data[];
#define imx25_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx25_imx_i2c_data[id], pdata)
#define imx25_add_imx_i2c0(pdata) imx25_add_imx_i2c(0, pdata)
#define imx25_add_imx_i2c1(pdata) imx25_add_imx_i2c(1, pdata)
#define imx25_add_imx_i2c2(pdata) imx25_add_imx_i2c(2, pdata)
extern const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst;
extern const struct imx_imx_keypad_data imx25_imx_keypad_data;
#define imx25_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx25_imx_keypad_data, pdata)
extern const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst;
extern const struct imx_imx_ssi_data imx25_imx_ssi_data[];
#define imx25_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx25_imx_ssi_data[id], pdata)
extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst;
extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[];
#define imx25_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx25_imx_uart_data[id], pdata)
#define imx25_add_imx_uart0(pdata) imx25_add_imx_uart(0, pdata)
@ -59,33 +59,32 @@ extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst;
#define imx25_add_imx_uart3(pdata) imx25_add_imx_uart(3, pdata)
#define imx25_add_imx_uart4(pdata) imx25_add_imx_uart(4, pdata)
extern const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst;
extern const struct imx_mx2_camera_data imx25_mx2_camera_data;
#define imx25_add_mx2_camera(pdata) \
imx_add_mx2_camera(&imx25_mx2_camera_data, pdata)
extern const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst;
extern const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data;
#define imx25_add_mxc_ehci_otg(pdata) \
imx_add_mxc_ehci(&imx25_mxc_ehci_otg_data, pdata)
extern const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst;
extern const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data;
#define imx25_add_mxc_ehci_hs(pdata) \
imx_add_mxc_ehci(&imx25_mxc_ehci_hs_data, pdata)
extern const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst;
extern const struct imx_mxc_nand_data imx25_mxc_nand_data;
#define imx25_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx25_mxc_nand_data, pdata)
extern const struct imx_sdhci_esdhc_imx_data
imx25_sdhci_esdhc_imx_data[] __initconst;
extern const struct imx_sdhci_esdhc_imx_data imx25_sdhci_esdhc_imx_data[];
#define imx25_add_sdhci_esdhc_imx(id, pdata) \
imx_add_sdhci_esdhc_imx(&imx25_sdhci_esdhc_imx_data[id], pdata)
extern const struct imx_spi_imx_data imx25_cspi_data[] __initconst;
extern const struct imx_spi_imx_data imx25_cspi_data[];
#define imx25_add_spi_imx(id, pdata) \
imx_add_spi_imx(&imx25_cspi_data[id], pdata)
#define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata)
#define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata)
#define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata)
extern struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst;
extern struct imx_mxc_pwm_data imx25_mxc_pwm_data[];
#define imx25_add_mxc_pwm(id) \
imx_add_mxc_pwm(&imx25_mxc_pwm_data[id])

30
arch/arm/mach-imx/devices-imx27.h
View File

@ -9,35 +9,35 @@
#include <mach/mx27.h>
#include <mach/devices-common.h>
extern const struct imx_fec_data imx27_fec_data __initconst;
extern const struct imx_fec_data imx27_fec_data;
#define imx27_add_fec(pdata) \
imx_add_fec(&imx27_fec_data, pdata)
extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst;
extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data;
#define imx27_add_fsl_usb2_udc(pdata) \
imx_add_fsl_usb2_udc(&imx27_fsl_usb2_udc_data, pdata)
extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst;
extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data;
#define imx27_add_imx2_wdt(pdata) \
imx_add_imx2_wdt(&imx27_imx2_wdt_data)
extern const struct imx_imx_fb_data imx27_imx_fb_data __initconst;
extern const struct imx_imx_fb_data imx27_imx_fb_data;
#define imx27_add_imx_fb(pdata) \
imx_add_imx_fb(&imx27_imx_fb_data, pdata)
extern const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst;
extern const struct imx_imx_i2c_data imx27_imx_i2c_data[];
#define imx27_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx27_imx_i2c_data[id], pdata)
extern const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst;
extern const struct imx_imx_keypad_data imx27_imx_keypad_data;
#define imx27_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx27_imx_keypad_data, pdata)
extern const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst;
extern const struct imx_imx_ssi_data imx27_imx_ssi_data[];
#define imx27_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx27_imx_ssi_data[id], pdata)
extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst;
extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[];
#define imx27_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx27_imx_uart_data[id], pdata)
#define imx27_add_imx_uart0(pdata) imx27_add_imx_uart(0, pdata)
@ -47,30 +47,30 @@ extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst;
#define imx27_add_imx_uart4(pdata) imx27_add_imx_uart(4, pdata)
#define imx27_add_imx_uart5(pdata) imx27_add_imx_uart(5, pdata)
extern const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst;
extern const struct imx_mx2_camera_data imx27_mx2_camera_data;
#define imx27_add_mx2_camera(pdata) \
imx_add_mx2_camera(&imx27_mx2_camera_data, pdata)
extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst;
extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data;
#define imx27_add_mxc_ehci_otg(pdata) \
imx_add_mxc_ehci(&imx27_mxc_ehci_otg_data, pdata)
extern const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[] __initconst;
extern const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[];
#define imx27_add_mxc_ehci_hs(id, pdata) \
imx_add_mxc_ehci(&imx27_mxc_ehci_hs_data[id - 1], pdata)
extern const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst;
extern const struct imx_mxc_mmc_data imx27_mxc_mmc_data[];
#define imx27_add_mxc_mmc(id, pdata) \
imx_add_mxc_mmc(&imx27_mxc_mmc_data[id], pdata)
extern const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst;
extern const struct imx_mxc_nand_data imx27_mxc_nand_data;
#define imx27_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx27_mxc_nand_data, pdata)
extern const struct imx_mxc_w1_data imx27_mxc_w1_data __initconst;
extern const struct imx_mxc_w1_data imx27_mxc_w1_data;
#define imx27_add_mxc_w1(pdata) \
imx_add_mxc_w1(&imx27_mxc_w1_data)
extern const struct imx_spi_imx_data imx27_cspi_data[] __initconst;
extern const struct imx_spi_imx_data imx27_cspi_data[];
#define imx27_add_cspi(id, pdata) \
imx_add_spi_imx(&imx27_cspi_data[id], pdata)
#define imx27_add_spi_imx0(pdata) imx27_add_cspi(0, pdata)

36
arch/arm/mach-mx3/devices-imx31.h → arch/arm/mach-imx/devices-imx31.h
View File

@ -9,30 +9,30 @@
#include <mach/mx31.h>
#include <mach/devices-common.h>
extern const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst;
extern const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data;
#define imx31_add_fsl_usb2_udc(pdata) \
imx_add_fsl_usb2_udc(&imx31_fsl_usb2_udc_data, pdata)
extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data __initconst;
extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data;
#define imx31_add_imx2_wdt(pdata) \
imx_add_imx2_wdt(&imx31_imx2_wdt_data)
extern const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst;
extern const struct imx_imx_i2c_data imx31_imx_i2c_data[];
#define imx31_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx31_imx_i2c_data[id], pdata)
#define imx31_add_imx_i2c0(pdata) imx31_add_imx_i2c(0, pdata)
#define imx31_add_imx_i2c1(pdata) imx31_add_imx_i2c(1, pdata)
#define imx31_add_imx_i2c2(pdata) imx31_add_imx_i2c(2, pdata)
extern const struct imx_imx_keypad_data imx31_imx_keypad_data __initconst;
extern const struct imx_imx_keypad_data imx31_imx_keypad_data;
#define imx31_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx31_imx_keypad_data, pdata)
extern const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst;
extern const struct imx_imx_ssi_data imx31_imx_ssi_data[];
#define imx31_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx31_imx_ssi_data[id], pdata)
extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst;
extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[];
#define imx31_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx31_imx_uart_data[id], pdata)
#define imx31_add_imx_uart0(pdata) imx31_add_imx_uart(0, pdata)
@ -41,26 +41,38 @@ extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst;
#define imx31_add_imx_uart3(pdata) imx31_add_imx_uart(3, pdata)
#define imx31_add_imx_uart4(pdata) imx31_add_imx_uart(4, pdata)
extern const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data __initconst;
extern const struct imx_ipu_core_data imx31_ipu_core_data;
#define imx31_add_ipu_core(pdata) \
imx_add_ipu_core(&imx31_ipu_core_data, pdata)
#define imx31_alloc_mx3_camera(pdata) \
imx_alloc_mx3_camera(&imx31_ipu_core_data, pdata)
#define imx31_add_mx3_sdc_fb(pdata) \
imx_add_mx3_sdc_fb(&imx31_ipu_core_data, pdata)
extern const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data;
#define imx31_add_mxc_ehci_otg(pdata) \
imx_add_mxc_ehci(&imx31_mxc_ehci_otg_data, pdata)
extern const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[] __initconst;
extern const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[];
#define imx31_add_mxc_ehci_hs(id, pdata) \
imx_add_mxc_ehci(&imx31_mxc_ehci_hs_data[id - 1], pdata)
extern const struct imx_mxc_mmc_data imx31_mxc_mmc_data[] __initconst;
extern const struct imx_mxc_mmc_data imx31_mxc_mmc_data[];
#define imx31_add_mxc_mmc(id, pdata) \
imx_add_mxc_mmc(&imx31_mxc_mmc_data[id], pdata)
extern const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst;
extern const struct imx_mxc_nand_data imx31_mxc_nand_data;
#define imx31_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx31_mxc_nand_data, pdata)
extern const struct imx_mxc_w1_data imx31_mxc_w1_data __initconst;
extern const struct imx_mxc_rtc_data imx31_mxc_rtc_data;
#define imx31_add_mxc_rtc(pdata) \
imx_add_mxc_rtc(&imx31_mxc_rtc_data)
extern const struct imx_mxc_w1_data imx31_mxc_w1_data;
#define imx31_add_mxc_w1(pdata) \
imx_add_mxc_w1(&imx31_mxc_w1_data)
extern const struct imx_spi_imx_data imx31_cspi_data[] __initconst;
extern const struct imx_spi_imx_data imx31_cspi_data[];
#define imx31_add_cspi(id, pdata) \
imx_add_spi_imx(&imx31_cspi_data[id], pdata)
#define imx31_add_spi_imx0(pdata) imx31_add_cspi(0, pdata)

37
arch/arm/mach-mx3/devices-imx35.h → arch/arm/mach-imx/devices-imx35.h
View File

@ -9,67 +9,74 @@
#include <mach/mx35.h>
#include <mach/devices-common.h>
extern const struct imx_fec_data imx35_fec_data __initconst;
extern const struct imx_fec_data imx35_fec_data;
#define imx35_add_fec(pdata) \
imx_add_fec(&imx35_fec_data, pdata)
extern const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst;
extern const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data;
#define imx35_add_fsl_usb2_udc(pdata) \
imx_add_fsl_usb2_udc(&imx35_fsl_usb2_udc_data, pdata)
extern const struct imx_flexcan_data imx35_flexcan_data[] __initconst;
extern const struct imx_flexcan_data imx35_flexcan_data[];
#define imx35_add_flexcan(id, pdata) \
imx_add_flexcan(&imx35_flexcan_data[id], pdata)
#define imx35_add_flexcan0(pdata) imx35_add_flexcan(0, pdata)
#define imx35_add_flexcan1(pdata) imx35_add_flexcan(1, pdata)
extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst;
extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data;
#define imx35_add_imx2_wdt(pdata) \
imx_add_imx2_wdt(&imx35_imx2_wdt_data)
extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst;
extern const struct imx_imx_i2c_data imx35_imx_i2c_data[];
#define imx35_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx35_imx_i2c_data[id], pdata)
#define imx35_add_imx_i2c0(pdata) imx35_add_imx_i2c(0, pdata)
#define imx35_add_imx_i2c1(pdata) imx35_add_imx_i2c(1, pdata)
#define imx35_add_imx_i2c2(pdata) imx35_add_imx_i2c(2, pdata)
extern const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst;
extern const struct imx_imx_keypad_data imx35_imx_keypad_data;
#define imx35_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx35_imx_keypad_data, pdata)
extern const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst;
extern const struct imx_imx_ssi_data imx35_imx_ssi_data[];
#define imx35_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx35_imx_ssi_data[id], pdata)
extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst;
extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[];
#define imx35_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx35_imx_uart_data[id], pdata)
#define imx35_add_imx_uart0(pdata) imx35_add_imx_uart(0, pdata)
#define imx35_add_imx_uart1(pdata) imx35_add_imx_uart(1, pdata)
#define imx35_add_imx_uart2(pdata) imx35_add_imx_uart(2, pdata)
extern const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data __initconst;
extern const struct imx_ipu_core_data imx35_ipu_core_data;
#define imx35_add_ipu_core(pdata) \
imx_add_ipu_core(&imx35_ipu_core_data, pdata)
#define imx35_alloc_mx3_camera(pdata) \
imx_alloc_mx3_camera(&imx35_ipu_core_data, pdata)
#define imx35_add_mx3_sdc_fb(pdata) \
imx_add_mx3_sdc_fb(&imx35_ipu_core_data, pdata)
extern const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data;
#define imx35_add_mxc_ehci_otg(pdata) \
imx_add_mxc_ehci(&imx35_mxc_ehci_otg_data, pdata)
extern const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst;
extern const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data;
#define imx35_add_mxc_ehci_hs(pdata) \
imx_add_mxc_ehci(&imx35_mxc_ehci_hs_data, pdata)
extern const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst;
extern const struct imx_mxc_nand_data imx35_mxc_nand_data;
#define imx35_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx35_mxc_nand_data, pdata)
extern const struct imx_mxc_w1_data imx35_mxc_w1_data __initconst;
extern const struct imx_mxc_w1_data imx35_mxc_w1_data;
#define imx35_add_mxc_w1(pdata) \
imx_add_mxc_w1(&imx35_mxc_w1_data)
extern const struct imx_sdhci_esdhc_imx_data
imx35_sdhci_esdhc_imx_data[] __initconst;
extern const struct imx_sdhci_esdhc_imx_data imx35_sdhci_esdhc_imx_data[];
#define imx35_add_sdhci_esdhc_imx(id, pdata) \
imx_add_sdhci_esdhc_imx(&imx35_sdhci_esdhc_imx_data[id], pdata)
extern const struct imx_spi_imx_data imx35_cspi_data[] __initconst;
extern const struct imx_spi_imx_data imx35_cspi_data[];
#define imx35_add_cspi(id, pdata) \
imx_add_spi_imx(&imx35_cspi_data[id], pdata)
#define imx35_add_spi_imx0(pdata) imx35_add_cspi(0, pdata)

1
arch/arm/mach-mx3/ehci-imx31.c → arch/arm/mach-imx/ehci-imx31.c
View File

@ -80,4 +80,3 @@ int mx31_initialize_usb_hw(int port, unsigned int flags)
return 0;
}

1
arch/arm/mach-mx3/ehci-imx35.c → arch/arm/mach-imx/ehci-imx35.c
View File

@ -77,4 +77,3 @@ int mx35_initialize_usb_hw(int port, unsigned int flags)
return 0;
}

1
arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
View File

@ -32,7 +32,6 @@
#include <mach/common.h>
#include <mach/iomux-mx27.h>
#include <mach/hardware.h>
#include <mach/spi.h>
#include <mach/audmux.h>
#include "devices-imx27.h"

17
arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
View File

@ -22,7 +22,6 @@
#include <linux/gpio.h>
#include <linux/leds.h>
#include <linux/platform_device.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <video/platform_lcd.h>
@ -32,9 +31,7 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/mx25.h>
#include <mach/imx-uart.h>
#include <mach/audmux.h>
#include <mach/esdhc.h>
#include "devices-imx25.h"
@ -208,23 +205,14 @@ static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
},
};
static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = {
static const struct gpio_keys_platform_data
eukrea_mbimxsd_button_data __initconst = {
.buttons = eukrea_mbimxsd_gpio_buttons,
.nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
};
static struct platform_device eukrea_mbimxsd_button_device = {
.name = "gpio-keys",
.id = -1,
.num_resources = 0,
.dev = {
.platform_data = &eukrea_mbimxsd_button_data,
}
};
static struct platform_device *platform_devices[] __initdata = {
&eukrea_mbimxsd_leds_gpio,
&eukrea_mbimxsd_button_device,
&eukrea_mbimxsd_lcd_powerdev,
};
@ -299,4 +287,5 @@ void __init eukrea_mbimxsd25_baseboard_init(void)
ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
}

29
arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c → arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
View File

@ -26,7 +26,6 @@
#include <linux/interrupt.h>
#include <linux/leds.h>
#include <linux/platform_device.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <video/platform_lcd.h>
#include <linux/i2c.h>
@ -38,15 +37,10 @@
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx35.h>
#include <mach/ipu.h>
#include <mach/mx3fb.h>
#include <mach/audmux.h>
#include <mach/esdhc.h>
#include "devices-imx35.h"
#include "devices.h"
static const struct fb_videomode fb_modedb[] = {
{
@ -101,12 +95,11 @@ static const struct fb_videomode fb_modedb[] = {
},
};
static struct ipu_platform_data mx3_ipu_data = {
static const struct ipu_platform_data mx3_ipu_data __initconst = {
.irq_base = MXC_IPU_IRQ_START,
};
static struct mx3fb_platform_data mx3fb_pdata = {
.dma_dev = &mx3_ipu.dev,
static struct mx3fb_platform_data mx3fb_pdata __initdata = {
.name = "CMO-QVGA",
.mode = fb_modedb,
.num_modes = ARRAY_SIZE(fb_modedb),
@ -223,23 +216,14 @@ static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
},
};
static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = {
static const struct gpio_keys_platform_data
eukrea_mbimxsd_button_data __initconst = {
.buttons = eukrea_mbimxsd_gpio_buttons,
.nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
};
static struct platform_device eukrea_mbimxsd_button_device = {
.name = "gpio-keys",
.id = -1,
.num_resources = 0,
.dev = {
.platform_data = &eukrea_mbimxsd_button_data,
}
};
static struct platform_device *platform_devices[] __initdata = {
&eukrea_mbimxsd_leds_gpio,
&eukrea_mbimxsd_button_device,
&eukrea_mbimxsd_lcd_powerdev,
};
@ -292,8 +276,8 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
#endif
imx35_add_imx_uart1(&uart_pdata);
mxc_register_device(&mx3_ipu, &mx3_ipu_data);
mxc_register_device(&mx3_fb, &mx3fb_pdata);
imx35_add_ipu_core(&mx3_ipu_data);
imx35_add_mx3_sdc_fb(&mx3fb_pdata);
imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
@ -315,4 +299,5 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
}

0
arch/arm/mach-mx3/iomux-imx31.c → arch/arm/mach-imx/iomux-imx31.c
View File

144
arch/arm/mach-imx/mach-apf9328.c Normal file
View File

@ -0,0 +1,144 @@
/*
* linux/arch/arm/mach-imx/mach-apf9328.c
*
* Copyright (c) 2005-2011 ARMadeus systems <support@armadeus.com>
*
* This work is based on mach-scb9328.c which is:
* Copyright (c) 2004 Sascha Hauer <saschahauer@web.de>
* Copyright (c) 2006-2008 Juergen Beisert <jbeisert@netscape.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/dm9000.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <mach/iomux-mx1.h>
#include "devices-imx1.h"
static const int apf9328_pins[] __initconst = {
/* UART1 */
PC9_PF_UART1_CTS,
PC10_PF_UART1_RTS,
PC11_PF_UART1_TXD,
PC12_PF_UART1_RXD,
/* UART2 */
PB28_PF_UART2_CTS,
PB29_PF_UART2_RTS,
PB30_PF_UART2_TXD,
PB31_PF_UART2_RXD,
};
/*
* The APF9328 can have up to 32MB NOR Flash
*/
static struct resource flash_resource = {
.start = MX1_CS0_PHYS,
.end = MX1_CS0_PHYS + SZ_32M - 1,
.flags = IORESOURCE_MEM,
};
static struct physmap_flash_data apf9328_flash_data = {
.width = 2,
};
static struct platform_device apf9328_flash_device = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &apf9328_flash_data,
},
.resource = &flash_resource,
.num_resources = 1,
};
/*
* APF9328 has a DM9000 Ethernet controller
*/
static struct dm9000_plat_data dm9000_setup = {
.flags = DM9000_PLATF_16BITONLY
};
static struct resource dm9000_resources[] = {
{
.start = MX1_CS4_PHYS + 0x00C00000,
.end = MX1_CS4_PHYS + 0x00C00001,
.flags = IORESOURCE_MEM,
}, {
.start = MX1_CS4_PHYS + 0x00C00002,
.end = MX1_CS4_PHYS + 0x00C00003,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_GPIOB(14),
.end = IRQ_GPIOB(14),
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
},
};
static struct platform_device dm9000x_device = {
.name = "dm9000",
.id = 0,
.num_resources = ARRAY_SIZE(dm9000_resources),
.resource = dm9000_resources,
.dev = {
.platform_data = &dm9000_setup,
}
};
/* --- SERIAL RESSOURCE --- */
static const struct imxuart_platform_data uart0_pdata __initconst = {
.flags = 0,
};
static const struct imxuart_platform_data uart1_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static struct platform_device *devices[] __initdata = {
&apf9328_flash_device,
&dm9000x_device,
};
static void __init apf9328_init(void)
{
mxc_gpio_setup_multiple_pins(apf9328_pins,
ARRAY_SIZE(apf9328_pins),
"APF9328");
imx1_add_imx_uart0(&uart0_pdata);
imx1_add_imx_uart1(&uart1_pdata);
platform_add_devices(devices, ARRAY_SIZE(devices));
}
static void __init apf9328_timer_init(void)
{
mx1_clocks_init(32768);
}
static struct sys_timer apf9328_timer = {
.init = apf9328_timer_init,
};
MACHINE_START(APF9328, "Armadeus APF9328")
/* Maintainer: Gwenhael Goavec-Merou, ARMadeus Systems */
.map_io = mx1_map_io,
.init_early = imx1_init_early,
.init_irq = mx1_init_irq,
.timer = &apf9328_timer,
.init_machine = apf9328_init,
MACHINE_END

29
arch/arm/mach-mx3/mach-armadillo5x0.c → arch/arm/mach-imx/mach-armadillo5x0.c
View File

@ -34,7 +34,6 @@
#include <linux/mtd/physmap.h>
#include <linux/io.h>
#include <linux/input.h>
#include <linux/gpio_keys.h>
#include <linux/i2c.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
@ -49,13 +48,10 @@
#include <mach/common.h>
#include <mach/iomux-mx3.h>
#include <mach/ipu.h>
#include <mach/mx3fb.h>
#include <mach/ulpi.h>
#include "devices-imx31.h"
#include "devices.h"
#include "crm_regs.h"
#include "crmregs-imx31.h"
static int armadillo5x0_pins[] = {
/* UART1 */
@ -280,20 +276,12 @@ static struct gpio_keys_button armadillo5x0_buttons[] = {
}
};
static struct gpio_keys_platform_data armadillo5x0_button_data = {
static const struct gpio_keys_platform_data
armadillo5x0_button_data __initconst = {
.buttons = armadillo5x0_buttons,
.nbuttons = ARRAY_SIZE(armadillo5x0_buttons),
};
static struct platform_device armadillo5x0_button_device = {
.name = "gpio-keys",
.id = -1,
.num_resources = 0,
.dev = {
.platform_data = &armadillo5x0_button_data,
}
};
/*
* NAND Flash
*/
@ -383,12 +371,11 @@ static const struct fb_videomode fb_modedb[] = {
},
};
static struct ipu_platform_data mx3_ipu_data = {
static const struct ipu_platform_data mx3_ipu_data __initconst = {
.irq_base = MXC_IPU_IRQ_START,
};
static struct mx3fb_platform_data mx3fb_pdata = {
.dma_dev = &mx3_ipu.dev,
static struct mx3fb_platform_data mx3fb_pdata __initdata = {
.name = "CRT-VGA",
.mode = fb_modedb,
.num_modes = ARRAY_SIZE(fb_modedb),
@ -496,7 +483,6 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
static struct platform_device *devices[] __initdata = {
&armadillo5x0_smc911x_device,
&armadillo5x0_button_device,
};
/*
@ -508,6 +494,7 @@ static void __init armadillo5x0_init(void)
ARRAY_SIZE(armadillo5x0_pins), "armadillo5x0");
platform_add_devices(devices, ARRAY_SIZE(devices));
imx_add_gpio_keys(&armadillo5x0_button_data);
imx31_add_imx_i2c1(NULL);
/* Register UART */
@ -521,8 +508,8 @@ static void __init armadillo5x0_init(void)
imx31_add_mxc_mmc(0, &sdhc_pdata);
/* Register FB */
mxc_register_device(&mx3_ipu, &mx3_ipu_data);
mxc_register_device(&mx3_fb, &mx3fb_pdata);
imx31_add_ipu_core(&mx3_ipu_data);
imx31_add_mx3_sdc_fb(&mx3fb_pdata);
/* Register NOR Flash */
mxc_register_device(&armadillo5x0_nor_flash,

1
arch/arm/mach-mx3/mach-bug.c → arch/arm/mach-imx/mach-bug.c
View File

@ -20,7 +20,6 @@
#include <linux/platform_device.h>
#include <mach/iomux-mx3.h>
#include <mach/imx-uart.h>
#include <mach/hardware.h>
#include <mach/common.h>

1
arch/arm/mach-imx/mach-cpuimx27.c
View File

@ -38,7 +38,6 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx27.h>
#include <mach/mxc_nand.h>
#include <mach/ulpi.h>
#include "devices-imx27.h"

2
arch/arm/mach-mx3/mach-cpuimx35.c → arch/arm/mach-imx/mach-cpuimx35.c
View File

@ -41,10 +41,8 @@
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/iomux-mx35.h>
#include <mach/mxc_nand.h>
#include "devices-imx35.h"
#include "devices.h"
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,

2
arch/arm/mach-imx/mach-eukrea_cpuimx25.c
View File

@ -36,8 +36,6 @@
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/mx25.h>
#include <mach/mxc_nand.h>
#include <mach/imxfb.h>
#include <mach/iomux-mx25.h>
#include "devices-imx25.h"

14
arch/arm/mach-imx/mach-imx27_visstrim_m10.c
View File

@ -27,7 +27,6 @@
#include <linux/mtd/physmap.h>
#include <linux/i2c.h>
#include <linux/i2c/pca953x.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/gpio.h>
#include <linux/delay.h>
@ -130,19 +129,12 @@ static struct gpio_keys_button visstrim_gpio_keys[] = {
}
};
static struct gpio_keys_platform_data visstrim_gpio_keys_platform_data = {
static const struct gpio_keys_platform_data
visstrim_gpio_keys_platform_data __initconst = {
.buttons = visstrim_gpio_keys,
.nbuttons = ARRAY_SIZE(visstrim_gpio_keys),
};
static struct platform_device visstrim_gpio_keys_device = {
.name = "gpio-keys",
.id = -1,
.dev = {
.platform_data = &visstrim_gpio_keys_platform_data,
},
};
/* Visstrim_SM10 has a microSD slot connected to sdhc1 */
static int visstrim_m10_sdhc1_init(struct device *dev,
irq_handler_t detect_irq, void *data)
@ -186,7 +178,6 @@ static struct platform_device visstrim_m10_nor_mtd_device = {
};
static struct platform_device *platform_devices[] __initdata = {
&visstrim_gpio_keys_device,
&visstrim_m10_nor_mtd_device,
};
@ -255,6 +246,7 @@ static void __init visstrim_m10_board_init(void)
imx27_add_mxc_mmc(0, &visstrim_m10_sdhc_pdata);
imx27_add_mxc_ehci_otg(&visstrim_m10_usbotg_pdata);
imx27_add_fec(NULL);
imx_add_gpio_keys(&visstrim_gpio_keys_platform_data);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
}

1
arch/arm/mach-mx3/mach-kzm_arm11_01.c → arch/arm/mach-imx/mach-kzm_arm11_01.c
View File

@ -39,7 +39,6 @@
#include <mach/iomux-mx3.h>
#include "devices-imx31.h"
#include "devices.h"
#define KZM_ARM11_IO_ADDRESS(x) (IOMEM( \
IMX_IO_P2V_MODULE(x, MX31_CS4) ?: \

1
arch/arm/mach-imx/mach-mx1ads.c
View File

@ -25,7 +25,6 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/i2c.h>
#include <mach/iomux-mx1.h>
#include <mach/irqs.h>

1
arch/arm/mach-imx/mach-mx21ads.c
View File

@ -25,7 +25,6 @@
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <mach/iomux-mx21.h>
#include <mach/mxc_nand.h>
#include "devices-imx21.h"

13
arch/arm/mach-imx/mach-mx25_3ds.c
View File

@ -29,7 +29,6 @@
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/input/matrix_keypad.h>
#include <linux/usb/otg.h>
#include <mach/hardware.h>
@ -103,6 +102,8 @@ static iomux_v3_cfg_t mx25pdk_pads[] = {
MX25_PAD_SD1_DATA1__SD1_DATA1,
MX25_PAD_SD1_DATA2__SD1_DATA2,
MX25_PAD_SD1_DATA3__SD1_DATA3,
MX25_PAD_A14__GPIO_2_0, /* WriteProtect */
MX25_PAD_A15__GPIO_2_1, /* CardDetect */
/* I2C1 */
MX25_PAD_I2C1_CLK__I2C1_CLK,
@ -208,6 +209,14 @@ static const struct imxi2c_platform_data mx25_3ds_i2c0_data __initconst = {
.bitrate = 100000,
};
#define SD1_GPIO_WP IMX_GPIO_NR(2, 0)
#define SD1_GPIO_CD IMX_GPIO_NR(2, 1)
static const struct esdhc_platform_data mx25pdk_esdhc_pdata __initconst = {
.wp_gpio = SD1_GPIO_WP,
.cd_gpio = SD1_GPIO_CD,
};
static void __init mx25pdk_init(void)
{
mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads,
@ -225,7 +234,7 @@ static void __init mx25pdk_init(void)
imx25_add_fec(&mx25_fec_pdata);
imx25_add_imx_keypad(&mx25pdk_keymap_data);
imx25_add_sdhci_esdhc_imx(0, NULL);
imx25_add_sdhci_esdhc_imx(0, &mx25pdk_esdhc_pdata);
imx25_add_imx_i2c0(&mx25_3ds_i2c0_data);
}

1
arch/arm/mach-imx/mach-mx27ads.c
View File

@ -29,7 +29,6 @@
#include <asm/mach/map.h>
#include <mach/gpio.h>
#include <mach/iomux-mx27.h>
#include <mach/mxc_nand.h>
#include "devices-imx27.h"

50
arch/arm/mach-mx3/mach-mx31_3ds.c → arch/arm/mach-imx/mach-mx31_3ds.c
View File

@ -39,13 +39,8 @@
#include <mach/iomux-mx3.h>
#include <mach/3ds_debugboard.h>
#include <mach/ulpi.h>
#include <mach/mmc.h>
#include <mach/ipu.h>
#include <mach/mx3fb.h>
#include <mach/mx3_camera.h>
#include "devices-imx31.h"
#include "devices.h"
/* CPLD IRQ line for external uart, external ethernet etc */
#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
@ -178,22 +173,37 @@ static struct gpio mx31_3ds_camera_gpios[] = {
{ MX31_3DS_GPIO_CAMERA_RST, GPIOF_OUT_INIT_HIGH, "camera-reset" },
};
static int __init mx31_3ds_camera_alloc_dma(void)
static const struct mx3_camera_pdata mx31_3ds_camera_pdata __initconst = {
.flags = MX3_CAMERA_DATAWIDTH_10,
.mclk_10khz = 2600,
};
static int __init mx31_3ds_init_camera(void)
{
int dma;
int dma, ret = -ENOMEM;
struct platform_device *pdev =
imx31_alloc_mx3_camera(&mx31_3ds_camera_pdata);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
if (!mx3_camera_base)
return -ENOMEM;
goto err;
dma = dma_declare_coherent_memory(&mx3_camera.dev,
dma = dma_declare_coherent_memory(&pdev->dev,
mx3_camera_base, mx3_camera_base,
MX31_3DS_CAMERA_BUF_SIZE,
DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
if (!(dma & DMA_MEMORY_MAP))
return -ENOMEM;
goto err;
return 0;
ret = platform_device_add(pdev);
if (ret)
err:
platform_device_put(pdev);
return ret;
}
static int mx31_3ds_camera_power(struct device *dev, int on)
@ -241,12 +251,6 @@ static struct platform_device mx31_3ds_ov2640 = {
},
};
struct mx3_camera_pdata mx31_3ds_camera_pdata = {
.dma_dev = &mx3_ipu.dev,
.flags = MX3_CAMERA_DATAWIDTH_10,
.mclk_10khz = 2600,
};
/*
* FB support
*/
@ -273,8 +277,7 @@ static struct ipu_platform_data mx3_ipu_data = {
.irq_base = MXC_IPU_IRQ_START,
};
static struct mx3fb_platform_data mx3fb_pdata = {
.dma_dev = &mx3_ipu.dev,
static struct mx3fb_platform_data mx3fb_pdata __initdata = {
.name = "Epson-VGA",
.mode = fb_modedb,
.num_modes = ARRAY_SIZE(fb_modedb),
@ -723,8 +726,8 @@ static void __init mx31_3ds_init(void)
imx31_add_mxc_mmc(0, &sdhc1_pdata);
imx31_add_spi_imx0(&spi0_pdata);
mxc_register_device(&mx3_ipu, &mx3_ipu_data);
mxc_register_device(&mx3_fb, &mx3fb_pdata);
imx31_add_ipu_core(&mx3_ipu_data);
imx31_add_mx3_sdc_fb(&mx3fb_pdata);
/* CSI */
/* Camera power: default - off */
@ -735,10 +738,7 @@ static void __init mx31_3ds_init(void)
iclink_ov2640.power = NULL;
}
if (!mx31_3ds_camera_alloc_dma())
mxc_register_device(&mx3_camera, &mx31_3ds_camera_pdata);
else
pr_err("Failed to allocate dma memory for camera");
mx31_3ds_init_camera();
}
static void __init mx31_3ds_timer_init(void)

1
arch/arm/mach-mx3/mach-mx31ads.c → arch/arm/mach-imx/mach-mx31ads.c
View File

@ -38,7 +38,6 @@
#endif
#include "devices-imx31.h"
#include "devices.h"
/* PBC Board interrupt status register */
#define PBC_INTSTATUS 0x000016

1
arch/arm/mach-mx3/mach-mx31lilly.c → arch/arm/mach-imx/mach-mx31lilly.c
View File

@ -46,7 +46,6 @@
#include <mach/ulpi.h>
#include "devices-imx31.h"
#include "devices.h"
/*
* This file contains module-specific initialization routines for LILLY-1131.

1
arch/arm/mach-mx3/mach-mx31lite.c → arch/arm/mach-imx/mach-mx31lite.c
View File

@ -44,7 +44,6 @@
#include <mach/ulpi.h>
#include "devices-imx31.h"
#include "devices.h"
/*
* This file contains the module-specific initialization routines.

75
arch/arm/mach-mx3/mach-mx31moboard.c → arch/arm/mach-imx/mach-mx31moboard.c
View File

@ -27,6 +27,7 @@
#include <linux/mfd/mc13783.h>
#include <linux/spi/spi.h>
#include <linux/types.h>
#include <linux/memblock.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
@ -39,13 +40,9 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx3.h>
#include <mach/ipu.h>
#include <mach/mx3_camera.h>
#include <mach/spi.h>
#include <mach/ulpi.h>
#include "devices-imx31.h"
#include "devices.h"
static unsigned int moboard_pins[] = {
/* UART0 */
@ -102,7 +99,7 @@ static unsigned int moboard_pins[] = {
};
static struct physmap_flash_data mx31moboard_flash_data = {
.width = 2,
.width = 2,
};
static struct resource mx31moboard_flash_resource = {
@ -194,8 +191,8 @@ static struct regulator_init_data sdhc_vreg_data = {
static struct regulator_consumer_supply cam_consumers[] = {
{
.dev = &mx3_camera.dev,
.supply = "cam_vcc",
.dev_name = "mx3_camera.0",
.supply = "cam_vcc",
},
};
@ -430,9 +427,9 @@ static int __init moboard_usbh2_init(void)
static struct gpio_led mx31moboard_leds[] = {
{
.name = "coreboard-led-0:red:running",
.name = "coreboard-led-0:red:running",
.default_trigger = "heartbeat",
.gpio = IOMUX_TO_GPIO(MX31_PIN_SVEN0),
.gpio = IOMUX_TO_GPIO(MX31_PIN_SVEN0),
}, {
.name = "coreboard-led-1:red",
.gpio = IOMUX_TO_GPIO(MX31_PIN_STX0),
@ -446,7 +443,7 @@ static struct gpio_led mx31moboard_leds[] = {
};
static struct gpio_led_platform_data mx31moboard_led_pdata = {
.num_leds = ARRAY_SIZE(mx31moboard_leds),
.num_leds = ARRAY_SIZE(mx31moboard_leds),
.leds = mx31moboard_leds,
};
@ -458,7 +455,7 @@ static struct platform_device mx31moboard_leds_device = {
},
};
static struct ipu_platform_data mx3_ipu_data = {
static const struct ipu_platform_data mx3_ipu_data __initconst = {
.irq_base = MXC_IPU_IRQ_START,
};
@ -467,37 +464,39 @@ static struct platform_device *devices[] __initdata = {
&mx31moboard_leds_device,
};
static struct mx3_camera_pdata camera_pdata = {
.dma_dev = &mx3_ipu.dev,
static struct mx3_camera_pdata camera_pdata __initdata = {
.flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10,
.mclk_10khz = 4800,
};
#define CAMERA_BUF_SIZE (4*1024*1024)
static phys_addr_t mx3_camera_base __initdata;
#define MX3_CAMERA_BUF_SIZE SZ_4M
static int __init mx31moboard_cam_alloc_dma(const size_t buf_size)
static int __init mx31moboard_init_cam(void)
{
dma_addr_t dma_handle;
void *buf;
int dma;
int dma, ret = -ENOMEM;
struct platform_device *pdev;
if (buf_size < 2 * 1024 * 1024)
return -EINVAL;
imx31_add_ipu_core(&mx3_ipu_data);
buf = dma_alloc_coherent(NULL, buf_size, &dma_handle, GFP_KERNEL);
if (!buf) {
pr_err("%s: cannot allocate camera buffer-memory\n", __func__);
return -ENOMEM;
}
pdev = imx31_alloc_mx3_camera(&camera_pdata);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
memset(buf, 0, buf_size);
dma = dma_declare_coherent_memory(&mx3_camera.dev,
dma_handle, dma_handle, buf_size,
dma = dma_declare_coherent_memory(&pdev->dev,
mx3_camera_base, mx3_camera_base,
MX3_CAMERA_BUF_SIZE,
DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
if (!(dma & DMA_MEMORY_MAP))
goto err;
ret = platform_device_add(pdev);
if (ret)
err:
platform_device_put(pdev);
return ret;
/* The way we call dma_declare_coherent_memory only a malloc can fail */
return dma & DMA_MEMORY_MAP ? 0 : -ENOMEM;
}
static int mx31moboard_baseboard;
@ -529,9 +528,7 @@ static void __init mx31moboard_init(void)
imx31_add_mxc_mmc(0, &sdhc1_pdata);
mxc_register_device(&mx3_ipu, &mx3_ipu_data);
if (!mx31moboard_cam_alloc_dma(CAMERA_BUF_SIZE))
mxc_register_device(&mx3_camera, &camera_pdata);
mx31moboard_init_cam();
usb_xcvr_reset();
@ -565,9 +562,19 @@ struct sys_timer mx31moboard_timer = {
.init = mx31moboard_timer_init,
};
static void __init mx31moboard_reserve(void)
{
/* reserve 4 MiB for mx3-camera */
mx3_camera_base = memblock_alloc(MX3_CAMERA_BUF_SIZE,
MX3_CAMERA_BUF_SIZE);
memblock_free(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
memblock_remove(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
}
MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
/* Maintainer: Valentin Longchamp, EPFL Mobots group */
.boot_params = MX3x_PHYS_OFFSET + 0x100,
.reserve = mx31moboard_reserve,
.map_io = mx31_map_io,
.init_early = imx31_init_early,
.init_irq = mx31_init_irq,

1
arch/arm/mach-mx3/mach-mx35_3ds.c → arch/arm/mach-imx/mach-mx35_3ds.c
View File

@ -42,7 +42,6 @@
#include <mach/3ds_debugboard.h>
#include "devices-imx35.h"
#include "devices.h"
#define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 1)

1
arch/arm/mach-imx/mach-mxt_td60.c
View File

@ -29,7 +29,6 @@
#include <asm/mach/map.h>
#include <linux/gpio.h>
#include <mach/iomux-mx27.h>
#include <mach/mxc_nand.h>
#include <linux/i2c/pca953x.h>
#include "devices-imx27.h"

1
arch/arm/mach-imx/mach-pca100.c
View File

@ -37,7 +37,6 @@
#include <mach/iomux-mx27.h>
#include <asm/mach/time.h>
#include <mach/audmux.h>
#include <mach/mxc_nand.h>
#include <mach/irqs.h>
#include <mach/ulpi.h>

65
arch/arm/mach-mx3/mach-pcm037.c → arch/arm/mach-imx/mach-pcm037.c
View File

@ -31,6 +31,7 @@
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/gfp.h>
#include <linux/memblock.h>
#include <media/soc_camera.h>
@ -41,13 +42,9 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx3.h>
#include <mach/ipu.h>
#include <mach/mx3_camera.h>
#include <mach/mx3fb.h>
#include <mach/ulpi.h>
#include "devices-imx31.h"
#include "devices.h"
#include "pcm037.h"
static enum pcm037_board_variant pcm037_instance = PCM037_PCM970;
@ -404,35 +401,35 @@ static const struct imxmmc_platform_data sdhc_pdata __initconst = {
.exit = pcm970_sdhc1_exit,
};
struct mx3_camera_pdata camera_pdata = {
.dma_dev = &mx3_ipu.dev,
struct mx3_camera_pdata camera_pdata __initdata = {
.flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10,
.mclk_10khz = 2000,
};
static int __init pcm037_camera_alloc_dma(const size_t buf_size)
static phys_addr_t mx3_camera_base __initdata;
#define MX3_CAMERA_BUF_SIZE SZ_4M
static int __init pcm037_init_camera(void)
{
dma_addr_t dma_handle;
void *buf;
int dma;
int dma, ret = -ENOMEM;
struct platform_device *pdev = imx31_alloc_mx3_camera(&camera_pdata);
if (buf_size < 2 * 1024 * 1024)
return -EINVAL;
if (IS_ERR(pdev))
return PTR_ERR(pdev);
buf = dma_alloc_coherent(NULL, buf_size, &dma_handle, GFP_KERNEL);
if (!buf) {
pr_err("%s: cannot allocate camera buffer-memory\n", __func__);
return -ENOMEM;
}
memset(buf, 0, buf_size);
dma = dma_declare_coherent_memory(&mx3_camera.dev,
dma_handle, dma_handle, buf_size,
dma = dma_declare_coherent_memory(&pdev->dev,
mx3_camera_base, mx3_camera_base,
MX3_CAMERA_BUF_SIZE,
DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
if (!(dma & DMA_MEMORY_MAP))
goto err;
/* The way we call dma_declare_coherent_memory only a malloc can fail */
return dma & DMA_MEMORY_MAP ? 0 : -ENOMEM;
ret = platform_device_add(pdev);
if (ret)
err:
platform_device_put(pdev);
return ret;
}
static struct platform_device *devices[] __initdata = {
@ -442,7 +439,7 @@ static struct platform_device *devices[] __initdata = {
&pcm037_mt9v022,
};
static struct ipu_platform_data mx3_ipu_data = {
static const struct ipu_platform_data mx3_ipu_data __initconst = {
.irq_base = MXC_IPU_IRQ_START,
};
@ -500,7 +497,6 @@ static const struct fb_videomode fb_modedb[] = {
};
static struct mx3fb_platform_data mx3fb_pdata = {
.dma_dev = &mx3_ipu.dev,
.name = "Sharp-LQ035Q7DH06-QVGA",
.mode = fb_modedb,
.num_modes = ARRAY_SIZE(fb_modedb),
@ -638,8 +634,8 @@ static void __init pcm037_init(void)
imx31_add_mxc_nand(&pcm037_nand_board_info);
imx31_add_mxc_mmc(0, &sdhc_pdata);
mxc_register_device(&mx3_ipu, &mx3_ipu_data);
mxc_register_device(&mx3_fb, &mx3fb_pdata);
imx31_add_ipu_core(&mx3_ipu_data);
imx31_add_mx3_sdc_fb(&mx3fb_pdata);
/* CSI */
/* Camera power: default - off */
@ -649,8 +645,7 @@ static void __init pcm037_init(void)
else
iclink_mt9t031.power = NULL;
if (!pcm037_camera_alloc_dma(4 * 1024 * 1024))
mxc_register_device(&mx3_camera, &camera_pdata);
pcm037_init_camera();
platform_device_register(&pcm970_sja1000);
@ -680,9 +675,19 @@ struct sys_timer pcm037_timer = {
.init = pcm037_timer_init,
};
static void __init pcm037_reserve(void)
{
/* reserve 4 MiB for mx3-camera */
mx3_camera_base = memblock_alloc(MX3_CAMERA_BUF_SIZE,
MX3_CAMERA_BUF_SIZE);
memblock_free(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
memblock_remove(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
}
MACHINE_START(PCM037, "Phytec Phycore pcm037")
/* Maintainer: Pengutronix */
.boot_params = MX3x_PHYS_OFFSET + 0x100,
.reserve = pcm037_reserve,
.map_io = mx31_map_io,
.init_early = imx31_init_early,
.init_irq = mx31_init_irq,

17
arch/arm/mach-mx3/mach-pcm037_eet.c → arch/arm/mach-imx/mach-pcm037_eet.c
View File

@ -7,19 +7,16 @@
* published by the Free Software Foundation.
*/
#include <linux/gpio.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <mach/common.h>
#include <mach/iomux-mx3.h>
#include <mach/spi.h>
#include <asm/mach-types.h>
#include "pcm037.h"
#include "devices.h"
#include "devices-imx31.h"
static unsigned int pcm037_eet_pins[] = {
@ -156,20 +153,13 @@ static struct gpio_keys_button pcm037_gpio_keys[] = {
},
};
static struct gpio_keys_platform_data pcm037_gpio_keys_platform_data = {
static const struct gpio_keys_platform_data
pcm037_gpio_keys_platform_data __initconst = {
.buttons = pcm037_gpio_keys,
.nbuttons = ARRAY_SIZE(pcm037_gpio_keys),
.rep = 0, /* No auto-repeat */
};
static struct platform_device pcm037_gpio_keys_device = {
.name = "gpio-keys",
.id = -1,
.dev = {
.platform_data = &pcm037_gpio_keys_platform_data,
},
};
static int __init eet_init_devices(void)
{
if (!machine_is_pcm037() || pcm037_variant() != PCM037_EET)
@ -182,9 +172,8 @@ static int __init eet_init_devices(void)
spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev));
imx31_add_spi_imx0(&pcm037_spi1_pdata);
platform_device_register(&pcm037_gpio_keys_device);
imx_add_gpio_keys(&pcm037_gpio_keys_platform_data);
return 0;
}
late_initcall(eet_init_devices);

1
arch/arm/mach-imx/mach-pcm038.c
View File

@ -36,7 +36,6 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx27.h>
#include <mach/mxc_nand.h>
#include <mach/ulpi.h>
#include "devices-imx27.h"

17
arch/arm/mach-mx3/mach-pcm043.c → arch/arm/mach-imx/mach-pcm043.c
View File

@ -36,14 +36,10 @@
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/iomux-mx35.h>
#include <mach/ipu.h>
#include <mach/mx3fb.h>
#include <mach/ulpi.h>
#include <mach/audmux.h>
#include <mach/esdhc.h>
#include "devices-imx35.h"
#include "devices.h"
static const struct fb_videomode fb_modedb[] = {
{
@ -81,12 +77,11 @@ static const struct fb_videomode fb_modedb[] = {
},
};
static struct ipu_platform_data mx3_ipu_data = {
static const struct ipu_platform_data mx3_ipu_data __initconst = {
.irq_base = MXC_IPU_IRQ_START,
};
static struct mx3fb_platform_data mx3fb_pdata = {
.dma_dev = &mx3_ipu.dev,
static struct mx3fb_platform_data mx3fb_pdata __initdata = {
.name = "Sharp-LQ035Q7",
.mode = fb_modedb,
.num_modes = ARRAY_SIZE(fb_modedb),
@ -127,12 +122,12 @@ static struct at24_platform_data board_eeprom = {
};
static struct i2c_board_info pcm043_i2c_devices[] = {
{
{
I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
.platform_data = &board_eeprom,
}, {
I2C_BOARD_INFO("pcf8563", 0x51),
}
},
};
static struct platform_device *devices[] __initdata = {
@ -390,8 +385,8 @@ static void __init pcm043_init(void)
imx35_add_imx_i2c0(&pcm043_i2c0_data);
mxc_register_device(&mx3_ipu, &mx3_ipu_data);
mxc_register_device(&mx3_fb, &mx3fb_pdata);
imx35_add_ipu_core(&mx3_ipu_data);
imx35_add_mx3_sdc_fb(&mx3fb_pdata);
if (otg_mode_host) {
otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |

15
arch/arm/mach-mx3/mach-qong.c → arch/arm/mach-imx/mach-qong.c
View File

@ -33,24 +33,23 @@
#include <mach/iomux-mx3.h>
#include "devices-imx31.h"
#include "devices.h"
/* FPGA defines */
#define QONG_FPGA_VERSION(major, minor, rev) \
(((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF))
#define QONG_FPGA_BASEADDR MX31_CS1_BASE_ADDR
#define QONG_FPGA_PERIPH_SIZE (1 << 24)
#define QONG_FPGA_BASEADDR MX31_CS1_BASE_ADDR
#define QONG_FPGA_PERIPH_SIZE (1 << 24)
#define QONG_FPGA_CTRL_BASEADDR QONG_FPGA_BASEADDR
#define QONG_FPGA_CTRL_SIZE 0x10
#define QONG_FPGA_CTRL_SIZE 0x10
/* FPGA control registers */
#define QONG_FPGA_CTRL_VERSION 0x00
#define QONG_DNET_ID 1
#define QONG_DNET_BASEADDR \
(QONG_FPGA_BASEADDR + QONG_DNET_ID * QONG_FPGA_PERIPH_SIZE)
#define QONG_DNET_SIZE 0x00001000
#define QONG_DNET_SIZE 0x00001000
#define QONG_FPGA_IRQ IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1)
@ -166,15 +165,15 @@ static struct platform_nand_data qong_nand_data = {
.options = 0,
},
.ctrl = {
.cmd_ctrl = qong_nand_cmd_ctrl,
.cmd_ctrl = qong_nand_cmd_ctrl,
.dev_ready = qong_nand_device_ready,
.select_chip = qong_nand_select_chip,
}
};
static struct resource qong_nand_resource = {
.start = MX31_CS3_BASE_ADDR,
.end = MX31_CS3_BASE_ADDR + SZ_32M - 1,
.start = MX31_CS3_BASE_ADDR,
.end = MX31_CS3_BASE_ADDR + SZ_32M - 1,
.flags = IORESOURCE_MEM,
};

25
arch/arm/mach-mx3/mach-vpr200.c → arch/arm/mach-imx/mach-vpr200.c
View File

@ -32,16 +32,12 @@
#include <mach/common.h>
#include <mach/iomux-mx35.h>
#include <mach/irqs.h>
#include <mach/ipu.h>
#include <mach/mx3fb.h>
#include <linux/i2c.h>
#include <linux/i2c/at24.h>
#include <linux/mfd/mc13xxx.h>
#include <linux/gpio_keys.h>
#include "devices-imx35.h"
#include "devices.h"
#define GPIO_LCDPWR IMX_GPIO_NR(1, 2)
#define GPIO_PMIC_INT IMX_GPIO_NR(2, 0)
@ -91,12 +87,11 @@ static const struct fb_videomode fb_modedb[] = {
}
};
static struct ipu_platform_data mx3_ipu_data = {
static const struct ipu_platform_data mx3_ipu_data __initconst = {
.irq_base = MXC_IPU_IRQ_START,
};
static struct mx3fb_platform_data mx3fb_pdata = {
.dma_dev = &mx3_ipu.dev,
static struct mx3fb_platform_data mx3fb_pdata __initdata = {
.name = "PT0708048",
.mode = fb_modedb,
.num_modes = ARRAY_SIZE(fb_modedb),
@ -141,18 +136,12 @@ static struct gpio_keys_button vpr200_gpio_keys_table[] = {
{KEY_F9, GPIO_BUTTON8, 1, "vpr-keys: F9", 1, VPR_KEY_DEBOUNCE},
};
static struct gpio_keys_platform_data vpr200_gpio_keys_data = {
static const struct gpio_keys_platform_data
vpr200_gpio_keys_data __initconst = {
.buttons = vpr200_gpio_keys_table,
.nbuttons = ARRAY_SIZE(vpr200_gpio_keys_table),
};
static struct platform_device vpr200_device_gpiokeys = {
.name = "gpio-keys",
.dev = {
.platform_data = &vpr200_gpio_keys_data,
}
};
static struct mc13xxx_platform_data vpr200_pmic = {
.flags = MC13XXX_USE_ADC | MC13XXX_USE_TOUCHSCREEN,
};
@ -271,7 +260,6 @@ static const struct mxc_usbh_platform_data usb_host_pdata __initconst = {
static struct platform_device *devices[] __initdata = {
&vpr200_flash,
&vpr200_device_gpiokeys,
};
/*
@ -283,6 +271,7 @@ static void __init vpr200_board_init(void)
imx35_add_fec(NULL);
imx35_add_imx2_wdt(NULL);
imx_add_gpio_keys(&vpr200_gpio_keys_data);
platform_add_devices(devices, ARRAY_SIZE(devices));
@ -299,8 +288,8 @@ static void __init vpr200_board_init(void)
imx35_add_imx_uart0(NULL);
imx35_add_imx_uart2(NULL);
mxc_register_device(&mx3_ipu, &mx3_ipu_data);
mxc_register_device(&mx3_fb, &mx3fb_pdata);
imx35_add_ipu_core(&mx3_ipu_data);
imx35_add_mx3_sdc_fb(&mx3fb_pdata);
imx35_add_fsl_usb2_udc(&otg_device_pdata);
imx35_add_mxc_ehci_hs(&usb_host_pdata);

66
arch/arm/mach-imx/mm-imx31.c Normal file
View File

@ -0,0 +1,66 @@
/*
* Copyright (C) 1999,2000 Arm Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
* Copyright (C) 2002 Shane Nay (shane@minirl.com)
* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* - add MX31 specific definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/err.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-v3.h>
#include <mach/gpio.h>
#include <mach/irqs.h>
static struct map_desc mx31_io_desc[] __initdata = {
imx_map_entry(MX31, X_MEMC, MT_DEVICE),
imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
};
/*
* This function initializes the memory map. It is called during the
* system startup to create static physical to virtual memory mappings
* for the IO modules.
*/
void __init mx31_map_io(void)
{
iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
}
void __init imx31_init_early(void)
{
mxc_set_cpu_type(MXC_CPU_MX31);
mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
}
static struct mxc_gpio_port imx31_gpio_ports[] = {
DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1),
DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2),
DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3),
};
void __init mx31_init_irq(void)
{
mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
mxc_gpio_init(imx31_gpio_ports, ARRAY_SIZE(imx31_gpio_ports));
}

63
arch/arm/mach-imx/mm-imx35.c Normal file
View File

@ -0,0 +1,63 @@
/*
* Copyright (C) 1999,2000 Arm Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
* Copyright (C) 2002 Shane Nay (shane@minirl.com)
* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* - add MX31 specific definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/err.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
#include <asm/hardware/cache-l2x0.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-v3.h>
#include <mach/gpio.h>
#include <mach/irqs.h>
static struct map_desc mx35_io_desc[] __initdata = {
imx_map_entry(MX35, X_MEMC, MT_DEVICE),
imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
};
void __init mx35_map_io(void)
{
iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
}
void __init imx35_init_early(void)
{
mxc_set_cpu_type(MXC_CPU_MX35);
mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
}
static struct mxc_gpio_port imx35_gpio_ports[] = {
DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1),
DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2),
DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3),
};
void __init mx35_init_irq(void)
{
mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
mxc_gpio_init(imx35_gpio_ports, ARRAY_SIZE(imx35_gpio_ports));
}

13
arch/arm/mach-mx3/mx31lilly-db.c → arch/arm/mach-imx/mx31lilly-db.c
View File

@ -34,11 +34,8 @@
#include <mach/common.h>
#include <mach/iomux-mx3.h>
#include <mach/board-mx31lilly.h>
#include <mach/mx3fb.h>
#include <mach/ipu.h>
#include "devices-imx31.h"
#include "devices.h"
/*
* This file contains board-specific initialization routines for the
@ -164,13 +161,13 @@ static const struct imxmmc_platform_data mmc_pdata __initconst = {
};
/* Framebuffer support */
static struct ipu_platform_data ipu_data __initdata = {
static const struct ipu_platform_data ipu_data __initconst = {
.irq_base = MXC_IPU_IRQ_START,
};
static const struct fb_videomode fb_modedb = {
/* 640x480 TFT panel (IPS-056T) */
.name = "CRT-VGA",
.name = "CRT-VGA",
.refresh = 64,
.xres = 640,
.yres = 480,
@ -187,7 +184,6 @@ static const struct fb_videomode fb_modedb = {
};
static struct mx3fb_platform_data fb_pdata __initdata = {
.dma_dev = &mx3_ipu.dev,
.name = "CRT-VGA",
.mode = &fb_modedb,
.num_modes = 1,
@ -202,8 +198,8 @@ static void __init mx31lilly_init_fb(void)
return;
}
mxc_register_device(&mx3_ipu, &ipu_data);
mxc_register_device(&mx3_fb, &fb_pdata);
imx31_add_ipu_core(&ipu_data);
imx31_add_mx3_sdc_fb(&fb_pdata);
gpio_direction_output(LCD_VCC_EN_GPIO, 1);
}
@ -218,4 +214,3 @@ void __init mx31lilly_db_init(void)
imx31_add_mxc_mmc(0, &mmc_pdata);
mx31lilly_init_fb();
}

3
arch/arm/mach-mx3/mx31lite-db.c → arch/arm/mach-imx/mx31lite-db.c
View File

@ -37,7 +37,6 @@
#include <mach/board-mx31lite.h>
#include "devices-imx31.h"
#include "devices.h"
/*
* This file contains board-specific initialization routines for the
@ -200,5 +199,5 @@ void __init mx31lite_db_init(void)
imx31_add_spi_imx0(&spi0_pdata);
platform_device_register(&litekit_led_device);
imx31_add_imx2_wdt(NULL);
mxc_register_device(&imx_rtc_device0, NULL);
imx31_add_mxc_rtc(NULL);
}

1
arch/arm/mach-mx3/mx31moboard-devboard.c → arch/arm/mach-imx/mx31moboard-devboard.c
View File

@ -28,7 +28,6 @@
#include <mach/ulpi.h>
#include "devices-imx31.h"
#include "devices.h"
static unsigned int devboard_pins[] = {
/* UART1 */

2
arch/arm/mach-mx3/mx31moboard-marxbot.c → arch/arm/mach-imx/mx31moboard-marxbot.c
View File

@ -26,14 +26,12 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx3.h>
#include <mach/ulpi.h>
#include <media/soc_camera.h>
#include "devices-imx31.h"
#include "devices.h"
static unsigned int marxbot_pins[] = {
/* SDHC2 */

1
arch/arm/mach-mx3/mx31moboard-smartbot.c → arch/arm/mach-imx/mx31moboard-smartbot.c
View File

@ -32,7 +32,6 @@
#include <media/soc_camera.h>
#include "devices-imx31.h"
#include "devices.h"
static unsigned int smartbot_pins[] = {
/* UART1 */

0
arch/arm/mach-mx3/pcm037.h → arch/arm/mach-imx/pcm037.h
View File

2
arch/arm/mach-iop32x/include/mach/uncompress.h
View File

@ -7,7 +7,7 @@
#include <linux/serial_reg.h>
#include <mach/hardware.h>
static volatile u8 *uart_base;
volatile u8 *uart_base;
#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)

2
arch/arm/mach-iop33x/include/mach/uncompress.h
View File

@ -7,7 +7,7 @@
#include <linux/serial_reg.h>
#include <mach/hardware.h>
static volatile u32 *uart_base;
volatile u32 *uart_base;
#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)

2
arch/arm/mach-ixp4xx/include/mach/uncompress.h
View File

@ -19,7 +19,7 @@
#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE)
static volatile u32* uart_base;
volatile u32* uart_base;
static inline void putc(int c)
{

603
arch/arm/mach-kirkwood/common.c
View File

@ -13,11 +13,9 @@
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/mbus.h>
#include <linux/mv643xx_eth.h>
#include <linux/mv643xx_i2c.h>
#include <linux/ata_platform.h>
#include <linux/mtd/nand.h>
#include <linux/spi/orion_spi.h>
#include <linux/dma-mapping.h>
#include <net/dsa.h>
#include <asm/page.h>
#include <asm/timex.h>
@ -28,11 +26,9 @@
#include <mach/bridge-regs.h>
#include <plat/audio.h>
#include <plat/cache-feroceon-l2.h>
#include <plat/ehci-orion.h>
#include <plat/mvsdio.h>
#include <plat/mv_xor.h>
#include <plat/orion_nand.h>
#include <plat/orion_wdt.h>
#include <plat/common.h>
#include <plat/time.h>
#include "common.h"
@ -69,210 +65,52 @@ void __init kirkwood_map_io(void)
* registered. Some reserved bits must be set to 1.
*/
unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED;
/*****************************************************************************
* EHCI
****************************************************************************/
static struct orion_ehci_data kirkwood_ehci_data = {
.dram = &kirkwood_mbus_dram_info,
.phy_version = EHCI_PHY_NA,
};
static u64 ehci_dmamask = 0xffffffffUL;
/*****************************************************************************
* EHCI0
****************************************************************************/
static struct resource kirkwood_ehci_resources[] = {
{
.start = USB_PHYS_BASE,
.end = USB_PHYS_BASE + 0x0fff,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_KIRKWOOD_USB,
.end = IRQ_KIRKWOOD_USB,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device kirkwood_ehci = {
.name = "orion-ehci",
.id = 0,
.dev = {
.dma_mask = &ehci_dmamask,
.coherent_dma_mask = 0xffffffff,
.platform_data = &kirkwood_ehci_data,
},
.resource = kirkwood_ehci_resources,
.num_resources = ARRAY_SIZE(kirkwood_ehci_resources),
};
void __init kirkwood_ehci_init(void)
{
kirkwood_clk_ctrl |= CGC_USB0;
platform_device_register(&kirkwood_ehci);
orion_ehci_init(&kirkwood_mbus_dram_info,
USB_PHYS_BASE, IRQ_KIRKWOOD_USB);
}
/*****************************************************************************
* GE00
****************************************************************************/
struct mv643xx_eth_shared_platform_data kirkwood_ge00_shared_data = {
.dram = &kirkwood_mbus_dram_info,
};
static struct resource kirkwood_ge00_shared_resources[] = {
{
.name = "ge00 base",
.start = GE00_PHYS_BASE + 0x2000,
.end = GE00_PHYS_BASE + 0x3fff,
.flags = IORESOURCE_MEM,
}, {
.name = "ge00 err irq",
.start = IRQ_KIRKWOOD_GE00_ERR,
.end = IRQ_KIRKWOOD_GE00_ERR,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device kirkwood_ge00_shared = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 0,
.dev = {
.platform_data = &kirkwood_ge00_shared_data,
},
.num_resources = ARRAY_SIZE(kirkwood_ge00_shared_resources),
.resource = kirkwood_ge00_shared_resources,
};
static struct resource kirkwood_ge00_resources[] = {
{
.name = "ge00 irq",
.start = IRQ_KIRKWOOD_GE00_SUM,
.end = IRQ_KIRKWOOD_GE00_SUM,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device kirkwood_ge00 = {
.name = MV643XX_ETH_NAME,
.id = 0,
.num_resources = 1,
.resource = kirkwood_ge00_resources,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
{
kirkwood_clk_ctrl |= CGC_GE0;
eth_data->shared = &kirkwood_ge00_shared;
kirkwood_ge00.dev.platform_data = eth_data;
platform_device_register(&kirkwood_ge00_shared);
platform_device_register(&kirkwood_ge00);
orion_ge00_init(eth_data, &kirkwood_mbus_dram_info,
GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM,
IRQ_KIRKWOOD_GE00_ERR, kirkwood_tclk);
}
/*****************************************************************************
* GE01
****************************************************************************/
struct mv643xx_eth_shared_platform_data kirkwood_ge01_shared_data = {
.dram = &kirkwood_mbus_dram_info,
.shared_smi = &kirkwood_ge00_shared,
};
static struct resource kirkwood_ge01_shared_resources[] = {
{
.name = "ge01 base",
.start = GE01_PHYS_BASE + 0x2000,
.end = GE01_PHYS_BASE + 0x3fff,
.flags = IORESOURCE_MEM,
}, {
.name = "ge01 err irq",
.start = IRQ_KIRKWOOD_GE01_ERR,
.end = IRQ_KIRKWOOD_GE01_ERR,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device kirkwood_ge01_shared = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 1,
.dev = {
.platform_data = &kirkwood_ge01_shared_data,
},
.num_resources = ARRAY_SIZE(kirkwood_ge01_shared_resources),
.resource = kirkwood_ge01_shared_resources,
};
static struct resource kirkwood_ge01_resources[] = {
{
.name = "ge01 irq",
.start = IRQ_KIRKWOOD_GE01_SUM,
.end = IRQ_KIRKWOOD_GE01_SUM,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device kirkwood_ge01 = {
.name = MV643XX_ETH_NAME,
.id = 1,
.num_resources = 1,
.resource = kirkwood_ge01_resources,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
{
kirkwood_clk_ctrl |= CGC_GE1;
eth_data->shared = &kirkwood_ge01_shared;
kirkwood_ge01.dev.platform_data = eth_data;
platform_device_register(&kirkwood_ge01_shared);
platform_device_register(&kirkwood_ge01);
kirkwood_clk_ctrl |= CGC_GE1;
orion_ge01_init(eth_data, &kirkwood_mbus_dram_info,
GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM,
IRQ_KIRKWOOD_GE01_ERR, kirkwood_tclk);
}
/*****************************************************************************
* Ethernet switch
****************************************************************************/
static struct resource kirkwood_switch_resources[] = {
{
.start = 0,
.end = 0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device kirkwood_switch_device = {
.name = "dsa",
.id = 0,
.num_resources = 0,
.resource = kirkwood_switch_resources,
};
void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq)
{
int i;
if (irq != NO_IRQ) {
kirkwood_switch_resources[0].start = irq;
kirkwood_switch_resources[0].end = irq;
kirkwood_switch_device.num_resources = 1;
}
d->netdev = &kirkwood_ge00.dev;
for (i = 0; i < d->nr_chips; i++)
d->chip[i].mii_bus = &kirkwood_ge00_shared.dev;
kirkwood_switch_device.dev.platform_data = d;
platform_device_register(&kirkwood_switch_device);
orion_ge00_switch_init(d, irq);
}
@ -325,53 +163,23 @@ void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
/*****************************************************************************
* SoC RTC
****************************************************************************/
static struct resource kirkwood_rtc_resource = {
.start = RTC_PHYS_BASE,
.end = RTC_PHYS_BASE + SZ_16 - 1,
.flags = IORESOURCE_MEM,
};
static void __init kirkwood_rtc_init(void)
{
platform_device_register_simple("rtc-mv", -1, &kirkwood_rtc_resource, 1);
orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
}
/*****************************************************************************
* SATA
****************************************************************************/
static struct resource kirkwood_sata_resources[] = {
{
.name = "sata base",
.start = SATA_PHYS_BASE,
.end = SATA_PHYS_BASE + 0x5000 - 1,
.flags = IORESOURCE_MEM,
}, {
.name = "sata irq",
.start = IRQ_KIRKWOOD_SATA,
.end = IRQ_KIRKWOOD_SATA,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device kirkwood_sata = {
.name = "sata_mv",
.id = 0,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(kirkwood_sata_resources),
.resource = kirkwood_sata_resources,
};
void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
{
kirkwood_clk_ctrl |= CGC_SATA0;
if (sata_data->n_ports > 1)
kirkwood_clk_ctrl |= CGC_SATA1;
sata_data->dram = &kirkwood_mbus_dram_info;
kirkwood_sata.dev.platform_data = sata_data;
platform_device_register(&kirkwood_sata);
orion_sata_init(sata_data, &kirkwood_mbus_dram_info,
SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
}
@ -391,14 +199,14 @@ static struct resource mvsdio_resources[] = {
},
};
static u64 mvsdio_dmamask = 0xffffffffUL;
static u64 mvsdio_dmamask = DMA_BIT_MASK(32);
static struct platform_device kirkwood_sdio = {
.name = "mvsdio",
.id = -1,
.dev = {
.dma_mask = &mvsdio_dmamask,
.coherent_dma_mask = 0xffffffff,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(mvsdio_resources),
.resource = mvsdio_resources,
@ -423,424 +231,84 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
/*****************************************************************************
* SPI
****************************************************************************/
static struct orion_spi_info kirkwood_spi_plat_data = {
};
static struct resource kirkwood_spi_resources[] = {
{
.start = SPI_PHYS_BASE,
.end = SPI_PHYS_BASE + SZ_512 - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device kirkwood_spi = {
.name = "orion_spi",
.id = 0,
.resource = kirkwood_spi_resources,
.dev = {
.platform_data = &kirkwood_spi_plat_data,
},
.num_resources = ARRAY_SIZE(kirkwood_spi_resources),
};
void __init kirkwood_spi_init()
{
kirkwood_clk_ctrl |= CGC_RUNIT;
platform_device_register(&kirkwood_spi);
orion_spi_init(SPI_PHYS_BASE, kirkwood_tclk);
}
/*****************************************************************************
* I2C
****************************************************************************/
static struct mv64xxx_i2c_pdata kirkwood_i2c_pdata = {
.freq_m = 8, /* assumes 166 MHz TCLK */
.freq_n = 3,
.timeout = 1000, /* Default timeout of 1 second */
};
static struct resource kirkwood_i2c_resources[] = {
{
.start = I2C_PHYS_BASE,
.end = I2C_PHYS_BASE + 0x1f,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_KIRKWOOD_TWSI,
.end = IRQ_KIRKWOOD_TWSI,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device kirkwood_i2c = {
.name = MV64XXX_I2C_CTLR_NAME,
.id = 0,
.num_resources = ARRAY_SIZE(kirkwood_i2c_resources),
.resource = kirkwood_i2c_resources,
.dev = {
.platform_data = &kirkwood_i2c_pdata,
},
};
void __init kirkwood_i2c_init(void)
{
platform_device_register(&kirkwood_i2c);
orion_i2c_init(I2C_PHYS_BASE, IRQ_KIRKWOOD_TWSI, 8);
}
/*****************************************************************************
* UART0
****************************************************************************/
static struct plat_serial8250_port kirkwood_uart0_data[] = {
{
.mapbase = UART0_PHYS_BASE,
.membase = (char *)UART0_VIRT_BASE,
.irq = IRQ_KIRKWOOD_UART_0,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = 0,
}, {
},
};
static struct resource kirkwood_uart0_resources[] = {
{
.start = UART0_PHYS_BASE,
.end = UART0_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_KIRKWOOD_UART_0,
.end = IRQ_KIRKWOOD_UART_0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device kirkwood_uart0 = {
.name = "serial8250",
.id = 0,
.dev = {
.platform_data = kirkwood_uart0_data,
},
.resource = kirkwood_uart0_resources,
.num_resources = ARRAY_SIZE(kirkwood_uart0_resources),
};
void __init kirkwood_uart0_init(void)
{
platform_device_register(&kirkwood_uart0);
orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
IRQ_KIRKWOOD_UART_0, kirkwood_tclk);
}
/*****************************************************************************
* UART1
****************************************************************************/
static struct plat_serial8250_port kirkwood_uart1_data[] = {
{
.mapbase = UART1_PHYS_BASE,
.membase = (char *)UART1_VIRT_BASE,
.irq = IRQ_KIRKWOOD_UART_1,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = 0,
}, {
},
};
static struct resource kirkwood_uart1_resources[] = {
{
.start = UART1_PHYS_BASE,
.end = UART1_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_KIRKWOOD_UART_1,
.end = IRQ_KIRKWOOD_UART_1,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device kirkwood_uart1 = {
.name = "serial8250",
.id = 1,
.dev = {
.platform_data = kirkwood_uart1_data,
},
.resource = kirkwood_uart1_resources,
.num_resources = ARRAY_SIZE(kirkwood_uart1_resources),
};
void __init kirkwood_uart1_init(void)
{
platform_device_register(&kirkwood_uart1);
orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
IRQ_KIRKWOOD_UART_1, kirkwood_tclk);
}
/*****************************************************************************
* Cryptographic Engines and Security Accelerator (CESA)
****************************************************************************/
static struct resource kirkwood_crypto_res[] = {
{
.name = "regs",
.start = CRYPTO_PHYS_BASE,
.end = CRYPTO_PHYS_BASE + 0xffff,
.flags = IORESOURCE_MEM,
}, {
.name = "sram",
.start = KIRKWOOD_SRAM_PHYS_BASE,
.end = KIRKWOOD_SRAM_PHYS_BASE + KIRKWOOD_SRAM_SIZE - 1,
.flags = IORESOURCE_MEM,
}, {
.name = "crypto interrupt",
.start = IRQ_KIRKWOOD_CRYPTO,
.end = IRQ_KIRKWOOD_CRYPTO,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device kirkwood_crypto_device = {
.name = "mv_crypto",
.id = -1,
.num_resources = ARRAY_SIZE(kirkwood_crypto_res),
.resource = kirkwood_crypto_res,
};
void __init kirkwood_crypto_init(void)
{
kirkwood_clk_ctrl |= CGC_CRYPTO;
platform_device_register(&kirkwood_crypto_device);
orion_crypto_init(CRYPTO_PHYS_BASE, KIRKWOOD_SRAM_PHYS_BASE,
KIRKWOOD_SRAM_SIZE, IRQ_KIRKWOOD_CRYPTO);
}
/*****************************************************************************
* XOR
****************************************************************************/
static struct mv_xor_platform_shared_data kirkwood_xor_shared_data = {
.dram = &kirkwood_mbus_dram_info,
};
static u64 kirkwood_xor_dmamask = DMA_BIT_MASK(32);
/*****************************************************************************
* XOR0
****************************************************************************/
static struct resource kirkwood_xor0_shared_resources[] = {
{
.name = "xor 0 low",
.start = XOR0_PHYS_BASE,
.end = XOR0_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
}, {
.name = "xor 0 high",
.start = XOR0_HIGH_PHYS_BASE,
.end = XOR0_HIGH_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device kirkwood_xor0_shared = {
.name = MV_XOR_SHARED_NAME,
.id = 0,
.dev = {
.platform_data = &kirkwood_xor_shared_data,
},
.num_resources = ARRAY_SIZE(kirkwood_xor0_shared_resources),
.resource = kirkwood_xor0_shared_resources,
};
static struct resource kirkwood_xor00_resources[] = {
[0] = {
.start = IRQ_KIRKWOOD_XOR_00,
.end = IRQ_KIRKWOOD_XOR_00,
.flags = IORESOURCE_IRQ,
},
};
static struct mv_xor_platform_data kirkwood_xor00_data = {
.shared = &kirkwood_xor0_shared,
.hw_id = 0,
.pool_size = PAGE_SIZE,
};
static struct platform_device kirkwood_xor00_channel = {
.name = MV_XOR_NAME,
.id = 0,
.num_resources = ARRAY_SIZE(kirkwood_xor00_resources),
.resource = kirkwood_xor00_resources,
.dev = {
.dma_mask = &kirkwood_xor_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(64),
.platform_data = &kirkwood_xor00_data,
},
};
static struct resource kirkwood_xor01_resources[] = {
[0] = {
.start = IRQ_KIRKWOOD_XOR_01,
.end = IRQ_KIRKWOOD_XOR_01,
.flags = IORESOURCE_IRQ,
},
};
static struct mv_xor_platform_data kirkwood_xor01_data = {
.shared = &kirkwood_xor0_shared,
.hw_id = 1,
.pool_size = PAGE_SIZE,
};
static struct platform_device kirkwood_xor01_channel = {
.name = MV_XOR_NAME,
.id = 1,
.num_resources = ARRAY_SIZE(kirkwood_xor01_resources),
.resource = kirkwood_xor01_resources,
.dev = {
.dma_mask = &kirkwood_xor_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(64),
.platform_data = &kirkwood_xor01_data,
},
};
static void __init kirkwood_xor0_init(void)
{
kirkwood_clk_ctrl |= CGC_XOR0;
platform_device_register(&kirkwood_xor0_shared);
/*
* two engines can't do memset simultaneously, this limitation
* satisfied by removing memset support from one of the engines.
*/
dma_cap_set(DMA_MEMCPY, kirkwood_xor00_data.cap_mask);
dma_cap_set(DMA_XOR, kirkwood_xor00_data.cap_mask);
platform_device_register(&kirkwood_xor00_channel);
dma_cap_set(DMA_MEMCPY, kirkwood_xor01_data.cap_mask);
dma_cap_set(DMA_MEMSET, kirkwood_xor01_data.cap_mask);
dma_cap_set(DMA_XOR, kirkwood_xor01_data.cap_mask);
platform_device_register(&kirkwood_xor01_channel);
orion_xor0_init(&kirkwood_mbus_dram_info,
XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE,
IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01);
}
/*****************************************************************************
* XOR1
****************************************************************************/
static struct resource kirkwood_xor1_shared_resources[] = {
{
.name = "xor 1 low",
.start = XOR1_PHYS_BASE,
.end = XOR1_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
}, {
.name = "xor 1 high",
.start = XOR1_HIGH_PHYS_BASE,
.end = XOR1_HIGH_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device kirkwood_xor1_shared = {
.name = MV_XOR_SHARED_NAME,
.id = 1,
.dev = {
.platform_data = &kirkwood_xor_shared_data,
},
.num_resources = ARRAY_SIZE(kirkwood_xor1_shared_resources),
.resource = kirkwood_xor1_shared_resources,
};
static struct resource kirkwood_xor10_resources[] = {
[0] = {
.start = IRQ_KIRKWOOD_XOR_10,
.end = IRQ_KIRKWOOD_XOR_10,
.flags = IORESOURCE_IRQ,
},
};
static struct mv_xor_platform_data kirkwood_xor10_data = {
.shared = &kirkwood_xor1_shared,
.hw_id = 0,
.pool_size = PAGE_SIZE,
};
static struct platform_device kirkwood_xor10_channel = {
.name = MV_XOR_NAME,
.id = 2,
.num_resources = ARRAY_SIZE(kirkwood_xor10_resources),
.resource = kirkwood_xor10_resources,
.dev = {
.dma_mask = &kirkwood_xor_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(64),
.platform_data = &kirkwood_xor10_data,
},
};
static struct resource kirkwood_xor11_resources[] = {
[0] = {
.start = IRQ_KIRKWOOD_XOR_11,
.end = IRQ_KIRKWOOD_XOR_11,
.flags = IORESOURCE_IRQ,
},
};
static struct mv_xor_platform_data kirkwood_xor11_data = {
.shared = &kirkwood_xor1_shared,
.hw_id = 1,
.pool_size = PAGE_SIZE,
};
static struct platform_device kirkwood_xor11_channel = {
.name = MV_XOR_NAME,
.id = 3,
.num_resources = ARRAY_SIZE(kirkwood_xor11_resources),
.resource = kirkwood_xor11_resources,
.dev = {
.dma_mask = &kirkwood_xor_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(64),
.platform_data = &kirkwood_xor11_data,
},
};
static void __init kirkwood_xor1_init(void)
{
kirkwood_clk_ctrl |= CGC_XOR1;
platform_device_register(&kirkwood_xor1_shared);
/*
* two engines can't do memset simultaneously, this limitation
* satisfied by removing memset support from one of the engines.
*/
dma_cap_set(DMA_MEMCPY, kirkwood_xor10_data.cap_mask);
dma_cap_set(DMA_XOR, kirkwood_xor10_data.cap_mask);
platform_device_register(&kirkwood_xor10_channel);
dma_cap_set(DMA_MEMCPY, kirkwood_xor11_data.cap_mask);
dma_cap_set(DMA_MEMSET, kirkwood_xor11_data.cap_mask);
dma_cap_set(DMA_XOR, kirkwood_xor11_data.cap_mask);
platform_device_register(&kirkwood_xor11_channel);
orion_xor1_init(XOR1_PHYS_BASE, XOR1_HIGH_PHYS_BASE,
IRQ_KIRKWOOD_XOR_10, IRQ_KIRKWOOD_XOR_11);
}
/*****************************************************************************
* Watchdog
****************************************************************************/
static struct orion_wdt_platform_data kirkwood_wdt_data = {
.tclk = 0,
};
static struct platform_device kirkwood_wdt_device = {
.name = "orion_wdt",
.id = -1,
.dev = {
.platform_data = &kirkwood_wdt_data,
},
.num_resources = 0,
};
static void __init kirkwood_wdt_init(void)
{
kirkwood_wdt_data.tclk = kirkwood_tclk;
platform_device_register(&kirkwood_wdt_device);
orion_wdt_init(kirkwood_tclk);
}
@ -984,11 +452,6 @@ void __init kirkwood_init(void)
{
printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
kirkwood_id(), kirkwood_tclk);
kirkwood_ge00_shared_data.t_clk = kirkwood_tclk;
kirkwood_ge01_shared_data.t_clk = kirkwood_tclk;
kirkwood_spi_plat_data.tclk = kirkwood_tclk;
kirkwood_uart0_data[0].uartclk = kirkwood_tclk;
kirkwood_uart1_data[0].uartclk = kirkwood_tclk;
kirkwood_i2s_data.tclk = kirkwood_tclk;
/*

1
arch/arm/mach-kirkwood/include/mach/irqs.h
View File

@ -51,6 +51,7 @@
#define IRQ_KIRKWOOD_GPIO_HIGH_16_23 41
#define IRQ_KIRKWOOD_GE00_ERR 46
#define IRQ_KIRKWOOD_GE01_ERR 47
#define IRQ_KIRKWOOD_RTC 53
/*
* KIRKWOOD General Purpose Pins

58
arch/arm/mach-kirkwood/mpp.c
View File

@ -14,6 +14,7 @@
#include <linux/io.h>
#include <asm/gpio.h>
#include <mach/hardware.h>
#include <plat/mpp.h>
#include "common.h"
#include "mpp.h"
@ -36,61 +37,8 @@ static unsigned int __init kirkwood_variant(void)
return 0;
}
#define MPP_CTRL(i) (DEV_BUS_VIRT_BASE + (i) * 4)
#define MPP_NR_REGS (1 + MPP_MAX/8)
void __init kirkwood_mpp_conf(unsigned int *mpp_list)
{
u32 mpp_ctrl[MPP_NR_REGS];
unsigned int variant_mask;
int i;
variant_mask = kirkwood_variant();
if (!variant_mask)
return;
printk(KERN_DEBUG "initial MPP regs:");
for (i = 0; i < MPP_NR_REGS; i++) {
mpp_ctrl[i] = readl(MPP_CTRL(i));
printk(" %08x", mpp_ctrl[i]);
}
printk("\n");
for ( ; *mpp_list; mpp_list++) {
unsigned int num = MPP_NUM(*mpp_list);
unsigned int sel = MPP_SEL(*mpp_list);
int shift, gpio_mode;
if (num > MPP_MAX) {
printk(KERN_ERR "kirkwood_mpp_conf: invalid MPP "
"number (%u)\n", num);
continue;
}
if (!(*mpp_list & variant_mask)) {
printk(KERN_WARNING
"kirkwood_mpp_conf: requested MPP%u config "
"unavailable on this hardware\n", num);
continue;
}
shift = (num & 7) << 2;
mpp_ctrl[num / 8] &= ~(0xf << shift);
mpp_ctrl[num / 8] |= sel << shift;
gpio_mode = 0;
if (*mpp_list & MPP_INPUT_MASK)
gpio_mode |= GPIO_INPUT_OK;
if (*mpp_list & MPP_OUTPUT_MASK)
gpio_mode |= GPIO_OUTPUT_OK;
if (sel != 0)
gpio_mode = 0;
orion_gpio_set_valid(num, gpio_mode);
}
printk(KERN_DEBUG " final MPP regs:");
for (i = 0; i < MPP_NR_REGS; i++) {
writel(mpp_ctrl[i], MPP_CTRL(i));
printk(" %08x", mpp_ctrl[i]);
}
printk("\n");
orion_mpp_conf(mpp_list, kirkwood_variant(),
MPP_MAX, DEV_BUS_VIRT_BASE);
}

6
arch/arm/mach-kirkwood/mpp.h
View File

@ -22,14 +22,8 @@
/* available on F6281 */ ((!!(_F6281)) << 17) | \
/* available on F6282 */ ((!!(_F6282)) << 18))
#define MPP_NUM(x) ((x) & 0xff)
#define MPP_SEL(x) (((x) >> 8) & 0xf)
/* num sel i o 6180 6190 6192 6281 6282 */
#define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0, 0 )
#define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0, 0 )
#define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0, 0 )
#define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0, 0 )
#define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0, 0 )

190
arch/arm/mach-loki/common.c
View File

@ -13,7 +13,7 @@
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/mbus.h>
#include <linux/mv643xx_eth.h>
#include <linux/dma-mapping.h>
#include <asm/page.h>
#include <asm/timex.h>
#include <asm/mach/map.h>
@ -22,6 +22,7 @@
#include <mach/loki.h>
#include <plat/orion_nand.h>
#include <plat/time.h>
#include <plat/common.h>
#include "common.h"
/*****************************************************************************
@ -43,116 +44,28 @@ void __init loki_map_io(void)
/*****************************************************************************
* GE0
* GE00
****************************************************************************/
struct mv643xx_eth_shared_platform_data loki_ge0_shared_data = {
.t_clk = LOKI_TCLK,
.dram = &loki_mbus_dram_info,
};
static struct resource loki_ge0_shared_resources[] = {
{
.name = "ge0 base",
.start = GE0_PHYS_BASE + 0x2000,
.end = GE0_PHYS_BASE + 0x3fff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device loki_ge0_shared = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 0,
.dev = {
.platform_data = &loki_ge0_shared_data,
},
.num_resources = 1,
.resource = loki_ge0_shared_resources,
};
static struct resource loki_ge0_resources[] = {
{
.name = "ge0 irq",
.start = IRQ_LOKI_GBE_A_INT,
.end = IRQ_LOKI_GBE_A_INT,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device loki_ge0 = {
.name = MV643XX_ETH_NAME,
.id = 0,
.num_resources = 1,
.resource = loki_ge0_resources,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
void __init loki_ge0_init(struct mv643xx_eth_platform_data *eth_data)
{
eth_data->shared = &loki_ge0_shared;
loki_ge0.dev.platform_data = eth_data;
writel(0x00079220, GE0_VIRT_BASE + 0x20b0);
platform_device_register(&loki_ge0_shared);
platform_device_register(&loki_ge0);
orion_ge00_init(eth_data, &loki_mbus_dram_info,
GE0_PHYS_BASE, IRQ_LOKI_GBE_A_INT,
0, LOKI_TCLK);
}
/*****************************************************************************
* GE1
* GE01
****************************************************************************/
struct mv643xx_eth_shared_platform_data loki_ge1_shared_data = {
.t_clk = LOKI_TCLK,
.dram = &loki_mbus_dram_info,
};
static struct resource loki_ge1_shared_resources[] = {
{
.name = "ge1 base",
.start = GE1_PHYS_BASE + 0x2000,
.end = GE1_PHYS_BASE + 0x3fff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device loki_ge1_shared = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 1,
.dev = {
.platform_data = &loki_ge1_shared_data,
},
.num_resources = 1,
.resource = loki_ge1_shared_resources,
};
static struct resource loki_ge1_resources[] = {
{
.name = "ge1 irq",
.start = IRQ_LOKI_GBE_B_INT,
.end = IRQ_LOKI_GBE_B_INT,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device loki_ge1 = {
.name = MV643XX_ETH_NAME,
.id = 1,
.num_resources = 1,
.resource = loki_ge1_resources,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
void __init loki_ge1_init(struct mv643xx_eth_platform_data *eth_data)
{
eth_data->shared = &loki_ge1_shared;
loki_ge1.dev.platform_data = eth_data;
writel(0x00079220, GE1_VIRT_BASE + 0x20b0);
platform_device_register(&loki_ge1_shared);
platform_device_register(&loki_ge1);
orion_ge01_init(eth_data, &loki_mbus_dram_info,
GE1_PHYS_BASE, IRQ_LOKI_GBE_B_INT,
0, LOKI_TCLK);
}
@ -187,7 +100,7 @@ static struct platform_device loki_sas = {
.name = "mvsas",
.id = 0,
.dev = {
.coherent_dma_mask = 0xffffffff,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(loki_sas_resources),
.resource = loki_sas_resources,
@ -203,88 +116,19 @@ void __init loki_sas_init(void)
/*****************************************************************************
* UART0
****************************************************************************/
static struct plat_serial8250_port loki_uart0_data[] = {
{
.mapbase = UART0_PHYS_BASE,
.membase = (char *)UART0_VIRT_BASE,
.irq = IRQ_LOKI_UART0,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = LOKI_TCLK,
}, {
},
};
static struct resource loki_uart0_resources[] = {
{
.start = UART0_PHYS_BASE,
.end = UART0_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_LOKI_UART0,
.end = IRQ_LOKI_UART0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device loki_uart0 = {
.name = "serial8250",
.id = 0,
.dev = {
.platform_data = loki_uart0_data,
},
.resource = loki_uart0_resources,
.num_resources = ARRAY_SIZE(loki_uart0_resources),
};
void __init loki_uart0_init(void)
{
platform_device_register(&loki_uart0);
orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
IRQ_LOKI_UART0, LOKI_TCLK);
}
/*****************************************************************************
* UART1
****************************************************************************/
static struct plat_serial8250_port loki_uart1_data[] = {
{
.mapbase = UART1_PHYS_BASE,
.membase = (char *)UART1_VIRT_BASE,
.irq = IRQ_LOKI_UART1,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = LOKI_TCLK,
}, {
},
};
static struct resource loki_uart1_resources[] = {
{
.start = UART1_PHYS_BASE,
.end = UART1_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_LOKI_UART1,
.end = IRQ_LOKI_UART1,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device loki_uart1 = {
.name = "serial8250",
.id = 1,
.dev = {
.platform_data = loki_uart1_data,
},
.resource = loki_uart1_resources,
.num_resources = ARRAY_SIZE(loki_uart1_resources),
};
void __init loki_uart1_init(void)
{
platform_device_register(&loki_uart1);
orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
IRQ_LOKI_UART1, LOKI_TCLK);
}

2
arch/arm/mach-mmp/include/mach/uncompress.h
View File

@ -14,7 +14,7 @@
#define UART2_BASE (APB_PHYS_BASE + 0x17000)
#define UART3_BASE (APB_PHYS_BASE + 0x18000)
static volatile unsigned long *UART;
volatile unsigned long *UART;
static inline void putc(char c)
{

10
arch/arm/mach-msm/gpio-v2.c
View File

@ -27,6 +27,9 @@
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <asm/mach/irq.h>
#include <mach/msm_iomap.h>
#include "gpiomux.h"
@ -309,8 +312,10 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
*/
static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
{
struct irq_data *data = irq_desc_get_irq_data(desc);
unsigned long i;
struct irq_chip *chip = irq_desc_get_chip(desc);
chained_irq_enter(chip, desc);
for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS);
i < NR_GPIO_IRQS;
@ -319,7 +324,8 @@ static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip,
i));
}
data->chip->irq_ack(data);
chained_irq_exit(chip, desc);
}
static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)

570
arch/arm/mach-mv78xx0/common.c
View File

@ -13,8 +13,6 @@
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/mbus.h>
#include <linux/mv643xx_eth.h>
#include <linux/mv643xx_i2c.h>
#include <linux/ata_platform.h>
#include <linux/ethtool.h>
#include <asm/mach/map.h>
@ -22,11 +20,12 @@
#include <mach/mv78xx0.h>
#include <mach/bridge-regs.h>
#include <plat/cache-feroceon-l2.h>
#include <plat/ehci-orion.h>
#include <plat/orion_nand.h>
#include <plat/time.h>
#include <plat/common.h>
#include "common.h"
static int get_tclk(void);
/*****************************************************************************
* Common bits
@ -168,285 +167,62 @@ void __init mv78xx0_map_io(void)
/*****************************************************************************
* EHCI
****************************************************************************/
static struct orion_ehci_data mv78xx0_ehci_data = {
.dram = &mv78xx0_mbus_dram_info,
.phy_version = EHCI_PHY_NA,
};
static u64 ehci_dmamask = 0xffffffffUL;
/*****************************************************************************
* EHCI0
****************************************************************************/
static struct resource mv78xx0_ehci0_resources[] = {
{
.start = USB0_PHYS_BASE,
.end = USB0_PHYS_BASE + 0x0fff,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_MV78XX0_USB_0,
.end = IRQ_MV78XX0_USB_0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mv78xx0_ehci0 = {
.name = "orion-ehci",
.id = 0,
.dev = {
.dma_mask = &ehci_dmamask,
.coherent_dma_mask = 0xffffffff,
.platform_data = &mv78xx0_ehci_data,
},
.resource = mv78xx0_ehci0_resources,
.num_resources = ARRAY_SIZE(mv78xx0_ehci0_resources),
};
void __init mv78xx0_ehci0_init(void)
{
platform_device_register(&mv78xx0_ehci0);
orion_ehci_init(&mv78xx0_mbus_dram_info,
USB0_PHYS_BASE, IRQ_MV78XX0_USB_0);
}
/*****************************************************************************
* EHCI1
****************************************************************************/
static struct resource mv78xx0_ehci1_resources[] = {
{
.start = USB1_PHYS_BASE,
.end = USB1_PHYS_BASE + 0x0fff,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_MV78XX0_USB_1,
.end = IRQ_MV78XX0_USB_1,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mv78xx0_ehci1 = {
.name = "orion-ehci",
.id = 1,
.dev = {
.dma_mask = &ehci_dmamask,
.coherent_dma_mask = 0xffffffff,
.platform_data = &mv78xx0_ehci_data,
},
.resource = mv78xx0_ehci1_resources,
.num_resources = ARRAY_SIZE(mv78xx0_ehci1_resources),
};
void __init mv78xx0_ehci1_init(void)
{
platform_device_register(&mv78xx0_ehci1);
orion_ehci_1_init(&mv78xx0_mbus_dram_info,
USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
}
/*****************************************************************************
* EHCI2
****************************************************************************/
static struct resource mv78xx0_ehci2_resources[] = {
{
.start = USB2_PHYS_BASE,
.end = USB2_PHYS_BASE + 0x0fff,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_MV78XX0_USB_2,
.end = IRQ_MV78XX0_USB_2,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mv78xx0_ehci2 = {
.name = "orion-ehci",
.id = 2,
.dev = {
.dma_mask = &ehci_dmamask,
.coherent_dma_mask = 0xffffffff,
.platform_data = &mv78xx0_ehci_data,
},
.resource = mv78xx0_ehci2_resources,
.num_resources = ARRAY_SIZE(mv78xx0_ehci2_resources),
};
void __init mv78xx0_ehci2_init(void)
{
platform_device_register(&mv78xx0_ehci2);
orion_ehci_2_init(&mv78xx0_mbus_dram_info,
USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
}
/*****************************************************************************
* GE00
****************************************************************************/
struct mv643xx_eth_shared_platform_data mv78xx0_ge00_shared_data = {
.t_clk = 0,
.dram = &mv78xx0_mbus_dram_info,
};
static struct resource mv78xx0_ge00_shared_resources[] = {
{
.name = "ge00 base",
.start = GE00_PHYS_BASE + 0x2000,
.end = GE00_PHYS_BASE + 0x3fff,
.flags = IORESOURCE_MEM,
}, {
.name = "ge err irq",
.start = IRQ_MV78XX0_GE_ERR,
.end = IRQ_MV78XX0_GE_ERR,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mv78xx0_ge00_shared = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 0,
.dev = {
.platform_data = &mv78xx0_ge00_shared_data,
},
.num_resources = ARRAY_SIZE(mv78xx0_ge00_shared_resources),
.resource = mv78xx0_ge00_shared_resources,
};
static struct resource mv78xx0_ge00_resources[] = {
{
.name = "ge00 irq",
.start = IRQ_MV78XX0_GE00_SUM,
.end = IRQ_MV78XX0_GE00_SUM,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mv78xx0_ge00 = {
.name = MV643XX_ETH_NAME,
.id = 0,
.num_resources = 1,
.resource = mv78xx0_ge00_resources,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
{
eth_data->shared = &mv78xx0_ge00_shared;
mv78xx0_ge00.dev.platform_data = eth_data;
platform_device_register(&mv78xx0_ge00_shared);
platform_device_register(&mv78xx0_ge00);
orion_ge00_init(eth_data, &mv78xx0_mbus_dram_info,
GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
IRQ_MV78XX0_GE_ERR, get_tclk());
}
/*****************************************************************************
* GE01
****************************************************************************/
struct mv643xx_eth_shared_platform_data mv78xx0_ge01_shared_data = {
.t_clk = 0,
.dram = &mv78xx0_mbus_dram_info,
.shared_smi = &mv78xx0_ge00_shared,
};
static struct resource mv78xx0_ge01_shared_resources[] = {
{
.name = "ge01 base",
.start = GE01_PHYS_BASE + 0x2000,
.end = GE01_PHYS_BASE + 0x3fff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device mv78xx0_ge01_shared = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 1,
.dev = {
.platform_data = &mv78xx0_ge01_shared_data,
},
.num_resources = 1,
.resource = mv78xx0_ge01_shared_resources,
};
static struct resource mv78xx0_ge01_resources[] = {
{
.name = "ge01 irq",
.start = IRQ_MV78XX0_GE01_SUM,
.end = IRQ_MV78XX0_GE01_SUM,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mv78xx0_ge01 = {
.name = MV643XX_ETH_NAME,
.id = 1,
.num_resources = 1,
.resource = mv78xx0_ge01_resources,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
{
eth_data->shared = &mv78xx0_ge01_shared;
mv78xx0_ge01.dev.platform_data = eth_data;
platform_device_register(&mv78xx0_ge01_shared);
platform_device_register(&mv78xx0_ge01);
orion_ge01_init(eth_data, &mv78xx0_mbus_dram_info,
GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
NO_IRQ, get_tclk());
}
/*****************************************************************************
* GE10
****************************************************************************/
struct mv643xx_eth_shared_platform_data mv78xx0_ge10_shared_data = {
.t_clk = 0,
.dram = &mv78xx0_mbus_dram_info,
.shared_smi = &mv78xx0_ge00_shared,
};
static struct resource mv78xx0_ge10_shared_resources[] = {
{
.name = "ge10 base",
.start = GE10_PHYS_BASE + 0x2000,
.end = GE10_PHYS_BASE + 0x3fff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device mv78xx0_ge10_shared = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 2,
.dev = {
.platform_data = &mv78xx0_ge10_shared_data,
},
.num_resources = 1,
.resource = mv78xx0_ge10_shared_resources,
};
static struct resource mv78xx0_ge10_resources[] = {
{
.name = "ge10 irq",
.start = IRQ_MV78XX0_GE10_SUM,
.end = IRQ_MV78XX0_GE10_SUM,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mv78xx0_ge10 = {
.name = MV643XX_ETH_NAME,
.id = 2,
.num_resources = 1,
.resource = mv78xx0_ge10_resources,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
{
u32 dev, rev;
eth_data->shared = &mv78xx0_ge10_shared;
mv78xx0_ge10.dev.platform_data = eth_data;
/*
* On the Z0, ge10 and ge11 are internally connected back
* to back, and not brought out.
@ -458,65 +234,19 @@ void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
eth_data->duplex = DUPLEX_FULL;
}
platform_device_register(&mv78xx0_ge10_shared);
platform_device_register(&mv78xx0_ge10);
orion_ge10_init(eth_data, &mv78xx0_mbus_dram_info,
GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM,
NO_IRQ, get_tclk());
}
/*****************************************************************************
* GE11
****************************************************************************/
struct mv643xx_eth_shared_platform_data mv78xx0_ge11_shared_data = {
.t_clk = 0,
.dram = &mv78xx0_mbus_dram_info,
.shared_smi = &mv78xx0_ge00_shared,
};
static struct resource mv78xx0_ge11_shared_resources[] = {
{
.name = "ge11 base",
.start = GE11_PHYS_BASE + 0x2000,
.end = GE11_PHYS_BASE + 0x3fff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device mv78xx0_ge11_shared = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 3,
.dev = {
.platform_data = &mv78xx0_ge11_shared_data,
},
.num_resources = 1,
.resource = mv78xx0_ge11_shared_resources,
};
static struct resource mv78xx0_ge11_resources[] = {
{
.name = "ge11 irq",
.start = IRQ_MV78XX0_GE11_SUM,
.end = IRQ_MV78XX0_GE11_SUM,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mv78xx0_ge11 = {
.name = MV643XX_ETH_NAME,
.id = 3,
.num_resources = 1,
.resource = mv78xx0_ge11_resources,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
{
u32 dev, rev;
eth_data->shared = &mv78xx0_ge11_shared;
mv78xx0_ge11.dev.platform_data = eth_data;
/*
* On the Z0, ge10 and ge11 are internally connected back
* to back, and not brought out.
@ -528,293 +258,68 @@ void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
eth_data->duplex = DUPLEX_FULL;
}
platform_device_register(&mv78xx0_ge11_shared);
platform_device_register(&mv78xx0_ge11);
orion_ge11_init(eth_data, &mv78xx0_mbus_dram_info,
GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM,
NO_IRQ, get_tclk());
}
/*****************************************************************************
* I2C bus 0
* I2C
****************************************************************************/
static struct mv64xxx_i2c_pdata mv78xx0_i2c_0_pdata = {
.freq_m = 8, /* assumes 166 MHz TCLK */
.freq_n = 3,
.timeout = 1000, /* Default timeout of 1 second */
};
static struct resource mv78xx0_i2c_0_resources[] = {
{
.start = I2C_0_PHYS_BASE,
.end = I2C_0_PHYS_BASE + 0x1f,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_MV78XX0_I2C_0,
.end = IRQ_MV78XX0_I2C_0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mv78xx0_i2c_0 = {
.name = MV64XXX_I2C_CTLR_NAME,
.id = 0,
.num_resources = ARRAY_SIZE(mv78xx0_i2c_0_resources),
.resource = mv78xx0_i2c_0_resources,
.dev = {
.platform_data = &mv78xx0_i2c_0_pdata,
},
};
/*****************************************************************************
* I2C bus 1
****************************************************************************/
static struct mv64xxx_i2c_pdata mv78xx0_i2c_1_pdata = {
.freq_m = 8, /* assumes 166 MHz TCLK */
.freq_n = 3,
.timeout = 1000, /* Default timeout of 1 second */
};
static struct resource mv78xx0_i2c_1_resources[] = {
{
.start = I2C_1_PHYS_BASE,
.end = I2C_1_PHYS_BASE + 0x1f,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_MV78XX0_I2C_1,
.end = IRQ_MV78XX0_I2C_1,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mv78xx0_i2c_1 = {
.name = MV64XXX_I2C_CTLR_NAME,
.id = 1,
.num_resources = ARRAY_SIZE(mv78xx0_i2c_1_resources),
.resource = mv78xx0_i2c_1_resources,
.dev = {
.platform_data = &mv78xx0_i2c_1_pdata,
},
};
void __init mv78xx0_i2c_init(void)
{
platform_device_register(&mv78xx0_i2c_0);
platform_device_register(&mv78xx0_i2c_1);
orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8);
orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8);
}
/*****************************************************************************
* SATA
****************************************************************************/
static struct resource mv78xx0_sata_resources[] = {
{
.name = "sata base",
.start = SATA_PHYS_BASE,
.end = SATA_PHYS_BASE + 0x5000 - 1,
.flags = IORESOURCE_MEM,
}, {
.name = "sata irq",
.start = IRQ_MV78XX0_SATA,
.end = IRQ_MV78XX0_SATA,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mv78xx0_sata = {
.name = "sata_mv",
.id = 0,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(mv78xx0_sata_resources),
.resource = mv78xx0_sata_resources,
};
void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
{
sata_data->dram = &mv78xx0_mbus_dram_info;
mv78xx0_sata.dev.platform_data = sata_data;
platform_device_register(&mv78xx0_sata);
orion_sata_init(sata_data, &mv78xx0_mbus_dram_info,
SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
}
/*****************************************************************************
* UART0
****************************************************************************/
static struct plat_serial8250_port mv78xx0_uart0_data[] = {
{
.mapbase = UART0_PHYS_BASE,
.membase = (char *)UART0_VIRT_BASE,
.irq = IRQ_MV78XX0_UART_0,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = 0,
}, {
},
};
static struct resource mv78xx0_uart0_resources[] = {
{
.start = UART0_PHYS_BASE,
.end = UART0_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_MV78XX0_UART_0,
.end = IRQ_MV78XX0_UART_0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mv78xx0_uart0 = {
.name = "serial8250",
.id = 0,
.dev = {
.platform_data = mv78xx0_uart0_data,
},
.resource = mv78xx0_uart0_resources,
.num_resources = ARRAY_SIZE(mv78xx0_uart0_resources),
};
void __init mv78xx0_uart0_init(void)
{
platform_device_register(&mv78xx0_uart0);
orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
IRQ_MV78XX0_UART_0, get_tclk());
}
/*****************************************************************************
* UART1
****************************************************************************/
static struct plat_serial8250_port mv78xx0_uart1_data[] = {
{
.mapbase = UART1_PHYS_BASE,
.membase = (char *)UART1_VIRT_BASE,
.irq = IRQ_MV78XX0_UART_1,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = 0,
}, {
},
};
static struct resource mv78xx0_uart1_resources[] = {
{
.start = UART1_PHYS_BASE,
.end = UART1_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_MV78XX0_UART_1,
.end = IRQ_MV78XX0_UART_1,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mv78xx0_uart1 = {
.name = "serial8250",
.id = 1,
.dev = {
.platform_data = mv78xx0_uart1_data,
},
.resource = mv78xx0_uart1_resources,
.num_resources = ARRAY_SIZE(mv78xx0_uart1_resources),
};
void __init mv78xx0_uart1_init(void)
{
platform_device_register(&mv78xx0_uart1);
orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
IRQ_MV78XX0_UART_1, get_tclk());
}
/*****************************************************************************
* UART2
****************************************************************************/
static struct plat_serial8250_port mv78xx0_uart2_data[] = {
{
.mapbase = UART2_PHYS_BASE,
.membase = (char *)UART2_VIRT_BASE,
.irq = IRQ_MV78XX0_UART_2,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = 0,
}, {
},
};
static struct resource mv78xx0_uart2_resources[] = {
{
.start = UART2_PHYS_BASE,
.end = UART2_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_MV78XX0_UART_2,
.end = IRQ_MV78XX0_UART_2,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mv78xx0_uart2 = {
.name = "serial8250",
.id = 2,
.dev = {
.platform_data = mv78xx0_uart2_data,
},
.resource = mv78xx0_uart2_resources,
.num_resources = ARRAY_SIZE(mv78xx0_uart2_resources),
};
void __init mv78xx0_uart2_init(void)
{
platform_device_register(&mv78xx0_uart2);
orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE,
IRQ_MV78XX0_UART_2, get_tclk());
}
/*****************************************************************************
* UART3
****************************************************************************/
static struct plat_serial8250_port mv78xx0_uart3_data[] = {
{
.mapbase = UART3_PHYS_BASE,
.membase = (char *)UART3_VIRT_BASE,
.irq = IRQ_MV78XX0_UART_3,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = 0,
}, {
},
};
static struct resource mv78xx0_uart3_resources[] = {
{
.start = UART3_PHYS_BASE,
.end = UART3_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_MV78XX0_UART_3,
.end = IRQ_MV78XX0_UART_3,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mv78xx0_uart3 = {
.name = "serial8250",
.id = 3,
.dev = {
.platform_data = mv78xx0_uart3_data,
},
.resource = mv78xx0_uart3_resources,
.num_resources = ARRAY_SIZE(mv78xx0_uart3_resources),
};
void __init mv78xx0_uart3_init(void)
{
platform_device_register(&mv78xx0_uart3);
orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE,
IRQ_MV78XX0_UART_3, get_tclk());
}
/*****************************************************************************
* Time handling
****************************************************************************/
@ -895,13 +400,4 @@ void __init mv78xx0_init(void)
#ifdef CONFIG_CACHE_FEROCEON_L2
feroceon_l2_init(is_l2_writethrough());
#endif
mv78xx0_ge00_shared_data.t_clk = tclk;
mv78xx0_ge01_shared_data.t_clk = tclk;
mv78xx0_ge10_shared_data.t_clk = tclk;
mv78xx0_ge11_shared_data.t_clk = tclk;
mv78xx0_uart0_data[0].uartclk = tclk;
mv78xx0_uart1_data[0].uartclk = tclk;
mv78xx0_uart2_data[0].uartclk = tclk;
mv78xx0_uart3_data[0].uartclk = tclk;
}

58
arch/arm/mach-mv78xx0/mpp.c
View File

@ -12,6 +12,7 @@
#include <linux/init.h>
#include <linux/mbus.h>
#include <linux/io.h>
#include <plat/mpp.h>
#include <asm/gpio.h>
#include <mach/hardware.h>
#include "common.h"
@ -31,61 +32,8 @@ static unsigned int __init mv78xx0_variant(void)
return 0;
}
#define MPP_CTRL(i) (DEV_BUS_VIRT_BASE + (i) * 4)
#define MPP_NR_REGS (1 + MPP_MAX/8)
void __init mv78xx0_mpp_conf(unsigned int *mpp_list)
{
u32 mpp_ctrl[MPP_NR_REGS];
unsigned int variant_mask;
int i;
variant_mask = mv78xx0_variant();
if (!variant_mask)
return;
printk(KERN_DEBUG "initial MPP regs:");
for (i = 0; i < MPP_NR_REGS; i++) {
mpp_ctrl[i] = readl(MPP_CTRL(i));
printk(" %08x", mpp_ctrl[i]);
}
printk("\n");
for ( ; *mpp_list; mpp_list++) {
unsigned int num = MPP_NUM(*mpp_list);
unsigned int sel = MPP_SEL(*mpp_list);
int shift, gpio_mode;
if (num > MPP_MAX) {
printk(KERN_ERR "mv78xx0_mpp_conf: invalid MPP "
"number (%u)\n", num);
continue;
}
if (!(*mpp_list & variant_mask)) {
printk(KERN_WARNING
"mv78xx0_mpp_conf: requested MPP%u config "
"unavailable on this hardware\n", num);
continue;
}
shift = (num & 7) << 2;
mpp_ctrl[num / 8] &= ~(0xf << shift);
mpp_ctrl[num / 8] |= sel << shift;
gpio_mode = 0;
if (*mpp_list & MPP_INPUT_MASK)
gpio_mode |= GPIO_INPUT_OK;
if (*mpp_list & MPP_OUTPUT_MASK)
gpio_mode |= GPIO_OUTPUT_OK;
if (sel != 0)
gpio_mode = 0;
orion_gpio_set_valid(num, gpio_mode);
}
printk(KERN_DEBUG " final MPP regs:");
for (i = 0; i < MPP_NR_REGS; i++) {
writel(mpp_ctrl[i], MPP_CTRL(i));
printk(" %08x", mpp_ctrl[i]);
}
printk("\n");
orion_mpp_conf(mpp_list, mv78xx0_variant(),
MPP_MAX, DEV_BUS_VIRT_BASE);
}

6
arch/arm/mach-mv78xx0/mpp.h
View File

@ -19,14 +19,8 @@
/* may be output signal */ ((!!(_out)) << 13) | \
/* available on A0 */ ((!!(_78100_A0)) << 14))
#define MPP_NUM(x) ((x) & 0xff)
#define MPP_SEL(x) (((x) >> 8) & 0xf)
/* num sel i o 78100_A0 */
#define MPP_INPUT_MASK MPP(0, 0x0, 1, 0, 0)
#define MPP_OUTPUT_MASK MPP(0, 0x0, 0, 1, 0)
#define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1)
#define MPP0_GPIO MPP(0, 0x0, 1, 1, 1)

257
arch/arm/mach-mx3/Kconfig
View File

@ -1,257 +0,0 @@
if ARCH_MX3
# ARCH_MX31 and ARCH_MX35 are left for compatibility
# Some usages assume that having one of them implies not having (e.g.) ARCH_MX2.
# To easily distinguish good and reviewed from unreviewed usages new (and IMHO
# more sensible) names are used: SOC_IMX31 and SOC_IMX35
config ARCH_MX31
bool
config ARCH_MX35
bool
config SOC_IMX31
bool
select IMX_HAVE_PLATFORM_MXC_RNGA
select ARCH_MXC_AUDMUX_V2
select ARCH_MX31
select MXC_AVIC
config SOC_IMX35
bool
select ARCH_MXC_IOMUX_V3
select ARCH_MXC_AUDMUX_V2
select HAVE_EPIT
select ARCH_MX35
select MXC_AVIC
comment "MX3 platforms:"
config MACH_MX31ADS
bool "Support MX31ADS platforms"
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IMX_UART
default y
help
Include support for MX31ADS platform. This includes specific
configurations for the board and its peripherals.
config MACH_MX31ADS_WM1133_EV1
bool "Support Wolfson Microelectronics 1133-EV1 module"
depends on MACH_MX31ADS
depends on MFD_WM8350_I2C
depends on REGULATOR_WM8350
select MFD_WM8350_CONFIG_MODE_0
select MFD_WM8352_CONFIG_MODE_0
help
Include support for the Wolfson Microelectronics 1133-EV1 PMU
and audio module for the MX31ADS platform.
config MACH_PCM037
bool "Support Phytec pcm037 (i.MX31) platforms"
select SOC_IMX31
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_MXC_W1
select MXC_ULPI if USB_ULPI
help
Include support for Phytec pcm037 platform. This includes
specific configurations for the board and its peripherals.
config MACH_PCM037_EET
bool "Support pcm037 EET board extensions"
depends on MACH_PCM037
select IMX_HAVE_PLATFORM_SPI_IMX
help
Add support for PCM037 EET baseboard extensions. If you are using the
OLED display with EET, use "video=mx3fb:CMEL-OLED" kernel
command-line parameter.
config MACH_MX31LITE
bool "Support MX31 LITEKIT (LogicPD)"
select SOC_IMX31
select MXC_ULPI if USB_ULPI
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SPI_IMX
help
Include support for MX31 LITEKIT platform. This includes specific
configurations for the board and its peripherals.
config MACH_MX31_3DS
bool "Support MX31PDK (3DS)"
select SOC_IMX31
select MXC_DEBUG_BOARD
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_KEYPAD
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_ULPI if USB_ULPI
help
Include support for MX31PDK (3DS) platform. This includes specific
configurations for the board and its peripherals.
config MACH_MX31_3DS_MXC_NAND_USE_BBT
bool "Make the MXC NAND driver use the in flash Bad Block Table"
depends on MACH_MX31_3DS
depends on MTD_NAND_MXC
help
Enable this if you want that the MXC NAND driver uses the in flash
Bad Block Table to know what blocks are bad instead of scanning the
entire flash looking for bad block markers.
config MACH_MX31MOBOARD
bool "Support mx31moboard platforms (EPFL Mobots group)"
select SOC_IMX31
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_ULPI if USB_ULPI
help
Include support for mx31moboard platform. This includes specific
configurations for the board and its peripherals.
config MACH_MX31LILLY
bool "Support MX31 LILLY-1131 platforms (INCO startec)"
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_ULPI if USB_ULPI
help
Include support for mx31 based LILLY1131 modules. This includes
specific configurations for the board and its peripherals.
config MACH_QONG
bool "Support Dave/DENX QongEVB-LITE platform"
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_UART
help
Include support for Dave/DENX QongEVB-LITE platform. This includes
specific configurations for the board and its peripherals.
config MACH_PCM043
bool "Support Phytec pcm043 (i.MX35) platforms"
select SOC_IMX35
select IMX_HAVE_PLATFORM_FLEXCAN
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select MXC_ULPI if USB_ULPI
help
Include support for Phytec pcm043 platform. This includes
specific configurations for the board and its peripherals.
config MACH_ARMADILLO5X0
bool "Support Atmark Armadillo-500 Development Base Board"
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
select MXC_ULPI if USB_ULPI
help
Include support for Atmark Armadillo-500 platform. This includes
specific configurations for the board and its peripherals.
config MACH_MX35_3DS
bool "Support MX35PDK platform"
select SOC_IMX35
select MXC_DEBUG_BOARD
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
help
Include support for MX35PDK platform. This includes specific
configurations for the board and its peripherals.
config MACH_KZM_ARM11_01
bool "Support KZM-ARM11-01(Kyoto Microcomputer)"
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_UART
help
Include support for KZM-ARM11-01. This includes specific
configurations for the board and its peripherals.
config MACH_BUG
bool "Support Buglabs BUGBase platform"
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_UART
default y
help
Include support for BUGBase 1.3 platform. This includes specific
configurations for the board and its peripherals.
config MACH_EUKREA_CPUIMX35
bool "Support Eukrea CPUIMX35 Platform"
select SOC_IMX35
select IMX_HAVE_PLATFORM_FLEXCAN
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select MXC_ULPI if USB_ULPI
help
Include support for Eukrea CPUIMX35 platform. This includes
specific configurations for the board and its peripherals.
choice
prompt "Baseboard"
depends on MACH_EUKREA_CPUIMX35
default MACH_EUKREA_MBIMXSD35_BASEBOARD
config MACH_EUKREA_MBIMXSD35_BASEBOARD
bool "Eukrea MBIMXSD development board"
select IMX_HAVE_PLATFORM_IMX_SSI
help
This adds board specific devices that can be found on Eukrea's
MBIMXSD evaluation board.
endchoice
config MACH_VPR200
bool "Support VPR200 platform"
select SOC_IMX35
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
help
Include support for VPR200 platform. This includes specific
configurations for the board and its peripherals.
endif

26
arch/arm/mach-mx3/Makefile
View File

@ -1,26 +0,0 @@
#
# Makefile for the linux kernel.
#
# Object file lists.
obj-y := mm.o devices.o cpu.o
obj-$(CONFIG_SOC_IMX31) += clock-imx31.o iomux-imx31.o ehci-imx31.o
obj-$(CONFIG_SOC_IMX35) += clock-imx35.o ehci-imx35.o
obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o
obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o
obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o
obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o
obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o
obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o
obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \
mx31moboard-marxbot.o mx31moboard-smartbot.o
obj-$(CONFIG_MACH_QONG) += mach-qong.o
obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o
obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o
obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o
obj-$(CONFIG_MACH_BUG) += mach-bug.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX35) += mach-cpuimx35.o
obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd-baseboard.o
obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o

3
arch/arm/mach-mx3/Makefile.boot
View File

@ -1,3 +0,0 @@
zreladdr-y := 0x80008000
params_phys-y := 0x80000100
initrd_phys-y := 0x80800000

115
arch/arm/mach-mx3/devices.c
View File

@ -1,115 +0,0 @@
/*
* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Sascha Hauer, kernel@pengutronix.de
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor,
* Boston, MA 02110-1301, USA.
*/
#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/serial.h>
#include <linux/gpio.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <mach/common.h>
#include <mach/mx3_camera.h>
#include "devices.h"
/* i.MX31 Image Processing Unit */
/* The resource order is important! */
static struct resource mx3_ipu_rsrc[] = {
{
.start = MX3x_IPU_CTRL_BASE_ADDR,
.end = MX3x_IPU_CTRL_BASE_ADDR + 0x5F,
.flags = IORESOURCE_MEM,
}, {
.start = MX3x_IPU_CTRL_BASE_ADDR + 0x88,
.end = MX3x_IPU_CTRL_BASE_ADDR + 0xB3,
.flags = IORESOURCE_MEM,
}, {
.start = MX3x_INT_IPU_SYN,
.end = MX3x_INT_IPU_SYN,
.flags = IORESOURCE_IRQ,
}, {
.start = MX3x_INT_IPU_ERR,
.end = MX3x_INT_IPU_ERR,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mx3_ipu = {
.name = "ipu-core",
.id = -1,
.num_resources = ARRAY_SIZE(mx3_ipu_rsrc),
.resource = mx3_ipu_rsrc,
};
static struct resource fb_resources[] = {
{
.start = MX3x_IPU_CTRL_BASE_ADDR + 0xB4,
.end = MX3x_IPU_CTRL_BASE_ADDR + 0x1BF,
.flags = IORESOURCE_MEM,
},
};
struct platform_device mx3_fb = {
.name = "mx3_sdc_fb",
.id = -1,
.num_resources = ARRAY_SIZE(fb_resources),
.resource = fb_resources,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
static struct resource camera_resources[] = {
{
.start = MX3x_IPU_CTRL_BASE_ADDR + 0x60,
.end = MX3x_IPU_CTRL_BASE_ADDR + 0x87,
.flags = IORESOURCE_MEM,
},
};
struct platform_device mx3_camera = {
.name = "mx3-camera",
.id = 0,
.num_resources = ARRAY_SIZE(camera_resources),
.resource = camera_resources,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
static struct resource imx_rtc_resources[] = {
{
.start = MX31_RTC_BASE_ADDR,
.end = MX31_RTC_BASE_ADDR + 0x3fff,
.flags = IORESOURCE_MEM,
},
{
.start = MX31_INT_RTC,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device imx_rtc_device0 = {
.name = "mxc_rtc",
.id = -1,
.num_resources = ARRAY_SIZE(imx_rtc_resources),
.resource = imx_rtc_resources,
};

4
arch/arm/mach-mx3/devices.h
View File

@ -1,4 +0,0 @@
extern struct platform_device mx3_ipu;
extern struct platform_device mx3_fb;
extern struct platform_device mx3_camera;
extern struct platform_device imx_rtc_device0;

141
arch/arm/mach-mx3/mm.c
View File

@ -1,141 +0,0 @@
/*
* Copyright (C) 1999,2000 Arm Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
* Copyright (C) 2002 Shane Nay (shane@minirl.com)
* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* - add MX31 specific definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/err.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
#include <asm/hardware/cache-l2x0.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-v3.h>
#include <mach/gpio.h>
#include <mach/irqs.h>
#ifdef CONFIG_SOC_IMX31
static struct map_desc mx31_io_desc[] __initdata = {
imx_map_entry(MX31, X_MEMC, MT_DEVICE),
imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
};
/*
* This function initializes the memory map. It is called during the
* system startup to create static physical to virtual memory mappings
* for the IO modules.
*/
void __init mx31_map_io(void)
{
iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
}
void __init imx31_init_early(void)
{
mxc_set_cpu_type(MXC_CPU_MX31);
mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
}
static struct mxc_gpio_port imx31_gpio_ports[] = {
DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1),
DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2),
DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3),
};
void __init mx31_init_irq(void)
{
mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
mxc_gpio_init(imx31_gpio_ports, ARRAY_SIZE(imx31_gpio_ports));
}
#endif /* ifdef CONFIG_SOC_IMX31 */
#ifdef CONFIG_SOC_IMX35
static struct map_desc mx35_io_desc[] __initdata = {
imx_map_entry(MX35, X_MEMC, MT_DEVICE),
imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
};
void __init mx35_map_io(void)
{
iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
}
void __init imx35_init_early(void)
{
mxc_set_cpu_type(MXC_CPU_MX35);
mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
}
static struct mxc_gpio_port imx35_gpio_ports[] = {
DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1),
DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2),
DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3),
};
void __init mx35_init_irq(void)
{
mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
mxc_gpio_init(imx35_gpio_ports, ARRAY_SIZE(imx35_gpio_ports));
}
#endif /* ifdef CONFIG_SOC_IMX35 */
#ifdef CONFIG_CACHE_L2X0
static int mxc_init_l2x0(void)
{
void __iomem *l2x0_base;
void __iomem *clkctl_base;
/*
* First of all, we must repair broken chip settings. There are some
* i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
* misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
* Workaraound is to setup the correct register setting prior enabling the
* L2 cache. This should not hurt already working CPUs, as they are using the
* same value
*/
#define L2_MEM_VAL 0x10
clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
if (clkctl_base != NULL) {
writel(0x00000515, clkctl_base + L2_MEM_VAL);
iounmap(clkctl_base);
} else {
pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
}
l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
if (IS_ERR(l2x0_base)) {
printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
PTR_ERR(l2x0_base));
return 0;
}
l2x0_init(l2x0_base, 0x00030024, 0x00000000);
return 0;
}
arch_initcall(mxc_init_l2x0);
#endif

58
arch/arm/mach-mx5/Kconfig
View File

@ -1,11 +1,11 @@
if ARCH_MX5
# ARCH_MX50/51/53 are left to mark places where prevent multi-soc in single
if ARCH_MX503 || ARCH_MX51
# ARCH_MX5/50/53 are left to mark places where prevent multi-soc in single
# image. So for most time, SOC_IMX50/51/53 should be used.
config ARCH_MX50
config ARCH_MX5
bool
config ARCH_MX51
config ARCH_MX50
bool
config ARCH_MX53
@ -13,27 +13,54 @@ config ARCH_MX53
config SOC_IMX50
bool
select CPU_V7
select ARM_L1_CACHE_SHIFT_6
select MXC_TZIC
select ARCH_MXC_IOMUX_V3
select ARCH_MXC_AUDMUX_V2
select ARCH_HAS_CPUFREQ
select ARCH_MX5
select ARCH_MX50
config SOC_IMX51
bool
select CPU_V7
select ARM_L1_CACHE_SHIFT_6
select MXC_TZIC
select ARCH_MXC_IOMUX_V3
select ARCH_MXC_AUDMUX_V2
select ARCH_HAS_CPUFREQ
select ARCH_MX51
select ARCH_MX5
config SOC_IMX53
bool
select CPU_V7
select ARM_L1_CACHE_SHIFT_6
select MXC_TZIC
select ARCH_MXC_IOMUX_V3
select ARCH_MX5
select ARCH_MX53
comment "MX5 platforms:"
if ARCH_MX50_SUPPORTED
#comment "i.MX50 machines:"
config MACH_MX50_RDP
bool "Support MX50 reference design platform"
depends on BROKEN
select SOC_IMX50
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select IMX_HAVE_PLATFORM_SPI_IMX
select IMX_HAVE_PLATFORM_FEC
help
Include support for MX50 reference design platform (RDP) board. This
includes specific configurations for the board and its peripherals.
endif # ARCH_MX50_SUPPORTED
if ARCH_MX51
comment "i.MX51 machines:"
config MACH_MX51_BABBAGE
bool "Support MX51 BABBAGE platforms"
@ -136,6 +163,11 @@ config MACH_MX51_EFIKASB
Include support for Genesi Efika Smartbook. This includes specific
configurations for the board and its peripherals.
endif # ARCH_MX51
if ARCH_MX53_SUPPORTED
comment "i.MX53 machines:"
config MACH_MX53_EVK
bool "Support MX53 EVK platforms"
select SOC_IMX53
@ -154,6 +186,7 @@ config MACH_MX53_SMD
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
help
Include support for MX53 SMD platform. This includes specific
configurations for the board and its peripherals.
@ -170,17 +203,6 @@ config MACH_MX53_LOCO
Include support for MX53 LOCO platform. This includes specific
configurations for the board and its peripherals.
config MACH_MX50_RDP
bool "Support MX50 reference design platform"
depends on BROKEN
select SOC_IMX50
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select IMX_HAVE_PLATFORM_SPI_IMX
select IMX_HAVE_PLATFORM_FEC
help
Include support for MX50 reference design platform (RDP) board. This
includes specific configurations for the board and its peripherals.
endif # ARCH_MX53_SUPPORTED
endif

2
arch/arm/mach-mx5/board-cpuimx51.c
View File

@ -23,13 +23,11 @@
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/fsl_devices.h>
#include <mach/eukrea-baseboards.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx51.h>
#include <mach/mxc_ehci.h>
#include <asm/irq.h>
#include <asm/setup.h>

2
arch/arm/mach-mx5/board-cpuimx51sd.c
View File

@ -23,7 +23,6 @@
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/fsl_devices.h>
#include <linux/i2c-gpio.h>
#include <linux/spi/spi.h>
#include <linux/can/platform/mcp251x.h>
@ -32,7 +31,6 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx51.h>
#include <mach/mxc_ehci.h>
#include <asm/irq.h>
#include <asm/setup.h>

1
arch/arm/mach-mx5/board-mx50_rdp.c
View File

@ -23,7 +23,6 @@
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/fsl_devices.h>
#include <mach/common.h>
#include <mach/hardware.h>

18
arch/arm/mach-mx5/board-mx51_babbage.c
View File

@ -16,9 +16,6 @@
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/fsl_devices.h>
#include <linux/fec.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/spi/flash.h>
#include <linux/spi/spi.h>
@ -26,7 +23,6 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx51.h>
#include <mach/mxc_ehci.h>
#include <asm/irq.h>
#include <asm/setup.h>
@ -208,18 +204,16 @@ static inline void babbage_usbhub_reset(void)
{
int ret;
/* Bring USB hub out of reset */
ret = gpio_request(BABBAGE_USB_HUB_RESET, "GPIO1_7");
/* Reset USB hub */
ret = gpio_request_one(BABBAGE_USB_HUB_RESET,
GPIOF_OUT_INIT_LOW, "GPIO1_7");
if (ret) {
printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret);
return;
}
gpio_direction_output(BABBAGE_USB_HUB_RESET, 0);
/* USB HUB RESET - De-assert USB HUB RESET_N */
msleep(1);
gpio_set_value(BABBAGE_USB_HUB_RESET, 0);
msleep(1);
msleep(2);
/* Deassert reset */
gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
}
@ -361,7 +355,7 @@ static void __init mx51_babbage_init(void)
/* Set the PAD settings for the pwr key. */
mxc_iomux_v3_setup_pad(power_key);
imx51_add_gpio_keys(&imx_button_data);
imx_add_gpio_keys(&imx_button_data);
imx51_add_imx_i2c(0, &babbage_i2c_data);
imx51_add_imx_i2c(1, &babbage_i2c_data);

5
arch/arm/mach-mx5/board-mx51_efikamx.c
View File

@ -22,7 +22,6 @@
#include <linux/input.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/fsl_devices.h>
#include <linux/spi/flash.h>
#include <linux/spi/spi.h>
#include <linux/mfd/mc13892.h>
@ -32,8 +31,6 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx51.h>
#include <mach/i2c.h>
#include <mach/mxc_ehci.h>
#include <asm/irq.h>
#include <asm/setup.h>
@ -252,7 +249,7 @@ static void __init mx51_efikamx_init(void)
}
platform_device_register(&mx51_efikamx_leds_device);
imx51_add_gpio_keys(&mx51_efikamx_powerkey_data);
imx_add_gpio_keys(&mx51_efikamx_powerkey_data);
if (system_rev == 0x11) {
gpio_request(EFIKAMX_RESET1_1, "reset");

5
arch/arm/mach-mx5/board-mx51_efikasb.c
View File

@ -22,7 +22,6 @@
#include <linux/input.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/fsl_devices.h>
#include <linux/spi/flash.h>
#include <linux/spi/spi.h>
#include <linux/mfd/mc13892.h>
@ -35,8 +34,6 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx51.h>
#include <mach/i2c.h>
#include <mach/mxc_ehci.h>
#include <asm/irq.h>
#include <asm/setup.h>
@ -260,7 +257,7 @@ static void __init efikasb_board_init(void)
imx51_add_sdhci_esdhc_imx(1, NULL);
platform_device_register(&mx51_efikasb_leds_device);
imx51_add_gpio_keys(&mx51_efikasb_keys_data);
imx_add_gpio_keys(&mx51_efikasb_keys_data);
}

2
arch/arm/mach-mx5/board-mx53_evk.c
View File

@ -21,7 +21,6 @@
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/fec.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/spi/flash.h>
@ -31,7 +30,6 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx53.h>
#define MX53_EVK_FEC_PHY_RST IMX_GPIO_NR(7, 6)

2
arch/arm/mach-mx5/board-mx53_loco.c
View File

@ -20,13 +20,11 @@
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/fec.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx53.h>
#include <asm/mach-types.h>

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