ath9k_hw: fix ASPM setting for AR9003
The AR_WA register should not be read when in sleep state so add a variable we can stash its value into for when we need to set it. Additionally the AR_WA_D3_TO_L1_DISABLE_REAL (bit 16) needs to be removed. Cc: Aeolus Yang <aeolus.yang@atheros.com> Cc: Madhan Jaganathan <madhan.jaganathan@atheros.com> signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -295,6 +295,8 @@ static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
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/* Several PCIe massages to ensure proper behaviour */
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if (ah->config.pcie_waen)
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REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
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else
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REG_WRITE(ah, AR_WA, ah->WARegVal);
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}
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}
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@ -575,14 +575,8 @@ static int __ath9k_hw_init(struct ath_hw *ah)
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* This enables PCIe low power mode.
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*/
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if (AR_SREV_9300_20_OR_LATER(ah)) {
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u32 regval;
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unsigned int i;
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/* Set Bits 16 and 17 in the AR_WA register. */
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regval = REG_READ(ah, AR_WA);
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regval |= 0x00030000;
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REG_WRITE(ah, AR_WA, regval);
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for (i = 0; i < ah->iniPcieSerdesLowPower.ia_rows; i++) {
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REG_WRITE(ah,
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INI_RA(&ah->iniPcieSerdesLowPower, i, 0),
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@ -590,6 +584,15 @@ static int __ath9k_hw_init(struct ath_hw *ah)
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}
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}
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/*
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* Read back AR_WA into a permanent copy and set bits 14 and 17.
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* We need to do this to avoid RMW of this register. We cannot
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* read the reg when chip is asleep.
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*/
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ah->WARegVal = REG_READ(ah, AR_WA);
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ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
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AR_WA_ASPM_TIMER_BASED_DISABLE);
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if (ah->is_pciexpress)
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ath9k_hw_configpcipowersave(ah, 0, 0);
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else
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@ -1009,6 +1012,11 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
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ENABLE_REGWRITE_BUFFER(ah);
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if (AR_SREV_9300_20_OR_LATER(ah)) {
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REG_WRITE(ah, AR_WA, ah->WARegVal);
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udelay(10);
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}
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REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
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AR_RTC_FORCE_WAKE_ON_INT);
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@ -1063,6 +1071,11 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
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{
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ENABLE_REGWRITE_BUFFER(ah);
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if (AR_SREV_9300_20_OR_LATER(ah)) {
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REG_WRITE(ah, AR_WA, ah->WARegVal);
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udelay(10);
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}
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REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
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AR_RTC_FORCE_WAKE_ON_INT);
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@ -1099,6 +1112,11 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
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static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
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{
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if (AR_SREV_9300_20_OR_LATER(ah)) {
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REG_WRITE(ah, AR_WA, ah->WARegVal);
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udelay(10);
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}
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REG_WRITE(ah, AR_RTC_FORCE_WAKE,
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AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
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@ -1768,6 +1786,11 @@ static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
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REG_CLR_BIT(ah, (AR_RTC_RESET),
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AR_RTC_RESET_EN);
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}
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/* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
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if (AR_SREV_9300_20_OR_LATER(ah))
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REG_WRITE(ah, AR_WA,
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ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
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}
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/*
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@ -1794,6 +1817,10 @@ static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
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AR_RTC_FORCE_WAKE_EN);
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}
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}
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/* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
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if (AR_SREV_9300_20_OR_LATER(ah))
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REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
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}
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static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
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@ -1801,6 +1828,12 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
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u32 val;
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int i;
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/* Set Bits 14 and 17 of AR_WA before powering on the chip. */
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if (AR_SREV_9300_20_OR_LATER(ah)) {
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REG_WRITE(ah, AR_WA, ah->WARegVal);
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udelay(10);
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}
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if (setChip) {
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if ((REG_READ(ah, AR_RTC_STATUS) &
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AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
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@ -819,6 +819,12 @@ struct ath_hw {
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u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
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u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
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/*
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* Store the permanent value of Reg 0x4004in WARegVal
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* so we dont have to R/M/W. We should not be reading
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* this register when in sleep states.
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*/
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u32 WARegVal;
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};
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static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
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@ -704,6 +704,11 @@
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#define AR_WA_BIT7 (1 << 7)
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#define AR_WA_BIT23 (1 << 23)
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#define AR_WA_D3_L1_DISABLE (1 << 14)
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#define AR_WA_D3_TO_L1_DISABLE_REAL (1 << 16)
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#define AR_WA_ASPM_TIMER_BASED_DISABLE (1 << 17)
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#define AR_WA_RESET_EN (1 << 18) /* Sw Control to enable PCI-Reset to POR (bit 15) */
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#define AR_WA_ANALOG_SHIFT (1 << 20)
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#define AR_WA_POR_SHORT (1 << 21) /* PCI-E Phy reset control */
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#define AR9285_WA_DEFAULT 0x004a050b
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#define AR9280_WA_DEFAULT 0x0040073b
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#define AR_WA_DEFAULT 0x0000073f
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