ARM: pgtable: document mapping types
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -129,7 +129,36 @@
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/*
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* These are the memory types, defined to be compatible with
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* pre-ARMv6 CPUs cacheable and bufferable bits: XXCB
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* pre-ARMv6 CPUs cacheable and bufferable bits: n/a,n/a,C,B
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* ARMv6+ without TEX remapping, they are a table index.
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* ARMv6+ with TEX remapping, they correspond to n/a,TEX(0),C,B
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*
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* MT type Pre-ARMv6 ARMv6+ type / cacheable status
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* UNCACHED Uncached Strongly ordered
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* BUFFERABLE Bufferable Normal memory / non-cacheable
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* WRITETHROUGH Writethrough Normal memory / write through
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* WRITEBACK Writeback Normal memory / write back, read alloc
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* MINICACHE Minicache N/A
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* WRITEALLOC Writeback Normal memory / write back, write alloc
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* DEV_SHARED Uncached Device memory (shared)
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* DEV_NONSHARED Uncached Device memory (non-shared)
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* DEV_WC Bufferable Normal memory / non-cacheable
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* DEV_CACHED Writeback Normal memory / write back, read alloc
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* VECTORS Variable Normal memory / variable
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*
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* All normal memory mappings have the following properties:
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* - reads can be repeated with no side effects
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* - repeated reads return the last value written
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* - reads can fetch additional locations without side effects
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* - writes can be repeated (in certain cases) with no side effects
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* - writes can be merged before accessing the target
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* - unaligned accesses can be supported
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*
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* All device mappings have the following properties:
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* - no access speculation
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* - no repetition (eg, on return from an exception)
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* - number, order and size of accesses are maintained
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* - unaligned accesses are "unpredictable"
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*/
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#define L_PTE_MT_UNCACHED (_AT(pteval_t, 0x00) << 2) /* 0000 */
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#define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 0x01) << 2) /* 0001 */
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