Merge branch 'for-rmk' of git://git.pengutronix.de/git/imx/linux-2.6 into devel-stable
This commit is contained in:
commit
9ae21ca362
|
@ -1669,6 +1669,12 @@ if ARCH_HAS_CPUFREQ
|
|||
|
||||
source "drivers/cpufreq/Kconfig"
|
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|
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config CPU_FREQ_IMX
|
||||
tristate "CPUfreq driver for i.MX CPUs"
|
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depends on ARCH_MXC && CPU_FREQ
|
||||
help
|
||||
This enables the CPUfreq driver for i.MX CPUs.
|
||||
|
||||
config CPU_FREQ_SA1100
|
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bool
|
||||
|
||||
|
|
|
@ -82,6 +82,7 @@ CONFIG_FEC=y
|
|||
CONFIG_INPUT_FF_MEMLESS=m
|
||||
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
CONFIG_KEYBOARD_GPIO=y
|
||||
CONFIG_INPUT_EVBUG=m
|
||||
CONFIG_MOUSE_PS2=m
|
||||
CONFIG_MOUSE_PS2_ELANTECH=y
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||||
|
|
|
@ -23,16 +23,20 @@
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|||
#include <linux/platform_device.h>
|
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#include <linux/gpio.h>
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#include <linux/input/matrix_keypad.h>
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#include <linux/irq.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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#include <mach/hardware.h>
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#include <mach/common.h>
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#include <mach/iomux-mx27.h>
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#include <mach/mmc.h>
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#include "devices-imx27.h"
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#include "devices.h"
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#define SD1_EN_GPIO (GPIO_PORTB + 25)
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|
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static const int mx27pdk_pins[] __initconst = {
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/* UART1 */
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PE12_PF_UART1_TXD,
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|
@ -58,6 +62,14 @@ static const int mx27pdk_pins[] __initconst = {
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|||
PD15_AOUT_FEC_COL,
|
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PD16_AIN_FEC_TX_ER,
|
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PF23_AIN_FEC_TX_EN,
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/* SDHC1 */
|
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PE18_PF_SD1_D0,
|
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PE19_PF_SD1_D1,
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PE20_PF_SD1_D2,
|
||||
PE21_PF_SD1_D3,
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PE22_PF_SD1_CMD,
|
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PE23_PF_SD1_CLK,
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SD1_EN_GPIO | GPIO_GPIO | GPIO_OUT,
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||||
};
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static const struct imxuart_platform_data uart_pdata __initconst = {
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||||
|
@ -85,13 +97,39 @@ static struct matrix_keymap_data mx27_3ds_keymap_data = {
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.keymap_size = ARRAY_SIZE(mx27_3ds_keymap),
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};
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static int mx27_3ds_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
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void *data)
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{
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return request_irq(IRQ_GPIOB(26), detect_irq, IRQF_TRIGGER_FALLING |
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IRQF_TRIGGER_RISING, "sdhc1-card-detect", data);
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}
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|
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static void mx27_3ds_sdhc1_exit(struct device *dev, void *data)
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{
|
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free_irq(IRQ_GPIOB(26), data);
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}
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|
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static struct imxmmc_platform_data sdhc1_pdata = {
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.init = mx27_3ds_sdhc1_init,
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.exit = mx27_3ds_sdhc1_exit,
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};
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static void mx27_3ds_sdhc1_enable_level_translator(void)
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{
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/* Turn on TXB0108 OE pin */
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gpio_request(SD1_EN_GPIO, "sd1_enable");
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gpio_direction_output(SD1_EN_GPIO, 1);
|
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}
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|
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static void __init mx27pdk_init(void)
|
||||
{
|
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mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
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"mx27pdk");
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mx27_3ds_sdhc1_enable_level_translator();
|
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imx27_add_imx_uart0(&uart_pdata);
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imx27_add_fec(NULL);
|
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mxc_register_device(&imx_kpp_device, &mx27_3ds_keymap_data);
|
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mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
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}
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static void __init mx27pdk_timer_init(void)
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|
|
|
@ -6,6 +6,7 @@ config MACH_MX25_3DS
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bool "Support MX25PDK (3DS) Platform"
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select IMX_HAVE_PLATFORM_IMX_UART
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select IMX_HAVE_PLATFORM_MXC_NAND
|
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select IMX_HAVE_PLATFORM_ESDHC
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config MACH_EUKREA_CPUIMX25
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bool "Support Eukrea CPUIMX25 Platform"
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|
|
|
@ -96,6 +96,14 @@ static struct pad_desc mx25pdk_pads[] = {
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MX25_PAD_KPP_COL1__KPP_COL1,
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MX25_PAD_KPP_COL2__KPP_COL2,
|
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MX25_PAD_KPP_COL3__KPP_COL3,
|
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|
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/* SD1 */
|
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MX25_PAD_SD1_CMD__SD1_CMD,
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MX25_PAD_SD1_CLK__SD1_CLK,
|
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MX25_PAD_SD1_DATA0__SD1_DATA0,
|
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MX25_PAD_SD1_DATA1__SD1_DATA1,
|
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MX25_PAD_SD1_DATA2__SD1_DATA2,
|
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MX25_PAD_SD1_DATA3__SD1_DATA3,
|
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};
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||||
static const struct fec_platform_data mx25_fec_pdata __initconst = {
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|
@ -193,6 +201,8 @@ static void __init mx25pdk_init(void)
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mx25pdk_fec_reset();
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imx25_add_fec(&mx25_fec_pdata);
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||||
mxc_register_device(&mx25_kpp_device, &mx25pdk_keymap_data);
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||||
|
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imx25_add_esdhc(0, NULL);
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||||
}
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static void __init mx25pdk_timer_init(void)
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|
|
|
@ -143,8 +143,10 @@ config MACH_ARMADILLO5X0
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config MACH_MX35_3DS
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bool "Support MX35PDK platform"
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||||
select ARCH_MX35
|
||||
select MXC_DEBUG_BOARD
|
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select IMX_HAVE_PLATFORM_IMX_UART
|
||||
select IMX_HAVE_PLATFORM_MXC_NAND
|
||||
select IMX_HAVE_PLATFORM_ESDHC
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default n
|
||||
help
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Include support for MX35PDK platform. This includes specific
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|
|
|
@ -72,24 +72,24 @@ struct platform_device mxc_w1_master_device = {
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|||
#ifdef CONFIG_ARCH_MX31
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static struct resource mxcsdhc0_resources[] = {
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||||
{
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||||
.start = MMC_SDHC1_BASE_ADDR,
|
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.end = MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
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.start = MX31_MMC_SDHC1_BASE_ADDR,
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.end = MX31_MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_MMC_SDHC1,
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.end = MXC_INT_MMC_SDHC1,
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.start = MX31_INT_MMC_SDHC1,
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.end = MX31_INT_MMC_SDHC1,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource mxcsdhc1_resources[] = {
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{
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.start = MMC_SDHC2_BASE_ADDR,
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.end = MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
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||||
.start = MX31_MMC_SDHC2_BASE_ADDR,
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.end = MX31_MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_MMC_SDHC2,
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.end = MXC_INT_MMC_SDHC2,
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.start = MX31_INT_MMC_SDHC2,
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.end = MX31_INT_MMC_SDHC2,
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.flags = IORESOURCE_IRQ,
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},
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};
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|
|
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@ -38,39 +38,9 @@
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#include "devices-imx31.h"
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#include "devices.h"
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|
||||
/* Definitions for components on the Debug board */
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|
||||
/* Base address of CPLD controller on the Debug board */
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#define DEBUG_BASE_ADDRESS CS5_IO_ADDRESS(MX3x_CS5_BASE_ADDR)
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/* LAN9217 ethernet base address */
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#define LAN9217_BASE_ADDR MX3x_CS5_BASE_ADDR
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/* CPLD config and interrupt base address */
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#define CPLD_ADDR (DEBUG_BASE_ADDRESS + 0x20000)
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/* status, interrupt */
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#define CPLD_INT_STATUS_REG (CPLD_ADDR + 0x10)
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#define CPLD_INT_MASK_REG (CPLD_ADDR + 0x38)
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#define CPLD_INT_RESET_REG (CPLD_ADDR + 0x20)
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/* magic word for debug CPLD */
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#define CPLD_MAGIC_NUMBER1_REG (CPLD_ADDR + 0x40)
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#define CPLD_MAGIC_NUMBER2_REG (CPLD_ADDR + 0x48)
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/* CPLD code version */
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#define CPLD_CODE_VER_REG (CPLD_ADDR + 0x50)
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/* magic word for debug CPLD */
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#define CPLD_MAGIC_NUMBER3_REG (CPLD_ADDR + 0x58)
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/* CPLD IRQ line for external uart, external ethernet etc */
|
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#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
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#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
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#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
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#define EXPIO_INT_ENET (MXC_EXP_IO_BASE + 0)
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#define MXC_MAX_EXP_IO_LINES 16
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/*
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* This file contains the board-specific initialization routines.
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*/
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|
@ -272,7 +242,7 @@ static void __init mxc_board_init(void)
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imx31_add_imx_uart0(&uart_pdata);
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imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
|
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|
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imx31_add_spi_imx0(&spi1_pdata);
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imx31_add_spi_imx1(&spi1_pdata);
|
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spi_register_board_info(mx31_3ds_spi_devs,
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ARRAY_SIZE(mx31_3ds_spi_devs));
|
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|
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|
@ -281,9 +251,9 @@ static void __init mxc_board_init(void)
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mx31_3ds_usbotg_init();
|
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mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata);
|
||||
|
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if (!mxc_expio_init(CS5_BASE_ADDR, EXPIO_PARENT_INT))
|
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if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT))
|
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printk(KERN_WARNING "Init of the debug board failed, all "
|
||||
"devices on the board are unusable.\n");
|
||||
"devices on the debug board are unusable.\n");
|
||||
}
|
||||
|
||||
static void __init mx31_3ds_timer_init(void)
|
||||
|
|
|
@ -38,11 +38,15 @@
|
|||
#include <mach/hardware.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/iomux-mx35.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/3ds_debugboard.h>
|
||||
#include <mach/mxc_ehci.h>
|
||||
|
||||
#include "devices-imx35.h"
|
||||
#include "devices.h"
|
||||
|
||||
#define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 1)
|
||||
|
||||
static const struct imxuart_platform_data uart_pdata __initconst = {
|
||||
.flags = IMXUART_HAVE_RTSCTS,
|
||||
};
|
||||
|
@ -108,6 +112,13 @@ static struct pad_desc mx35pdk_pads[] = {
|
|||
/* USBH1 */
|
||||
MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
|
||||
MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
|
||||
/* SDCARD */
|
||||
MX35_PAD_SD1_CMD__ESDHC1_CMD,
|
||||
MX35_PAD_SD1_CLK__ESDHC1_CLK,
|
||||
MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
|
||||
MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
|
||||
MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
|
||||
MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
|
||||
};
|
||||
|
||||
/* OTG config */
|
||||
|
@ -140,6 +151,11 @@ static void __init mxc_board_init(void)
|
|||
mxc_register_device(&mxc_usbh1, &usb_host_pdata);
|
||||
|
||||
imx35_add_mxc_nand(&mx35pdk_nand_board_info);
|
||||
imx35_add_esdhc(0, NULL);
|
||||
|
||||
if (mxc_expio_init(MX35_CS5_BASE_ADDR, EXPIO_PARENT_INT))
|
||||
pr_warn("Init of the debugboard failed, all "
|
||||
"devices on the debugboard are unusable.\n");
|
||||
}
|
||||
|
||||
static void __init mx35pdk_timer_init(void)
|
||||
|
|
|
@ -6,6 +6,7 @@ config ARCH_MX51
|
|||
select MXC_TZIC
|
||||
select ARCH_MXC_IOMUX_V3
|
||||
select ARCH_MXC_AUDMUX_V2
|
||||
select ARCH_HAS_CPUFREQ
|
||||
|
||||
comment "MX5 platforms:"
|
||||
|
||||
|
@ -13,6 +14,7 @@ config MACH_MX51_BABBAGE
|
|||
bool "Support MX51 BABBAGE platforms"
|
||||
select IMX_HAVE_PLATFORM_IMX_I2C
|
||||
select IMX_HAVE_PLATFORM_IMX_UART
|
||||
select IMX_HAVE_PLATFORM_ESDHC
|
||||
help
|
||||
Include support for MX51 Babbage platform, also known as MX51EVK in
|
||||
u-boot. This includes specific configurations for the board and its
|
||||
|
|
|
@ -5,6 +5,7 @@
|
|||
# Object file lists.
|
||||
obj-y := cpu.o mm.o clock-mx51.o devices.o
|
||||
|
||||
obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o
|
||||
obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
|
||||
obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
|
||||
obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
|
@ -18,6 +18,8 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/fsl_devices.h>
|
||||
#include <linux/fec.h>
|
||||
#include <linux/gpio_keys.h>
|
||||
#include <linux/input.h>
|
||||
|
||||
#include <mach/common.h>
|
||||
#include <mach/hardware.h>
|
||||
|
@ -32,11 +34,13 @@
|
|||
|
||||
#include "devices-imx51.h"
|
||||
#include "devices.h"
|
||||
#include "cpu_op-mx51.h"
|
||||
|
||||
#define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */
|
||||
#define BABBAGE_USBH1_STP (0*32 + 27) /* GPIO_1_27 */
|
||||
#define BABBAGE_PHY_RESET (1*32 + 5) /* GPIO_2_5 */
|
||||
#define BABBAGE_FEC_PHY_RESET (1*32 + 14) /* GPIO_2_14 */
|
||||
#define BABBAGE_POWER_KEY (1*32 + 21) /* GPIO_2_21 */
|
||||
|
||||
/* USB_CTRL_1 */
|
||||
#define MX51_USB_CTRL_1_OFFSET 0x10
|
||||
|
@ -46,6 +50,21 @@
|
|||
#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
|
||||
#define MX51_USB_PLL_DIV_24_MHZ 0x02
|
||||
|
||||
static struct gpio_keys_button babbage_buttons[] = {
|
||||
{
|
||||
.gpio = BABBAGE_POWER_KEY,
|
||||
.code = BTN_0,
|
||||
.desc = "PWR",
|
||||
.active_low = 1,
|
||||
.wakeup = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct gpio_keys_platform_data imx_button_data __initconst = {
|
||||
.buttons = babbage_buttons,
|
||||
.nbuttons = ARRAY_SIZE(babbage_buttons),
|
||||
};
|
||||
|
||||
static struct pad_desc mx51babbage_pads[] = {
|
||||
/* UART1 */
|
||||
MX51_PAD_UART1_RXD__UART1_RXD,
|
||||
|
@ -112,6 +131,22 @@ static struct pad_desc mx51babbage_pads[] = {
|
|||
|
||||
/* FEC PHY reset line */
|
||||
MX51_PAD_EIM_A20__GPIO_2_14,
|
||||
|
||||
/* SD 1 */
|
||||
MX51_PAD_SD1_CMD__SD1_CMD,
|
||||
MX51_PAD_SD1_CLK__SD1_CLK,
|
||||
MX51_PAD_SD1_DATA0__SD1_DATA0,
|
||||
MX51_PAD_SD1_DATA1__SD1_DATA1,
|
||||
MX51_PAD_SD1_DATA2__SD1_DATA2,
|
||||
MX51_PAD_SD1_DATA3__SD1_DATA3,
|
||||
|
||||
/* SD 2 */
|
||||
MX51_PAD_SD2_CMD__SD2_CMD,
|
||||
MX51_PAD_SD2_CLK__SD2_CLK,
|
||||
MX51_PAD_SD2_DATA0__SD2_DATA0,
|
||||
MX51_PAD_SD2_DATA1__SD2_DATA1,
|
||||
MX51_PAD_SD2_DATA2__SD2_DATA2,
|
||||
MX51_PAD_SD2_DATA3__SD2_DATA3,
|
||||
};
|
||||
|
||||
/* Serial ports */
|
||||
|
@ -281,13 +316,22 @@ __setup("otg_mode=", babbage_otg_mode);
|
|||
static void __init mxc_board_init(void)
|
||||
{
|
||||
struct pad_desc usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
|
||||
struct pad_desc power_key = MX51_PAD_EIM_A27__GPIO_2_21;
|
||||
|
||||
#if defined(CONFIG_CPU_FREQ_IMX)
|
||||
get_cpu_op = mx51_get_cpu_op;
|
||||
#endif
|
||||
mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
|
||||
ARRAY_SIZE(mx51babbage_pads));
|
||||
mxc_init_imx_uart();
|
||||
babbage_fec_reset();
|
||||
imx51_add_fec(NULL);
|
||||
|
||||
/* Set the PAD settings for the pwr key. */
|
||||
power_key.pad_ctrl = MX51_GPIO_PAD_CTRL_2;
|
||||
mxc_iomux_v3_setup_pad(&power_key);
|
||||
imx51_add_gpio_keys(&imx_button_data);
|
||||
|
||||
imx51_add_imx_i2c(0, &babbage_i2c_data);
|
||||
imx51_add_imx_i2c(1, &babbage_i2c_data);
|
||||
mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data);
|
||||
|
@ -304,6 +348,9 @@ static void __init mxc_board_init(void)
|
|||
/* setback USBH1_STP to be function */
|
||||
mxc_iomux_v3_setup_pad(&usbh1stp);
|
||||
babbage_usbhub_reset();
|
||||
|
||||
imx51_add_esdhc(0, NULL);
|
||||
imx51_add_esdhc(1, NULL);
|
||||
}
|
||||
|
||||
static void __init mx51_babbage_timer_init(void)
|
||||
|
|
|
@ -362,7 +362,7 @@ static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static unsigned long clk_arm_get_rate(struct clk *clk)
|
||||
static unsigned long clk_cpu_get_rate(struct clk *clk)
|
||||
{
|
||||
u32 cacrr, div;
|
||||
unsigned long parent_rate;
|
||||
|
@ -374,6 +374,22 @@ static unsigned long clk_arm_get_rate(struct clk *clk)
|
|||
return parent_rate / div;
|
||||
}
|
||||
|
||||
static int clk_cpu_set_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
u32 reg, cpu_podf;
|
||||
unsigned long parent_rate;
|
||||
|
||||
parent_rate = clk_get_rate(clk->parent);
|
||||
cpu_podf = parent_rate / rate - 1;
|
||||
/* use post divider to change freq */
|
||||
reg = __raw_readl(MXC_CCM_CACRR);
|
||||
reg &= ~MXC_CCM_CACRR_ARM_PODF_MASK;
|
||||
reg |= cpu_podf << MXC_CCM_CACRR_ARM_PODF_OFFSET;
|
||||
__raw_writel(reg, MXC_CCM_CACRR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent)
|
||||
{
|
||||
u32 reg, mux;
|
||||
|
@ -736,7 +752,8 @@ static struct clk periph_apm_clk = {
|
|||
|
||||
static struct clk cpu_clk = {
|
||||
.parent = &pll1_sw_clk,
|
||||
.get_rate = clk_arm_get_rate,
|
||||
.get_rate = clk_cpu_get_rate,
|
||||
.set_rate = clk_cpu_set_rate,
|
||||
};
|
||||
|
||||
static struct clk ahb_clk = {
|
||||
|
@ -1064,6 +1081,7 @@ static struct clk_lookup lookups[] = {
|
|||
_REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk)
|
||||
_REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
|
||||
_REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
|
||||
_REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk)
|
||||
};
|
||||
|
||||
static void clk_tree_init(void)
|
||||
|
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
static struct cpu_op mx51_cpu_op[] = {
|
||||
{
|
||||
.cpu_rate = 160000000,},
|
||||
{
|
||||
.cpu_rate = 800000000,},
|
||||
};
|
||||
|
||||
struct cpu_op *mx51_get_cpu_op(int *op)
|
||||
{
|
||||
*op = ARRAY_SIZE(mx51_cpu_op);
|
||||
return mx51_cpu_op;
|
||||
}
|
|
@ -0,0 +1,14 @@
|
|||
/*
|
||||
* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
extern struct cpu_op *mx51_get_cpu_op(int *op);
|
|
@ -13,6 +13,8 @@ extern const struct imx_fec_data imx51_fec_data __initconst;
|
|||
#define imx51_add_fec(pdata) \
|
||||
imx_add_fec(&imx51_fec_data, pdata)
|
||||
|
||||
#define imx51_add_gpio_keys(pdata) imx_add_gpio_keys(pdata)
|
||||
|
||||
extern const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst;
|
||||
#define imx51_add_imx_i2c(id, pdata) \
|
||||
imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata)
|
||||
|
|
|
@ -18,6 +18,7 @@ obj-$(CONFIG_MXC_USE_EPIT) += epit.o
|
|||
obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
|
||||
obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o
|
||||
obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
|
||||
obj-$(CONFIG_CPU_FREQ_IMX) += cpufreq.o
|
||||
ifdef CONFIG_SND_IMX_SOC
|
||||
obj-y += ssi-fiq.o
|
||||
obj-y += ssi-fiq-ksym.o
|
||||
|
|
|
@ -0,0 +1,206 @@
|
|||
/*
|
||||
* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/*
|
||||
* A driver for the Freescale Semiconductor i.MXC CPUfreq module.
|
||||
* The CPUFREQ driver is for controling CPU frequency. It allows you to change
|
||||
* the CPU clock speed on the fly.
|
||||
*/
|
||||
|
||||
#include <linux/cpufreq.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/slab.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/clock.h>
|
||||
|
||||
#define CLK32_FREQ 32768
|
||||
#define NANOSECOND (1000 * 1000 * 1000)
|
||||
|
||||
struct cpu_op *(*get_cpu_op)(int *op);
|
||||
|
||||
static int cpu_freq_khz_min;
|
||||
static int cpu_freq_khz_max;
|
||||
|
||||
static struct clk *cpu_clk;
|
||||
static struct cpufreq_frequency_table *imx_freq_table;
|
||||
|
||||
static int cpu_op_nr;
|
||||
static struct cpu_op *cpu_op_tbl;
|
||||
|
||||
static int set_cpu_freq(int freq)
|
||||
{
|
||||
int ret = 0;
|
||||
int org_cpu_rate;
|
||||
|
||||
org_cpu_rate = clk_get_rate(cpu_clk);
|
||||
if (org_cpu_rate == freq)
|
||||
return ret;
|
||||
|
||||
ret = clk_set_rate(cpu_clk, freq);
|
||||
if (ret != 0) {
|
||||
printk(KERN_DEBUG "cannot set CPU clock rate\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mxc_verify_speed(struct cpufreq_policy *policy)
|
||||
{
|
||||
if (policy->cpu != 0)
|
||||
return -EINVAL;
|
||||
|
||||
return cpufreq_frequency_table_verify(policy, imx_freq_table);
|
||||
}
|
||||
|
||||
static unsigned int mxc_get_speed(unsigned int cpu)
|
||||
{
|
||||
if (cpu)
|
||||
return 0;
|
||||
|
||||
return clk_get_rate(cpu_clk) / 1000;
|
||||
}
|
||||
|
||||
static int mxc_set_target(struct cpufreq_policy *policy,
|
||||
unsigned int target_freq, unsigned int relation)
|
||||
{
|
||||
struct cpufreq_freqs freqs;
|
||||
int freq_Hz;
|
||||
int ret = 0;
|
||||
unsigned int index;
|
||||
|
||||
cpufreq_frequency_table_target(policy, imx_freq_table,
|
||||
target_freq, relation, &index);
|
||||
freq_Hz = imx_freq_table[index].frequency * 1000;
|
||||
|
||||
freqs.old = clk_get_rate(cpu_clk) / 1000;
|
||||
freqs.new = freq_Hz / 1000;
|
||||
freqs.cpu = 0;
|
||||
freqs.flags = 0;
|
||||
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
|
||||
|
||||
ret = set_cpu_freq(freq_Hz);
|
||||
|
||||
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __init mxc_cpufreq_init(struct cpufreq_policy *policy)
|
||||
{
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
printk(KERN_INFO "i.MXC CPU frequency driver\n");
|
||||
|
||||
if (policy->cpu != 0)
|
||||
return -EINVAL;
|
||||
|
||||
if (!get_cpu_op)
|
||||
return -EINVAL;
|
||||
|
||||
cpu_clk = clk_get(NULL, "cpu_clk");
|
||||
if (IS_ERR(cpu_clk)) {
|
||||
printk(KERN_ERR "%s: failed to get cpu clock\n", __func__);
|
||||
return PTR_ERR(cpu_clk);
|
||||
}
|
||||
|
||||
cpu_op_tbl = get_cpu_op(&cpu_op_nr);
|
||||
|
||||
cpu_freq_khz_min = cpu_op_tbl[0].cpu_rate / 1000;
|
||||
cpu_freq_khz_max = cpu_op_tbl[0].cpu_rate / 1000;
|
||||
|
||||
imx_freq_table = kmalloc(
|
||||
sizeof(struct cpufreq_frequency_table) * (cpu_op_nr + 1),
|
||||
GFP_KERNEL);
|
||||
if (!imx_freq_table) {
|
||||
ret = -ENOMEM;
|
||||
goto err1;
|
||||
}
|
||||
|
||||
for (i = 0; i < cpu_op_nr; i++) {
|
||||
imx_freq_table[i].index = i;
|
||||
imx_freq_table[i].frequency = cpu_op_tbl[i].cpu_rate / 1000;
|
||||
|
||||
if ((cpu_op_tbl[i].cpu_rate / 1000) < cpu_freq_khz_min)
|
||||
cpu_freq_khz_min = cpu_op_tbl[i].cpu_rate / 1000;
|
||||
|
||||
if ((cpu_op_tbl[i].cpu_rate / 1000) > cpu_freq_khz_max)
|
||||
cpu_freq_khz_max = cpu_op_tbl[i].cpu_rate / 1000;
|
||||
}
|
||||
|
||||
imx_freq_table[i].index = i;
|
||||
imx_freq_table[i].frequency = CPUFREQ_TABLE_END;
|
||||
|
||||
policy->cur = clk_get_rate(cpu_clk) / 1000;
|
||||
policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
|
||||
policy->min = policy->cpuinfo.min_freq = cpu_freq_khz_min;
|
||||
policy->max = policy->cpuinfo.max_freq = cpu_freq_khz_max;
|
||||
|
||||
/* Manual states, that PLL stabilizes in two CLK32 periods */
|
||||
policy->cpuinfo.transition_latency = 2 * NANOSECOND / CLK32_FREQ;
|
||||
|
||||
ret = cpufreq_frequency_table_cpuinfo(policy, imx_freq_table);
|
||||
|
||||
if (ret < 0) {
|
||||
printk(KERN_ERR "%s: failed to register i.MXC CPUfreq \
|
||||
with error code %d\n", __func__, ret);
|
||||
goto err;
|
||||
}
|
||||
|
||||
cpufreq_frequency_table_get_attr(imx_freq_table, policy->cpu);
|
||||
return 0;
|
||||
err:
|
||||
kfree(imx_freq_table);
|
||||
err1:
|
||||
clk_put(cpu_clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mxc_cpufreq_exit(struct cpufreq_policy *policy)
|
||||
{
|
||||
cpufreq_frequency_table_put_attr(policy->cpu);
|
||||
|
||||
set_cpu_freq(cpu_freq_khz_max * 1000);
|
||||
clk_put(cpu_clk);
|
||||
kfree(imx_freq_table);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct cpufreq_driver mxc_driver = {
|
||||
.flags = CPUFREQ_STICKY,
|
||||
.verify = mxc_verify_speed,
|
||||
.target = mxc_set_target,
|
||||
.get = mxc_get_speed,
|
||||
.init = mxc_cpufreq_init,
|
||||
.exit = mxc_cpufreq_exit,
|
||||
.name = "imx",
|
||||
};
|
||||
|
||||
static int __devinit mxc_cpufreq_driver_init(void)
|
||||
{
|
||||
return cpufreq_register_driver(&mxc_driver);
|
||||
}
|
||||
|
||||
static void mxc_cpufreq_driver_exit(void)
|
||||
{
|
||||
cpufreq_unregister_driver(&mxc_driver);
|
||||
}
|
||||
|
||||
module_init(mxc_cpufreq_driver_init);
|
||||
module_exit(mxc_cpufreq_driver_exit);
|
||||
|
||||
MODULE_AUTHOR("Freescale Semiconductor Inc. Yong Shen <yong.shen@linaro.org>");
|
||||
MODULE_DESCRIPTION("CPUfreq driver for i.MX");
|
||||
MODULE_LICENSE("GPL");
|
|
@ -6,9 +6,13 @@ config IMX_HAVE_PLATFORM_FEC
|
|||
default y if ARCH_MX25 || SOC_IMX27 || ARCH_MX35 || ARCH_MX51
|
||||
|
||||
config IMX_HAVE_PLATFORM_FLEXCAN
|
||||
select HAVE_CAN_FLEXCAN
|
||||
select HAVE_CAN_FLEXCAN if CAN
|
||||
bool
|
||||
|
||||
config IMX_HAVE_PLATFORM_GPIO_KEYS
|
||||
bool
|
||||
default y if ARCH_MX51
|
||||
|
||||
config IMX_HAVE_PLATFORM_IMX_I2C
|
||||
bool
|
||||
|
||||
|
|
|
@ -1,6 +1,7 @@
|
|||
obj-$(CONFIG_IMX_HAVE_PLATFORM_ESDHC) += platform-esdhc.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o
|
||||
obj-y += platform-imx-dma.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o
|
||||
|
|
|
@ -0,0 +1,27 @@
|
|||
/*
|
||||
* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
#include <asm/sizes.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/devices-common.h>
|
||||
|
||||
struct platform_device *__init imx_add_gpio_keys(
|
||||
const struct gpio_keys_platform_data *pdata)
|
||||
{
|
||||
return imx_add_platform_device("gpio-keys", -1, NULL,
|
||||
0, pdata, sizeof(*pdata));
|
||||
}
|
|
@ -20,6 +20,7 @@
|
|||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/gpio.h>
|
||||
|
@ -201,11 +202,42 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
|
|||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Set interrupt number "irq" in the GPIO as a wake-up source.
|
||||
* While system is running, all registered GPIO interrupts need to have
|
||||
* wake-up enabled. When system is suspended, only selected GPIO interrupts
|
||||
* need to have wake-up enabled.
|
||||
* @param irq interrupt source number
|
||||
* @param enable enable as wake-up if equal to non-zero
|
||||
* @return This function returns 0 on success.
|
||||
*/
|
||||
static int gpio_set_wake_irq(u32 irq, u32 enable)
|
||||
{
|
||||
u32 gpio = irq_to_gpio(irq);
|
||||
u32 gpio_idx = gpio & 0x1F;
|
||||
struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32];
|
||||
|
||||
if (enable) {
|
||||
if (port->irq_high && (gpio_idx >= 16))
|
||||
enable_irq_wake(port->irq_high);
|
||||
else
|
||||
enable_irq_wake(port->irq);
|
||||
} else {
|
||||
if (port->irq_high && (gpio_idx >= 16))
|
||||
disable_irq_wake(port->irq_high);
|
||||
else
|
||||
disable_irq_wake(port->irq);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct irq_chip gpio_irq_chip = {
|
||||
.ack = gpio_ack_irq,
|
||||
.mask = gpio_mask_irq,
|
||||
.unmask = gpio_unmask_irq,
|
||||
.set_type = gpio_set_irq_type,
|
||||
.set_wake = gpio_set_wake_irq,
|
||||
};
|
||||
|
||||
static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
|
||||
|
|
|
@ -29,6 +29,10 @@ struct platform_device *__init imx_add_flexcan(int id,
|
|||
resource_size_t irq,
|
||||
const struct flexcan_platform_data *pdata);
|
||||
|
||||
#include <linux/gpio_keys.h>
|
||||
struct platform_device *__init imx_add_gpio_keys(
|
||||
const struct gpio_keys_platform_data *pdata);
|
||||
|
||||
#include <mach/i2c.h>
|
||||
struct imx_imx_i2c_data {
|
||||
int id;
|
||||
|
|
|
@ -45,6 +45,8 @@ typedef enum iomux_config {
|
|||
PAD_CTL_PKE | PAD_CTL_HYS)
|
||||
#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \
|
||||
PAD_CTL_SRE_FAST)
|
||||
#define MX51_GPIO_PAD_CTRL_2 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
|
||||
PAD_CTL_PUS_100K_UP)
|
||||
#define MX51_ECSPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
|
||||
PAD_CTL_SRE_FAST)
|
||||
#define MX51_SDHCI_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP | \
|
||||
|
|
|
@ -240,7 +240,6 @@ static inline void mx31_setup_weimcs(size_t cs,
|
|||
#define MPEG4_ENC_BASE_ADDR MX31_MPEG4_ENC_BASE_ADDR
|
||||
#define MXC_INT_MPEG4_ENCODER MX31_INT_MPEG4_ENCODER
|
||||
#define MXC_INT_FIRI MX31_INT_FIRI
|
||||
#define MXC_INT_MMC_SDHC1 MX31_INT_MMC_SDHC1
|
||||
#define MXC_INT_MBX MX31_INT_MBX
|
||||
#define MXC_INT_CSPI3 MX31_INT_CSPI3
|
||||
#define MXC_INT_SIM2 MX31_INT_SIM2
|
||||
|
|
|
@ -197,8 +197,6 @@
|
|||
/* these should go away */
|
||||
#define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR
|
||||
#define MXC_INT_OWIRE MX35_INT_OWIRE
|
||||
#define MXC_INT_MMC_SDHC2 MX35_INT_MMC_SDHC2
|
||||
#define MXC_INT_MMC_SDHC3 MX35_INT_MMC_SDHC3
|
||||
#define MXC_INT_GPU2D MX35_INT_GPU2D
|
||||
#define MXC_INT_ASRC MX35_INT_ASRC
|
||||
#define MXC_INT_USBHS MX35_INT_USBHS
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2004-2007, 2010 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
|
@ -20,6 +20,8 @@
|
|||
#ifndef __ASM_ARCH_MXC_H__
|
||||
#define __ASM_ARCH_MXC_H__
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
#ifndef __ASM_ARCH_MXC_HARDWARE_H__
|
||||
#error "Do not include directly."
|
||||
#endif
|
||||
|
@ -133,6 +135,15 @@ extern unsigned int __mxc_cpu_type;
|
|||
# define cpu_is_mxc91231() (0)
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
struct cpu_op {
|
||||
u32 cpu_rate;
|
||||
};
|
||||
|
||||
extern struct cpu_op *(*get_cpu_op)(int *op);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2)
|
||||
/* These are deprecated, use mx[23][157]_setup_weimcs instead. */
|
||||
#define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10))
|
||||
|
|
Loading…
Reference in New Issue