Merge branch 'drm-patches' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-patches' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (21 commits) drm: only trust core drm ioctls - driver ioctls are a mess. drm/i915: add support for Intel series 4 chipsets. drm/radeon: add hier-z registers for r300 and r500 chipsets drm/radeon: use DSTCACHE_CTLSTAT rather than RB2D_DSTCACHE_CTLSTAT drm/radeon: switch IGP gart to use radeon_write_agp_base() drm/radeon: Restore sw interrupt on resume drm/r500: add support for AGP based cards. drm/radeon: fix texture uploads with large 3d textures (bug 13980) drm/radeon: add initial r500 support. drm/radeon: init pipe setup in kernel code. drm/radeon: fixup radeon_do_engine_reset drm/radeon: fix pixcache and purge/cache flushing registers drm/radeon: write AGP_BASE_2 on chips that support it. drm/radeon: merge IGP chip setup and fixup RS400 vs RS480 support drm/radeon: IGP clean up register and magic numbers. drm/rs690: set base 2 to 0. drm/rs690: set all of gart base address. radeon: add production microcode from AMD drm: pcigart use proper pci map interfaces. drm: the sg alloc ioctl should write back the handle to userspace ...
This commit is contained in:
Linus Torvalds
commit
9aef85cc58
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@ -76,7 +76,7 @@ int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info
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for (i = 0; i < pages; i++) {
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if (!entry->busaddr[i])
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break;
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pci_unmap_single(dev->pdev, entry->busaddr[i],
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pci_unmap_page(dev->pdev, entry->busaddr[i],
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PAGE_SIZE, PCI_DMA_TODEVICE);
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}
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@ -137,10 +137,8 @@ int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *ga
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for (i = 0; i < pages; i++) {
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/* we need to support large memory configurations */
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entry->busaddr[i] = pci_map_single(dev->pdev,
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page_address(entry->
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pagelist[i]),
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PAGE_SIZE, PCI_DMA_TODEVICE);
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entry->busaddr[i] = pci_map_page(dev->pdev, entry->pagelist[i],
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0, PAGE_SIZE, PCI_DMA_TODEVICE);
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if (entry->busaddr[i] == 0) {
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DRM_ERROR("unable to map PCIGART pages!\n");
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drm_ati_pcigart_cleanup(dev, gart_info);
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@ -628,7 +628,7 @@ struct drm_set_version {
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#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding)
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#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding)
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#define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, struct drm_scatter_gather)
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#define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather)
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#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather)
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#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)
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@ -470,17 +470,18 @@ int drm_ioctl(struct inode *inode, struct file *filp,
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if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) &&
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(nr < DRM_COMMAND_BASE + dev->driver->num_ioctls))
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ioctl = &dev->driver->ioctls[nr - DRM_COMMAND_BASE];
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else if ((nr >= DRM_COMMAND_END) || (nr < DRM_COMMAND_BASE))
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else if ((nr >= DRM_COMMAND_END) || (nr < DRM_COMMAND_BASE)) {
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ioctl = &drm_ioctls[nr];
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else
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cmd = ioctl->cmd;
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} else
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goto err_i1;
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/* Do not trust userspace, use our own definition */
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func = ioctl->func;
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/* is there a local override? */
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if ((nr == DRM_IOCTL_NR(DRM_IOCTL_DMA)) && dev->driver->dma_ioctl)
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func = dev->driver->dma_ioctl;
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if (!func) {
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DRM_DEBUG("no function\n");
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retcode = -EINVAL;
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@ -103,20 +103,18 @@
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{0x1002, 0x5653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP}, \
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{0x1002, 0x5835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \
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{0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
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{0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
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{0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
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{0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
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{0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
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{0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
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{0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
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{0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
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{0x1002, 0x5960, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
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{0x1002, 0x5961, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
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{0x1002, 0x5962, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
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{0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
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{0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
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{0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
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{0x1002, 0x5a41, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
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{0x1002, 0x5a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
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{0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
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{0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
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{0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
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{0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
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{0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
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@ -411,4 +409,7 @@
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{0x8086, 0x2a02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
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{0x8086, 0x2a12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
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{0x8086, 0x2a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
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{0x8086, 0x2e02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
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{0x8086, 0x2e12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
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{0x8086, 0x2e22, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
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{0, 0, 0}
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@ -1112,12 +1112,19 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
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(dev)->pci_device == 0x29A2 || \
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(dev)->pci_device == 0x2A02 || \
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(dev)->pci_device == 0x2A12 || \
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(dev)->pci_device == 0x2A42)
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(dev)->pci_device == 0x2A42 || \
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(dev)->pci_device == 0x2E02 || \
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(dev)->pci_device == 0x2E12 || \
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(dev)->pci_device == 0x2E22)
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#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
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#define IS_IGD_GM(dev) ((dev)->pci_device == 0x2A42)
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#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
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(dev)->pci_device == 0x2E12 || \
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(dev)->pci_device == 0x2E22)
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#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
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(dev)->pci_device == 0x29B2 || \
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(dev)->pci_device == 0x29D2)
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@ -1128,7 +1135,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
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#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
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IS_I945GM(dev) || IS_I965GM(dev) || IS_IGD_GM(dev))
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#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_IGD_GM(dev))
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#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_IGD_GM(dev) || IS_G4X(dev))
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#define PRIMARY_RINGBUFFER_SIZE (128*1024)
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@ -189,18 +189,12 @@ void r300_init_reg_flags(struct drm_device *dev)
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ADD_RANGE(R300_RE_CULL_CNTL, 1);
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ADD_RANGE(0x42C0, 2);
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ADD_RANGE(R300_RS_CNTL_0, 2);
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ADD_RANGE(R300_RS_INTERP_0, 8);
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ADD_RANGE(R300_RS_ROUTE_0, 8);
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ADD_RANGE(0x43A4, 2);
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ADD_RANGE(R300_SC_HYPERZ, 2);
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ADD_RANGE(0x43E8, 1);
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ADD_RANGE(R300_PFS_CNTL_0, 3);
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ADD_RANGE(R300_PFS_NODE_0, 4);
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ADD_RANGE(R300_PFS_TEXI_0, 64);
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ADD_RANGE(0x46A4, 5);
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ADD_RANGE(R300_PFS_INSTR0_0, 64);
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ADD_RANGE(R300_PFS_INSTR1_0, 64);
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ADD_RANGE(R300_PFS_INSTR2_0, 64);
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ADD_RANGE(R300_PFS_INSTR3_0, 64);
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ADD_RANGE(R300_RE_FOG_STATE, 1);
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ADD_RANGE(R300_FOG_COLOR_R, 3);
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ADD_RANGE(R300_PP_ALPHA_TEST, 2);
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|
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@ -215,14 +209,12 @@ void r300_init_reg_flags(struct drm_device *dev)
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ADD_RANGE(0x4E50, 9);
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ADD_RANGE(0x4E88, 1);
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ADD_RANGE(0x4EA0, 2);
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ADD_RANGE(R300_RB3D_ZSTENCIL_CNTL_0, 3);
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ADD_RANGE(R300_RB3D_ZSTENCIL_FORMAT, 4);
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ADD_RANGE_MARK(R300_RB3D_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */
|
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ADD_RANGE(R300_RB3D_DEPTHPITCH, 1);
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ADD_RANGE(0x4F28, 1);
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ADD_RANGE(0x4F30, 2);
|
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ADD_RANGE(0x4F44, 1);
|
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ADD_RANGE(0x4F54, 1);
|
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ADD_RANGE(R300_ZB_CNTL, 3);
|
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ADD_RANGE(R300_ZB_FORMAT, 4);
|
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ADD_RANGE_MARK(R300_ZB_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */
|
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ADD_RANGE(R300_ZB_DEPTHPITCH, 1);
|
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ADD_RANGE(R300_ZB_DEPTHCLEARVALUE, 1);
|
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ADD_RANGE(R300_ZB_ZMASK_OFFSET, 13);
|
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|
||||
ADD_RANGE(R300_TX_FILTER_0, 16);
|
||||
ADD_RANGE(R300_TX_FILTER1_0, 16);
|
||||
|
|
@ -235,13 +227,32 @@ void r300_init_reg_flags(struct drm_device *dev)
|
|||
ADD_RANGE(R300_TX_BORDER_COLOR_0, 16);
|
||||
|
||||
/* Sporadic registers used as primitives are emitted */
|
||||
ADD_RANGE(R300_RB3D_ZCACHE_CTLSTAT, 1);
|
||||
ADD_RANGE(R300_ZB_ZCACHE_CTLSTAT, 1);
|
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ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1);
|
||||
ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8);
|
||||
ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8);
|
||||
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
|
||||
ADD_RANGE(0x4074, 16);
|
||||
ADD_RANGE(R500_VAP_INDEX_OFFSET, 1);
|
||||
ADD_RANGE(R500_US_CONFIG, 2);
|
||||
ADD_RANGE(R500_US_CODE_ADDR, 3);
|
||||
ADD_RANGE(R500_US_FC_CTRL, 1);
|
||||
ADD_RANGE(R500_RS_IP_0, 16);
|
||||
ADD_RANGE(R500_RS_INST_0, 16);
|
||||
ADD_RANGE(R500_RB3D_COLOR_CLEAR_VALUE_AR, 2);
|
||||
ADD_RANGE(R500_RB3D_CONSTANT_COLOR_AR, 2);
|
||||
ADD_RANGE(R500_ZB_FIFO_SIZE, 2);
|
||||
} else {
|
||||
ADD_RANGE(R300_PFS_CNTL_0, 3);
|
||||
ADD_RANGE(R300_PFS_NODE_0, 4);
|
||||
ADD_RANGE(R300_PFS_TEXI_0, 64);
|
||||
ADD_RANGE(R300_PFS_INSTR0_0, 64);
|
||||
ADD_RANGE(R300_PFS_INSTR1_0, 64);
|
||||
ADD_RANGE(R300_PFS_INSTR2_0, 64);
|
||||
ADD_RANGE(R300_PFS_INSTR3_0, 64);
|
||||
ADD_RANGE(R300_RS_INTERP_0, 8);
|
||||
ADD_RANGE(R300_RS_ROUTE_0, 8);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -707,8 +718,9 @@ static __inline__ void r300_pacify(drm_radeon_private_t *dev_priv)
|
|||
BEGIN_RING(6);
|
||||
OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
|
||||
OUT_RING(R300_RB3D_DSTCACHE_UNKNOWN_0A);
|
||||
OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
|
||||
OUT_RING(R300_RB3D_ZCACHE_UNKNOWN_03);
|
||||
OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0));
|
||||
OUT_RING(R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE|
|
||||
R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
|
||||
OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0));
|
||||
OUT_RING(0x0);
|
||||
ADVANCE_RING();
|
||||
|
|
@ -828,6 +840,54 @@ static int r300_scratch(drm_radeon_private_t *dev_priv,
|
|||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Uploads user-supplied vertex program instructions or parameters onto
|
||||
* the graphics card.
|
||||
* Called by r300_do_cp_cmdbuf.
|
||||
*/
|
||||
static inline int r300_emit_r500fp(drm_radeon_private_t *dev_priv,
|
||||
drm_radeon_kcmd_buffer_t *cmdbuf,
|
||||
drm_r300_cmd_header_t header)
|
||||
{
|
||||
int sz;
|
||||
int addr;
|
||||
int type;
|
||||
int clamp;
|
||||
int stride;
|
||||
RING_LOCALS;
|
||||
|
||||
sz = header.r500fp.count;
|
||||
/* address is 9 bits 0 - 8, bit 1 of flags is part of address */
|
||||
addr = ((header.r500fp.adrhi_flags & 1) << 8) | header.r500fp.adrlo;
|
||||
|
||||
type = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
|
||||
clamp = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
|
||||
|
||||
addr |= (type << 16);
|
||||
addr |= (clamp << 17);
|
||||
|
||||
stride = type ? 4 : 6;
|
||||
|
||||
DRM_DEBUG("r500fp %d %d type: %d\n", sz, addr, type);
|
||||
if (!sz)
|
||||
return 0;
|
||||
if (sz * stride * 4 > cmdbuf->bufsz)
|
||||
return -EINVAL;
|
||||
|
||||
BEGIN_RING(3 + sz * stride);
|
||||
OUT_RING_REG(R500_GA_US_VECTOR_INDEX, addr);
|
||||
OUT_RING(CP_PACKET0_TABLE(R500_GA_US_VECTOR_DATA, sz * stride - 1));
|
||||
OUT_RING_TABLE((int *)cmdbuf->buf, sz * stride);
|
||||
|
||||
ADVANCE_RING();
|
||||
|
||||
cmdbuf->buf += sz * stride * 4;
|
||||
cmdbuf->bufsz -= sz * stride * 4;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Parses and validates a user-supplied command buffer and emits appropriate
|
||||
* commands on the DMA ring buffer.
|
||||
|
|
@ -963,6 +1023,19 @@ int r300_do_cp_cmdbuf(struct drm_device *dev,
|
|||
}
|
||||
break;
|
||||
|
||||
case R300_CMD_R500FP:
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) {
|
||||
DRM_ERROR("Calling r500 command on r300 card\n");
|
||||
ret = -EINVAL;
|
||||
goto cleanup;
|
||||
}
|
||||
DRM_DEBUG("R300_CMD_R500FP\n");
|
||||
ret = r300_emit_r500fp(dev_priv, cmdbuf, header);
|
||||
if (ret) {
|
||||
DRM_ERROR("r300_emit_r500fp failed\n");
|
||||
goto cleanup;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
DRM_ERROR("bad cmd_type %i at %p\n",
|
||||
header.header.cmd_type,
|
||||
|
|
|
|||
|
|
@ -702,6 +702,27 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|||
# define R300_RS_ROUTE_1_UNKNOWN11 (1 << 11)
|
||||
/* END: Rasterization / Interpolators - many guesses */
|
||||
|
||||
/* Hierarchical Z Enable */
|
||||
#define R300_SC_HYPERZ 0x43a4
|
||||
# define R300_SC_HYPERZ_DISABLE (0 << 0)
|
||||
# define R300_SC_HYPERZ_ENABLE (1 << 0)
|
||||
# define R300_SC_HYPERZ_MIN (0 << 1)
|
||||
# define R300_SC_HYPERZ_MAX (1 << 1)
|
||||
# define R300_SC_HYPERZ_ADJ_256 (0 << 2)
|
||||
# define R300_SC_HYPERZ_ADJ_128 (1 << 2)
|
||||
# define R300_SC_HYPERZ_ADJ_64 (2 << 2)
|
||||
# define R300_SC_HYPERZ_ADJ_32 (3 << 2)
|
||||
# define R300_SC_HYPERZ_ADJ_16 (4 << 2)
|
||||
# define R300_SC_HYPERZ_ADJ_8 (5 << 2)
|
||||
# define R300_SC_HYPERZ_ADJ_4 (6 << 2)
|
||||
# define R300_SC_HYPERZ_ADJ_2 (7 << 2)
|
||||
# define R300_SC_HYPERZ_HZ_Z0MIN_NO (0 << 5)
|
||||
# define R300_SC_HYPERZ_HZ_Z0MIN (1 << 5)
|
||||
# define R300_SC_HYPERZ_HZ_Z0MAX_NO (0 << 6)
|
||||
# define R300_SC_HYPERZ_HZ_Z0MAX (1 << 6)
|
||||
|
||||
#define R300_SC_EDGERULE 0x43a8
|
||||
|
||||
/* BEGIN: Scissors and cliprects */
|
||||
|
||||
/* There are four clipping rectangles. Their corner coordinates are inclusive.
|
||||
|
|
@ -1346,7 +1367,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|||
/* Guess by Vladimir.
|
||||
* Set to 0A before 3D operations, set to 02 afterwards.
|
||||
*/
|
||||
#define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C
|
||||
/*#define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C*/
|
||||
# define R300_RB3D_DSTCACHE_UNKNOWN_02 0x00000002
|
||||
# define R300_RB3D_DSTCACHE_UNKNOWN_0A 0x0000000A
|
||||
|
||||
|
|
@ -1355,19 +1376,14 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|||
* for this.
|
||||
* Bit (1<<8) is the "test" bit. so plain write is 6 - vd
|
||||
*/
|
||||
#define R300_RB3D_ZSTENCIL_CNTL_0 0x4F00
|
||||
# define R300_RB3D_Z_DISABLED_1 0x00000010
|
||||
# define R300_RB3D_Z_DISABLED_2 0x00000014
|
||||
# define R300_RB3D_Z_TEST 0x00000012
|
||||
# define R300_RB3D_Z_TEST_AND_WRITE 0x00000016
|
||||
# define R300_RB3D_Z_WRITE_ONLY 0x00000006
|
||||
#define R300_ZB_CNTL 0x4F00
|
||||
# define R300_STENCIL_ENABLE (1 << 0)
|
||||
# define R300_Z_ENABLE (1 << 1)
|
||||
# define R300_Z_WRITE_ENABLE (1 << 2)
|
||||
# define R300_Z_SIGNED_COMPARE (1 << 3)
|
||||
# define R300_STENCIL_FRONT_BACK (1 << 4)
|
||||
|
||||
# define R300_RB3D_Z_TEST 0x00000012
|
||||
# define R300_RB3D_Z_TEST_AND_WRITE 0x00000016
|
||||
# define R300_RB3D_Z_WRITE_ONLY 0x00000006
|
||||
# define R300_RB3D_STENCIL_ENABLE 0x00000001
|
||||
|
||||
#define R300_RB3D_ZSTENCIL_CNTL_1 0x4F04
|
||||
#define R300_ZB_ZSTENCILCNTL 0x4f04
|
||||
/* functions */
|
||||
# define R300_ZS_NEVER 0
|
||||
# define R300_ZS_LESS 1
|
||||
|
|
@ -1387,52 +1403,166 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|||
# define R300_ZS_INVERT 5
|
||||
# define R300_ZS_INCR_WRAP 6
|
||||
# define R300_ZS_DECR_WRAP 7
|
||||
# define R300_Z_FUNC_SHIFT 0
|
||||
/* front and back refer to operations done for front
|
||||
and back faces, i.e. separate stencil function support */
|
||||
# define R300_RB3D_ZS1_DEPTH_FUNC_SHIFT 0
|
||||
# define R300_RB3D_ZS1_FRONT_FUNC_SHIFT 3
|
||||
# define R300_RB3D_ZS1_FRONT_FAIL_OP_SHIFT 6
|
||||
# define R300_RB3D_ZS1_FRONT_ZPASS_OP_SHIFT 9
|
||||
# define R300_RB3D_ZS1_FRONT_ZFAIL_OP_SHIFT 12
|
||||
# define R300_RB3D_ZS1_BACK_FUNC_SHIFT 15
|
||||
# define R300_RB3D_ZS1_BACK_FAIL_OP_SHIFT 18
|
||||
# define R300_RB3D_ZS1_BACK_ZPASS_OP_SHIFT 21
|
||||
# define R300_RB3D_ZS1_BACK_ZFAIL_OP_SHIFT 24
|
||||
# define R300_S_FRONT_FUNC_SHIFT 3
|
||||
# define R300_S_FRONT_SFAIL_OP_SHIFT 6
|
||||
# define R300_S_FRONT_ZPASS_OP_SHIFT 9
|
||||
# define R300_S_FRONT_ZFAIL_OP_SHIFT 12
|
||||
# define R300_S_BACK_FUNC_SHIFT 15
|
||||
# define R300_S_BACK_SFAIL_OP_SHIFT 18
|
||||
# define R300_S_BACK_ZPASS_OP_SHIFT 21
|
||||
# define R300_S_BACK_ZFAIL_OP_SHIFT 24
|
||||
|
||||
#define R300_RB3D_ZSTENCIL_CNTL_2 0x4F08
|
||||
# define R300_RB3D_ZS2_STENCIL_REF_SHIFT 0
|
||||
# define R300_RB3D_ZS2_STENCIL_MASK 0xFF
|
||||
# define R300_RB3D_ZS2_STENCIL_MASK_SHIFT 8
|
||||
# define R300_RB3D_ZS2_STENCIL_WRITE_MASK_SHIFT 16
|
||||
#define R300_ZB_STENCILREFMASK 0x4f08
|
||||
# define R300_STENCILREF_SHIFT 0
|
||||
# define R300_STENCILREF_MASK 0x000000ff
|
||||
# define R300_STENCILMASK_SHIFT 8
|
||||
# define R300_STENCILMASK_MASK 0x0000ff00
|
||||
# define R300_STENCILWRITEMASK_SHIFT 16
|
||||
# define R300_STENCILWRITEMASK_MASK 0x00ff0000
|
||||
|
||||
/* gap */
|
||||
|
||||
#define R300_RB3D_ZSTENCIL_FORMAT 0x4F10
|
||||
# define R300_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
|
||||
# define R300_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
|
||||
/* 16 bit format or some aditional bit ? */
|
||||
# define R300_DEPTH_FORMAT_UNK32 (32 << 0)
|
||||
#define R300_ZB_FORMAT 0x4f10
|
||||
# define R300_DEPTHFORMAT_16BIT_INT_Z (0 << 0)
|
||||
# define R300_DEPTHFORMAT_16BIT_13E3 (1 << 0)
|
||||
# define R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL (2 << 0)
|
||||
/* reserved up to (15 << 0) */
|
||||
# define R300_INVERT_13E3_LEADING_ONES (0 << 4)
|
||||
# define R300_INVERT_13E3_LEADING_ZEROS (1 << 4)
|
||||
|
||||
#define R300_RB3D_EARLY_Z 0x4F14
|
||||
# define R300_EARLY_Z_DISABLE (0 << 0)
|
||||
# define R300_EARLY_Z_ENABLE (1 << 0)
|
||||
#define R300_ZB_ZTOP 0x4F14
|
||||
# define R300_ZTOP_DISABLE (0 << 0)
|
||||
# define R300_ZTOP_ENABLE (1 << 0)
|
||||
|
||||
/* gap */
|
||||
|
||||
#define R300_RB3D_ZCACHE_CTLSTAT 0x4F18 /* GUESS */
|
||||
# define R300_RB3D_ZCACHE_UNKNOWN_01 0x1
|
||||
# define R300_RB3D_ZCACHE_UNKNOWN_03 0x3
|
||||
#define R300_ZB_ZCACHE_CTLSTAT 0x4f18
|
||||
# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT (0 << 0)
|
||||
# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0)
|
||||
# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1)
|
||||
# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1)
|
||||
# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31)
|
||||
# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31)
|
||||
|
||||
#define R300_ZB_BW_CNTL 0x4f1c
|
||||
# define R300_HIZ_DISABLE (0 << 0)
|
||||
# define R300_HIZ_ENABLE (1 << 0)
|
||||
# define R300_HIZ_MIN (0 << 1)
|
||||
# define R300_HIZ_MAX (1 << 1)
|
||||
# define R300_FAST_FILL_DISABLE (0 << 2)
|
||||
# define R300_FAST_FILL_ENABLE (1 << 2)
|
||||
# define R300_RD_COMP_DISABLE (0 << 3)
|
||||
# define R300_RD_COMP_ENABLE (1 << 3)
|
||||
# define R300_WR_COMP_DISABLE (0 << 4)
|
||||
# define R300_WR_COMP_ENABLE (1 << 4)
|
||||
# define R300_ZB_CB_CLEAR_RMW (0 << 5)
|
||||
# define R300_ZB_CB_CLEAR_CACHE_LINEAR (1 << 5)
|
||||
# define R300_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE (0 << 6)
|
||||
# define R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE (1 << 6)
|
||||
|
||||
# define R500_ZEQUAL_OPTIMIZE_ENABLE (0 << 7)
|
||||
# define R500_ZEQUAL_OPTIMIZE_DISABLE (1 << 7)
|
||||
# define R500_SEQUAL_OPTIMIZE_ENABLE (0 << 8)
|
||||
# define R500_SEQUAL_OPTIMIZE_DISABLE (1 << 8)
|
||||
|
||||
# define R500_BMASK_ENABLE (0 << 10)
|
||||
# define R500_BMASK_DISABLE (1 << 10)
|
||||
# define R500_HIZ_EQUAL_REJECT_DISABLE (0 << 11)
|
||||
# define R500_HIZ_EQUAL_REJECT_ENABLE (1 << 11)
|
||||
# define R500_HIZ_FP_EXP_BITS_DISABLE (0 << 12)
|
||||
# define R500_HIZ_FP_EXP_BITS_1 (1 << 12)
|
||||
# define R500_HIZ_FP_EXP_BITS_2 (2 << 12)
|
||||
# define R500_HIZ_FP_EXP_BITS_3 (3 << 12)
|
||||
# define R500_HIZ_FP_EXP_BITS_4 (4 << 12)
|
||||
# define R500_HIZ_FP_EXP_BITS_5 (5 << 12)
|
||||
# define R500_HIZ_FP_INVERT_LEADING_ONES (0 << 15)
|
||||
# define R500_HIZ_FP_INVERT_LEADING_ZEROS (1 << 15)
|
||||
# define R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE (0 << 16)
|
||||
# define R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE (1 << 16)
|
||||
# define R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE (0 << 17)
|
||||
# define R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE (1 << 17)
|
||||
# define R500_PEQ_PACKING_DISABLE (0 << 18)
|
||||
# define R500_PEQ_PACKING_ENABLE (1 << 18)
|
||||
# define R500_COVERED_PTR_MASKING_DISABLE (0 << 18)
|
||||
# define R500_COVERED_PTR_MASKING_ENABLE (1 << 18)
|
||||
|
||||
|
||||
/* gap */
|
||||
|
||||
#define R300_RB3D_DEPTHOFFSET 0x4F20
|
||||
#define R300_RB3D_DEPTHPITCH 0x4F24
|
||||
# define R300_DEPTHPITCH_MASK 0x00001FF8 /* GUESS */
|
||||
# define R300_DEPTH_TILE_ENABLE (1 << 16) /* GUESS */
|
||||
# define R300_DEPTH_MICROTILE_ENABLE (1 << 17) /* GUESS */
|
||||
# define R300_DEPTH_ENDIAN_NO_SWAP (0 << 18) /* GUESS */
|
||||
# define R300_DEPTH_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */
|
||||
# define R300_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */
|
||||
/* Z Buffer Address Offset.
|
||||
* Bits 31 to 5 are used for aligned Z buffer address offset for macro tiles.
|
||||
*/
|
||||
#define R300_ZB_DEPTHOFFSET 0x4f20
|
||||
|
||||
/* Z Buffer Pitch and Endian Control */
|
||||
#define R300_ZB_DEPTHPITCH 0x4f24
|
||||
# define R300_DEPTHPITCH_MASK 0x00003FFC
|
||||
# define R300_DEPTHMACROTILE_DISABLE (0 << 16)
|
||||
# define R300_DEPTHMACROTILE_ENABLE (1 << 16)
|
||||
# define R300_DEPTHMICROTILE_LINEAR (0 << 17)
|
||||
# define R300_DEPTHMICROTILE_TILED (1 << 17)
|
||||
# define R300_DEPTHMICROTILE_TILED_SQUARE (2 << 17)
|
||||
# define R300_DEPTHENDIAN_NO_SWAP (0 << 18)
|
||||
# define R300_DEPTHENDIAN_WORD_SWAP (1 << 18)
|
||||
# define R300_DEPTHENDIAN_DWORD_SWAP (2 << 18)
|
||||
# define R300_DEPTHENDIAN_HALF_DWORD_SWAP (3 << 18)
|
||||
|
||||
/* Z Buffer Clear Value */
|
||||
#define R300_ZB_DEPTHCLEARVALUE 0x4f28
|
||||
|
||||
#define R300_ZB_ZMASK_OFFSET 0x4f30
|
||||
#define R300_ZB_ZMASK_PITCH 0x4f34
|
||||
#define R300_ZB_ZMASK_WRINDEX 0x4f38
|
||||
#define R300_ZB_ZMASK_DWORD 0x4f3c
|
||||
#define R300_ZB_ZMASK_RDINDEX 0x4f40
|
||||
|
||||
/* Hierarchical Z Memory Offset */
|
||||
#define R300_ZB_HIZ_OFFSET 0x4f44
|
||||
|
||||
/* Hierarchical Z Write Index */
|
||||
#define R300_ZB_HIZ_WRINDEX 0x4f48
|
||||
|
||||
/* Hierarchical Z Data */
|
||||
#define R300_ZB_HIZ_DWORD 0x4f4c
|
||||
|
||||
/* Hierarchical Z Read Index */
|
||||
#define R300_ZB_HIZ_RDINDEX 0x4f50
|
||||
|
||||
/* Hierarchical Z Pitch */
|
||||
#define R300_ZB_HIZ_PITCH 0x4f54
|
||||
|
||||
/* Z Buffer Z Pass Counter Data */
|
||||
#define R300_ZB_ZPASS_DATA 0x4f58
|
||||
|
||||
/* Z Buffer Z Pass Counter Address */
|
||||
#define R300_ZB_ZPASS_ADDR 0x4f5c
|
||||
|
||||
/* Depth buffer X and Y coordinate offset */
|
||||
#define R300_ZB_DEPTHXY_OFFSET 0x4f60
|
||||
# define R300_DEPTHX_OFFSET_SHIFT 1
|
||||
# define R300_DEPTHX_OFFSET_MASK 0x000007FE
|
||||
# define R300_DEPTHY_OFFSET_SHIFT 17
|
||||
# define R300_DEPTHY_OFFSET_MASK 0x07FE0000
|
||||
|
||||
/* Sets the fifo sizes */
|
||||
#define R500_ZB_FIFO_SIZE 0x4fd0
|
||||
# define R500_OP_FIFO_SIZE_FULL (0 << 0)
|
||||
# define R500_OP_FIFO_SIZE_HALF (1 << 0)
|
||||
# define R500_OP_FIFO_SIZE_QUATER (2 << 0)
|
||||
# define R500_OP_FIFO_SIZE_EIGTHS (4 << 0)
|
||||
|
||||
/* Stencil Reference Value and Mask for backfacing quads */
|
||||
/* R300_ZB_STENCILREFMASK handles front face */
|
||||
#define R500_ZB_STENCILREFMASK_BF 0x4fd4
|
||||
# define R500_STENCILREF_SHIFT 0
|
||||
# define R500_STENCILREF_MASK 0x000000ff
|
||||
# define R500_STENCILMASK_SHIFT 8
|
||||
# define R500_STENCILMASK_MASK 0x0000ff00
|
||||
# define R500_STENCILWRITEMASK_SHIFT 16
|
||||
# define R500_STENCILWRITEMASK_MASK 0x00ff0000
|
||||
|
||||
/* BEGIN: Vertex program instruction set */
|
||||
|
||||
|
|
@ -1623,4 +1753,20 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|||
*/
|
||||
#define R300_CP_CMD_BITBLT_MULTI 0xC0009B00
|
||||
|
||||
#define R500_VAP_INDEX_OFFSET 0x208c
|
||||
|
||||
#define R500_GA_US_VECTOR_INDEX 0x4250
|
||||
#define R500_GA_US_VECTOR_DATA 0x4254
|
||||
|
||||
#define R500_RS_IP_0 0x4074
|
||||
#define R500_RS_INST_0 0x4320
|
||||
|
||||
#define R500_US_CONFIG 0x4600
|
||||
|
||||
#define R500_US_FC_CTRL 0x4624
|
||||
#define R500_US_CODE_ADDR 0x4630
|
||||
|
||||
#define R500_RB3D_COLOR_CLEAR_VALUE_AR 0x46c0
|
||||
#define R500_RB3D_CONSTANT_COLOR_AR 0x4ef8
|
||||
|
||||
#endif /* _R300_REG_H */
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -240,6 +240,7 @@ typedef union {
|
|||
# define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8
|
||||
|
||||
#define R300_CMD_SCRATCH 8
|
||||
#define R300_CMD_R500FP 9
|
||||
|
||||
typedef union {
|
||||
unsigned int u;
|
||||
|
|
@ -268,6 +269,9 @@ typedef union {
|
|||
struct {
|
||||
unsigned char cmd_type, reg, n_bufs, flags;
|
||||
} scratch;
|
||||
struct {
|
||||
unsigned char cmd_type, count, adrlo, adrhi_flags;
|
||||
} r500fp;
|
||||
} drm_r300_cmd_header_t;
|
||||
|
||||
#define RADEON_FRONT 0x1
|
||||
|
|
@ -278,6 +282,9 @@ typedef union {
|
|||
#define RADEON_USE_HIERZ 0x40000000
|
||||
#define RADEON_USE_COMP_ZBUF 0x20000000
|
||||
|
||||
#define R500FP_CONSTANT_TYPE (1 << 1)
|
||||
#define R500FP_CONSTANT_CLAMP (1 << 2)
|
||||
|
||||
/* Primitive types
|
||||
*/
|
||||
#define RADEON_POINTS 0x1
|
||||
|
|
@ -669,6 +676,7 @@ typedef struct drm_radeon_indirect {
|
|||
#define RADEON_PARAM_CARD_TYPE 12
|
||||
#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */
|
||||
#define RADEON_PARAM_FB_LOCATION 14 /* FB location */
|
||||
#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */
|
||||
|
||||
typedef struct drm_radeon_getparam {
|
||||
int param;
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@
|
|||
|
||||
#define DRIVER_NAME "radeon"
|
||||
#define DRIVER_DESC "ATI Radeon"
|
||||
#define DRIVER_DATE "20060524"
|
||||
#define DRIVER_DATE "20080528"
|
||||
|
||||
/* Interface history:
|
||||
*
|
||||
|
|
@ -98,9 +98,10 @@
|
|||
* 1.26- Add support for variable size PCI(E) gart aperture
|
||||
* 1.27- Add support for IGP GART
|
||||
* 1.28- Add support for VBL on CRTC2
|
||||
* 1.29- R500 3D cmd buffer support
|
||||
*/
|
||||
#define DRIVER_MAJOR 1
|
||||
#define DRIVER_MINOR 28
|
||||
#define DRIVER_MINOR 29
|
||||
#define DRIVER_PATCHLEVEL 0
|
||||
|
||||
/*
|
||||
|
|
@ -122,7 +123,7 @@ enum radeon_family {
|
|||
CHIP_RV380,
|
||||
CHIP_R420,
|
||||
CHIP_RV410,
|
||||
CHIP_RS400,
|
||||
CHIP_RS480,
|
||||
CHIP_RS690,
|
||||
CHIP_RV515,
|
||||
CHIP_R520,
|
||||
|
|
@ -294,6 +295,7 @@ typedef struct drm_radeon_private {
|
|||
int vblank_crtc;
|
||||
uint32_t irq_enable_reg;
|
||||
int irq_enabled;
|
||||
uint32_t r500_disp_irq_reg;
|
||||
|
||||
struct radeon_surface surfaces[RADEON_MAX_SURFACES];
|
||||
struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
|
||||
|
|
@ -307,6 +309,8 @@ typedef struct drm_radeon_private {
|
|||
/* starting from here on, data is preserved accross an open */
|
||||
uint32_t flags; /* see radeon_chip_flags */
|
||||
unsigned long fb_aper_offset;
|
||||
|
||||
int num_gb_pipes;
|
||||
} drm_radeon_private_t;
|
||||
|
||||
typedef struct drm_radeon_buf_priv {
|
||||
|
|
@ -382,6 +386,7 @@ extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
|
|||
extern void radeon_driver_irq_preinstall(struct drm_device * dev);
|
||||
extern void radeon_driver_irq_postinstall(struct drm_device * dev);
|
||||
extern void radeon_driver_irq_uninstall(struct drm_device * dev);
|
||||
extern void radeon_enable_interrupt(struct drm_device *dev);
|
||||
extern int radeon_vblank_crtc_get(struct drm_device *dev);
|
||||
extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
|
||||
|
||||
|
|
@ -444,13 +449,13 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
|
|||
#define RADEON_PCIE_DATA 0x0034
|
||||
#define RADEON_PCIE_TX_GART_CNTL 0x10
|
||||
# define RADEON_PCIE_TX_GART_EN (1 << 0)
|
||||
# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1)
|
||||
# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1)
|
||||
# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1)
|
||||
# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3)
|
||||
# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3)
|
||||
# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5)
|
||||
# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8)
|
||||
# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
|
||||
# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1)
|
||||
# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1)
|
||||
# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3)
|
||||
# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3)
|
||||
# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5)
|
||||
# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8)
|
||||
#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
|
||||
#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
|
||||
#define RADEON_PCIE_TX_GART_BASE 0x13
|
||||
|
|
@ -459,14 +464,9 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
|
|||
#define RADEON_PCIE_TX_GART_END_LO 0x16
|
||||
#define RADEON_PCIE_TX_GART_END_HI 0x17
|
||||
|
||||
#define RADEON_IGPGART_INDEX 0x168
|
||||
#define RADEON_IGPGART_DATA 0x16c
|
||||
#define RADEON_IGPGART_UNK_18 0x18
|
||||
#define RADEON_IGPGART_CTRL 0x2b
|
||||
#define RADEON_IGPGART_BASE_ADDR 0x2c
|
||||
#define RADEON_IGPGART_FLUSH 0x2e
|
||||
#define RADEON_IGPGART_ENABLE 0x38
|
||||
#define RADEON_IGPGART_UNK_39 0x39
|
||||
#define RS480_NB_MC_INDEX 0x168
|
||||
# define RS480_NB_MC_IND_WR_EN (1 << 8)
|
||||
#define RS480_NB_MC_DATA 0x16c
|
||||
|
||||
#define RS690_MC_INDEX 0x78
|
||||
# define RS690_MC_INDEX_MASK 0x1ff
|
||||
|
|
@ -474,45 +474,91 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
|
|||
# define RS690_MC_INDEX_WR_ACK 0x7f
|
||||
#define RS690_MC_DATA 0x7c
|
||||
|
||||
#define RS690_MC_MISC_CNTL 0x18
|
||||
#define RS690_MC_GART_FEATURE_ID 0x2b
|
||||
#define RS690_MC_GART_BASE 0x2c
|
||||
#define RS690_MC_GART_CACHE_CNTL 0x2e
|
||||
# define RS690_MC_GART_CC_NO_CHANGE 0x0
|
||||
# define RS690_MC_GART_CC_CLEAR 0x1
|
||||
# define RS690_MC_GART_CLEAR_STATUS (1 << 1)
|
||||
# define RS690_MC_GART_CLEAR_DONE (0 << 1)
|
||||
# define RS690_MC_GART_CLEAR_PENDING (1 << 1)
|
||||
#define RS690_MC_AGP_SIZE 0x38
|
||||
# define RS690_MC_GART_DIS 0x0
|
||||
# define RS690_MC_GART_EN 0x1
|
||||
# define RS690_MC_AGP_SIZE_32MB (0 << 1)
|
||||
# define RS690_MC_AGP_SIZE_64MB (1 << 1)
|
||||
# define RS690_MC_AGP_SIZE_128MB (2 << 1)
|
||||
# define RS690_MC_AGP_SIZE_256MB (3 << 1)
|
||||
# define RS690_MC_AGP_SIZE_512MB (4 << 1)
|
||||
# define RS690_MC_AGP_SIZE_1GB (5 << 1)
|
||||
# define RS690_MC_AGP_SIZE_2GB (6 << 1)
|
||||
#define RS690_MC_AGP_MODE_CONTROL 0x39
|
||||
/* MC indirect registers */
|
||||
#define RS480_MC_MISC_CNTL 0x18
|
||||
# define RS480_DISABLE_GTW (1 << 1)
|
||||
/* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */
|
||||
# define RS480_GART_INDEX_REG_EN (1 << 12)
|
||||
# define RS690_BLOCK_GFX_D3_EN (1 << 14)
|
||||
#define RS480_K8_FB_LOCATION 0x1e
|
||||
#define RS480_GART_FEATURE_ID 0x2b
|
||||
# define RS480_HANG_EN (1 << 11)
|
||||
# define RS480_TLB_ENABLE (1 << 18)
|
||||
# define RS480_P2P_ENABLE (1 << 19)
|
||||
# define RS480_GTW_LAC_EN (1 << 25)
|
||||
# define RS480_2LEVEL_GART (0 << 30)
|
||||
# define RS480_1LEVEL_GART (1 << 30)
|
||||
# define RS480_PDC_EN (1 << 31)
|
||||
#define RS480_GART_BASE 0x2c
|
||||
#define RS480_GART_CACHE_CNTRL 0x2e
|
||||
# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
|
||||
#define RS480_AGP_ADDRESS_SPACE_SIZE 0x38
|
||||
# define RS480_GART_EN (1 << 0)
|
||||
# define RS480_VA_SIZE_32MB (0 << 1)
|
||||
# define RS480_VA_SIZE_64MB (1 << 1)
|
||||
# define RS480_VA_SIZE_128MB (2 << 1)
|
||||
# define RS480_VA_SIZE_256MB (3 << 1)
|
||||
# define RS480_VA_SIZE_512MB (4 << 1)
|
||||
# define RS480_VA_SIZE_1GB (5 << 1)
|
||||
# define RS480_VA_SIZE_2GB (6 << 1)
|
||||
#define RS480_AGP_MODE_CNTL 0x39
|
||||
# define RS480_POST_GART_Q_SIZE (1 << 18)
|
||||
# define RS480_NONGART_SNOOP (1 << 19)
|
||||
# define RS480_AGP_RD_BUF_SIZE (1 << 20)
|
||||
# define RS480_REQ_TYPE_SNOOP_SHIFT 22
|
||||
# define RS480_REQ_TYPE_SNOOP_MASK 0x3
|
||||
# define RS480_REQ_TYPE_SNOOP_DIS (1 << 24)
|
||||
#define RS480_MC_MISC_UMA_CNTL 0x5f
|
||||
#define RS480_MC_MCLK_CNTL 0x7a
|
||||
#define RS480_MC_UMA_DUALCH_CNTL 0x86
|
||||
|
||||
#define RS690_MC_FB_LOCATION 0x100
|
||||
#define RS690_MC_AGP_LOCATION 0x101
|
||||
#define RS690_MC_AGP_BASE 0x102
|
||||
#define RS690_MC_AGP_BASE_2 0x103
|
||||
|
||||
#define R520_MC_IND_INDEX 0x70
|
||||
#define R520_MC_IND_WR_EN (1<<24)
|
||||
#define R520_MC_IND_WR_EN (1 << 24)
|
||||
#define R520_MC_IND_DATA 0x74
|
||||
|
||||
#define RV515_MC_FB_LOCATION 0x01
|
||||
#define RV515_MC_AGP_LOCATION 0x02
|
||||
#define RV515_MC_AGP_BASE 0x03
|
||||
#define RV515_MC_AGP_BASE_2 0x04
|
||||
|
||||
#define R520_MC_FB_LOCATION 0x04
|
||||
#define R520_MC_AGP_LOCATION 0x05
|
||||
#define R520_MC_AGP_BASE 0x06
|
||||
#define R520_MC_AGP_BASE_2 0x07
|
||||
|
||||
#define RADEON_MPP_TB_CONFIG 0x01c0
|
||||
#define RADEON_MEM_CNTL 0x0140
|
||||
#define RADEON_MEM_SDRAM_MODE_REG 0x0158
|
||||
#define RADEON_AGP_BASE_2 0x015c /* r200+ only */
|
||||
#define RS480_AGP_BASE_2 0x0164
|
||||
#define RADEON_AGP_BASE 0x0170
|
||||
|
||||
/* pipe config regs */
|
||||
#define R400_GB_PIPE_SELECT 0x402c
|
||||
#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */
|
||||
#define R500_SU_REG_DEST 0x42c8
|
||||
#define R300_GB_TILE_CONFIG 0x4018
|
||||
# define R300_ENABLE_TILING (1 << 0)
|
||||
# define R300_PIPE_COUNT_RV350 (0 << 1)
|
||||
# define R300_PIPE_COUNT_R300 (3 << 1)
|
||||
# define R300_PIPE_COUNT_R420_3P (6 << 1)
|
||||
# define R300_PIPE_COUNT_R420 (7 << 1)
|
||||
# define R300_TILE_SIZE_8 (0 << 4)
|
||||
# define R300_TILE_SIZE_16 (1 << 4)
|
||||
# define R300_TILE_SIZE_32 (2 << 4)
|
||||
# define R300_SUBPIXEL_1_12 (0 << 16)
|
||||
# define R300_SUBPIXEL_1_16 (1 << 16)
|
||||
#define R300_DST_PIPE_CONFIG 0x170c
|
||||
# define R300_PIPE_AUTO_CONFIG (1 << 31)
|
||||
#define R300_RB2D_DSTCACHE_MODE 0x3428
|
||||
# define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
|
||||
# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
|
||||
|
||||
#define RADEON_RB3D_COLOROFFSET 0x1c40
|
||||
#define RADEON_RB3D_COLORPITCH 0x1c48
|
||||
|
||||
|
|
@ -616,11 +662,12 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
|
|||
#define RADEON_PP_TXFILTER_1 0x1c6c
|
||||
#define RADEON_PP_TXFILTER_2 0x1c84
|
||||
|
||||
#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
|
||||
# define RADEON_RB2D_DC_FLUSH (3 << 0)
|
||||
# define RADEON_RB2D_DC_FREE (3 << 2)
|
||||
# define RADEON_RB2D_DC_FLUSH_ALL 0xf
|
||||
# define RADEON_RB2D_DC_BUSY (1 << 31)
|
||||
#define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */
|
||||
#define R300_DSTCACHE_CTLSTAT 0x1714
|
||||
# define R300_RB2D_DC_FLUSH (3 << 0)
|
||||
# define R300_RB2D_DC_FREE (3 << 2)
|
||||
# define R300_RB2D_DC_FLUSH_ALL 0xf
|
||||
# define R300_RB2D_DC_BUSY (1 << 31)
|
||||
#define RADEON_RB3D_CNTL 0x1c3c
|
||||
# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
|
||||
# define RADEON_PLANE_MASK_ENABLE (1 << 1)
|
||||
|
|
@ -643,11 +690,18 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
|
|||
# define RADEON_RB3D_ZC_FREE (1 << 2)
|
||||
# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
|
||||
# define RADEON_RB3D_ZC_BUSY (1 << 31)
|
||||
#define R300_ZB_ZCACHE_CTLSTAT 0x4f18
|
||||
# define R300_ZC_FLUSH (1 << 0)
|
||||
# define R300_ZC_FREE (1 << 1)
|
||||
# define R300_ZC_FLUSH_ALL 0x3
|
||||
# define R300_ZC_BUSY (1 << 31)
|
||||
#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
|
||||
# define RADEON_RB3D_DC_FLUSH (3 << 0)
|
||||
# define RADEON_RB3D_DC_FREE (3 << 2)
|
||||
# define RADEON_RB3D_DC_FLUSH_ALL 0xf
|
||||
# define RADEON_RB3D_DC_BUSY (1 << 31)
|
||||
#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
|
||||
# define R300_RB3D_DC_FINISH (1 << 4)
|
||||
#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
|
||||
# define RADEON_Z_TEST_MASK (7 << 4)
|
||||
# define RADEON_Z_TEST_ALWAYS (7 << 4)
|
||||
|
|
@ -1057,6 +1111,31 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
|
|||
|
||||
#define R200_VAP_PVS_CNTL_1 0x22D0
|
||||
|
||||
#define R500_D1CRTC_STATUS 0x609c
|
||||
#define R500_D2CRTC_STATUS 0x689c
|
||||
#define R500_CRTC_V_BLANK (1<<0)
|
||||
|
||||
#define R500_D1CRTC_FRAME_COUNT 0x60a4
|
||||
#define R500_D2CRTC_FRAME_COUNT 0x68a4
|
||||
|
||||
#define R500_D1MODE_V_COUNTER 0x6530
|
||||
#define R500_D2MODE_V_COUNTER 0x6d30
|
||||
|
||||
#define R500_D1MODE_VBLANK_STATUS 0x6534
|
||||
#define R500_D2MODE_VBLANK_STATUS 0x6d34
|
||||
#define R500_VBLANK_OCCURED (1<<0)
|
||||
#define R500_VBLANK_ACK (1<<4)
|
||||
#define R500_VBLANK_STAT (1<<12)
|
||||
#define R500_VBLANK_INT (1<<16)
|
||||
|
||||
#define R500_DxMODE_INT_MASK 0x6540
|
||||
#define R500_D1MODE_INT_MASK (1<<0)
|
||||
#define R500_D2MODE_INT_MASK (1<<8)
|
||||
|
||||
#define R500_DISP_INTERRUPT_STATUS 0x7edc
|
||||
#define R500_D1_VBLANK_INTERRUPT (1 << 4)
|
||||
#define R500_D2_VBLANK_INTERRUPT (1 << 5)
|
||||
|
||||
/* Constants */
|
||||
#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
|
||||
|
||||
|
|
@ -1078,42 +1157,50 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
|
|||
#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
|
||||
#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
|
||||
|
||||
#define RADEON_WRITE_PLL( addr, val ) \
|
||||
#define RADEON_WRITE_PLL(addr, val) \
|
||||
do { \
|
||||
RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \
|
||||
RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \
|
||||
((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
|
||||
RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \
|
||||
RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \
|
||||
} while (0)
|
||||
|
||||
#define RADEON_WRITE_IGPGART( addr, val ) \
|
||||
#define RADEON_WRITE_PCIE(addr, val) \
|
||||
do { \
|
||||
RADEON_WRITE( RADEON_IGPGART_INDEX, \
|
||||
((addr) & 0x7f) | (1 << 8)); \
|
||||
RADEON_WRITE( RADEON_IGPGART_DATA, (val) ); \
|
||||
RADEON_WRITE( RADEON_IGPGART_INDEX, 0x7f ); \
|
||||
} while (0)
|
||||
|
||||
#define RADEON_WRITE_PCIE( addr, val ) \
|
||||
do { \
|
||||
RADEON_WRITE8( RADEON_PCIE_INDEX, \
|
||||
RADEON_WRITE8(RADEON_PCIE_INDEX, \
|
||||
((addr) & 0xff)); \
|
||||
RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \
|
||||
RADEON_WRITE(RADEON_PCIE_DATA, (val)); \
|
||||
} while (0)
|
||||
|
||||
#define RADEON_WRITE_MCIND( addr, val ) \
|
||||
do { \
|
||||
RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
|
||||
RADEON_WRITE(R520_MC_IND_DATA, (val)); \
|
||||
RADEON_WRITE(R520_MC_IND_INDEX, 0); \
|
||||
} while (0)
|
||||
#define R500_WRITE_MCIND(addr, val) \
|
||||
do { \
|
||||
RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
|
||||
RADEON_WRITE(R520_MC_IND_DATA, (val)); \
|
||||
RADEON_WRITE(R520_MC_IND_INDEX, 0); \
|
||||
} while (0)
|
||||
|
||||
#define RS690_WRITE_MCIND( addr, val ) \
|
||||
#define RS480_WRITE_MCIND(addr, val) \
|
||||
do { \
|
||||
RADEON_WRITE(RS480_NB_MC_INDEX, \
|
||||
((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \
|
||||
RADEON_WRITE(RS480_NB_MC_DATA, (val)); \
|
||||
RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \
|
||||
} while (0)
|
||||
|
||||
#define RS690_WRITE_MCIND(addr, val) \
|
||||
do { \
|
||||
RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \
|
||||
RADEON_WRITE(RS690_MC_DATA, val); \
|
||||
RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \
|
||||
} while (0)
|
||||
|
||||
#define IGP_WRITE_MCIND(addr, val) \
|
||||
do { \
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) \
|
||||
RS690_WRITE_MCIND(addr, val); \
|
||||
else \
|
||||
RS480_WRITE_MCIND(addr, val); \
|
||||
} while (0)
|
||||
|
||||
#define CP_PACKET0( reg, n ) \
|
||||
(RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
|
||||
#define CP_PACKET0_TABLE( reg, n ) \
|
||||
|
|
@ -1154,23 +1241,43 @@ do { \
|
|||
} while (0)
|
||||
|
||||
#define RADEON_FLUSH_CACHE() do { \
|
||||
OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
|
||||
OUT_RING( RADEON_RB3D_DC_FLUSH ); \
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
|
||||
OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
|
||||
OUT_RING(RADEON_RB3D_DC_FLUSH); \
|
||||
} else { \
|
||||
OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
|
||||
OUT_RING(RADEON_RB3D_DC_FLUSH); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define RADEON_PURGE_CACHE() do { \
|
||||
OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
|
||||
OUT_RING( RADEON_RB3D_DC_FLUSH_ALL ); \
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
|
||||
OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
|
||||
OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \
|
||||
} else { \
|
||||
OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
|
||||
OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define RADEON_FLUSH_ZCACHE() do { \
|
||||
OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
|
||||
OUT_RING( RADEON_RB3D_ZC_FLUSH ); \
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
|
||||
OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
|
||||
OUT_RING(RADEON_RB3D_ZC_FLUSH); \
|
||||
} else { \
|
||||
OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
|
||||
OUT_RING(R300_ZC_FLUSH); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define RADEON_PURGE_ZCACHE() do { \
|
||||
OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
|
||||
OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
|
||||
OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
|
||||
OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL); \
|
||||
} else { \
|
||||
OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
|
||||
OUT_RING(R300_ZC_FLUSH_ALL); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
/* ================================================================
|
||||
|
|
|
|||
|
|
@ -234,7 +234,7 @@ int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_pr
|
|||
return radeon_wait_irq(dev, irqwait->irq_seq);
|
||||
}
|
||||
|
||||
static void radeon_enable_interrupt(struct drm_device *dev)
|
||||
void radeon_enable_interrupt(struct drm_device *dev)
|
||||
{
|
||||
drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1662,7 +1662,7 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
|
|||
u32 height;
|
||||
int i;
|
||||
u32 texpitch, microtile;
|
||||
u32 offset;
|
||||
u32 offset, byte_offset;
|
||||
RING_LOCALS;
|
||||
|
||||
if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) {
|
||||
|
|
@ -1727,6 +1727,13 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
|
|||
} else
|
||||
microtile = 0;
|
||||
|
||||
/* this might fail for zero-sized uploads - are those illegal? */
|
||||
if (!radeon_check_offset(dev_priv, tex->offset + image->height *
|
||||
blit_width - 1)) {
|
||||
DRM_ERROR("Invalid final destination offset\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width);
|
||||
|
||||
do {
|
||||
|
|
@ -1840,6 +1847,7 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
|
|||
}
|
||||
|
||||
#undef RADEON_COPY_MT
|
||||
byte_offset = (image->y & ~2047) * blit_width;
|
||||
buf->file_priv = file_priv;
|
||||
buf->used = size;
|
||||
offset = dev_priv->gart_buffers_offset + buf->offset;
|
||||
|
|
@ -1854,9 +1862,9 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
|
|||
RADEON_DP_SRC_SOURCE_MEMORY |
|
||||
RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
|
||||
OUT_RING((spitch << 22) | (offset >> 10));
|
||||
OUT_RING((texpitch << 22) | (tex->offset >> 10));
|
||||
OUT_RING((texpitch << 22) | ((tex->offset >> 10) + (byte_offset >> 10)));
|
||||
OUT_RING(0);
|
||||
OUT_RING((image->x << 16) | image->y);
|
||||
OUT_RING((image->x << 16) | (image->y % 2048));
|
||||
OUT_RING((image->width << 16) | height);
|
||||
RADEON_WAIT_UNTIL_2D_IDLE();
|
||||
ADVANCE_RING();
|
||||
|
|
@ -3037,6 +3045,9 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
|
|||
case RADEON_PARAM_FB_LOCATION:
|
||||
value = radeon_read_fb_location(dev_priv);
|
||||
break;
|
||||
case RADEON_PARAM_NUM_GB_PIPES:
|
||||
value = dev_priv->num_gb_pipes;
|
||||
break;
|
||||
default:
|
||||
DRM_DEBUG("Invalid parameter %d\n", param->param);
|
||||
return -EINVAL;
|
||||
|
|
|
|||
Loading…
Reference in New Issue