drm/i915: Use the fixed pixel clock for eDP in intel_dp_set_m_n()
The eDP output on HP Z1 is still broken when X is started even after fixing the infinite link-train loop. The regression was introduced in 3.6 kernel for cleaning up the mode clock handling code in intel_dp.c by the commit [71244653: drm/i915: adjusted_mode->clock in the dp mode_fix]. In the past, the clock of the reference mode was modified in intel_dp_mode_fixup() in the case of eDP fixed clock, and this clock was used for calculating in intel_dp_set_m_n(). This override was removed, thus the wrong mode clock is used for the calculation, resulting in a psychedelic smoking output in the end. This patch corrects the clock to be used in the place. v1->v2: Use intel_edp_target_clock() for checking eDP fixed clock instead of open code as in ironlake_set_m_n(). Cc: <stable@vger.kernel.org> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -820,6 +820,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
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struct intel_link_m_n m_n;
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int pipe = intel_crtc->pipe;
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enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
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int target_clock;
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/*
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* Find the lane count in the intel_encoder private
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@ -835,13 +836,22 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
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}
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}
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target_clock = mode->clock;
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for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
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if (intel_encoder->type == INTEL_OUTPUT_EDP) {
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target_clock = intel_edp_target_clock(intel_encoder,
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mode);
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break;
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}
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}
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/*
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* Compute the GMCH and Link ratios. The '3' here is
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* the number of bytes_per_pixel post-LUT, which we always
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* set up for 8-bits of R/G/B, or 3 bytes total.
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*/
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intel_link_compute_m_n(intel_crtc->bpp, lane_count,
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mode->clock, adjusted_mode->clock, &m_n);
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target_clock, adjusted_mode->clock, &m_n);
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if (IS_HASWELL(dev)) {
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I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
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