ixgbe: update PHY code to support 100Mbps as well as 1G/10G
This change updates the PHY setup code to support 100Mbps capable PHYs as well as 10G and 1Gbps. Signed-off-by: Emil Tantilov <emil.s.tantilov@intel.com> Tested-by: Stephen Ko <stephen.s.ko@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
parent
7e7eb43463
commit
9dda173667
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@ -158,6 +158,7 @@ static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
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switch (hw->phy.type) {
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switch (hw->phy.type) {
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case ixgbe_phy_tn:
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case ixgbe_phy_tn:
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phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
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phy->ops.check_link = &ixgbe_check_phy_link_tnx;
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phy->ops.check_link = &ixgbe_check_phy_link_tnx;
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phy->ops.get_firmware_version =
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phy->ops.get_firmware_version =
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&ixgbe_get_phy_firmware_version_tnx;
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&ixgbe_get_phy_firmware_version_tnx;
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@ -402,49 +402,89 @@ s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
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**/
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**/
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s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
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s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
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{
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{
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s32 status = IXGBE_NOT_IMPLEMENTED;
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s32 status = 0;
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u32 time_out;
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u32 time_out;
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u32 max_time_out = 10;
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u32 max_time_out = 10;
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u16 autoneg_reg;
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u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
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bool autoneg = false;
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ixgbe_link_speed speed;
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/*
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ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
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* Set advertisement settings in PHY based on autoneg_advertised
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* settings. If autoneg_advertised = 0, then advertise default values
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if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
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* tnx devices cannot be "forced" to a autoneg 10G and fail. But can
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/* Set or unset auto-negotiation 10G advertisement */
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* for a 1G.
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hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
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*/
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MDIO_MMD_AN,
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hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg);
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&autoneg_reg);
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if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL)
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autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
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autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
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else
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if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
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autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
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autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
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hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg);
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hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
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MDIO_MMD_AN,
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autoneg_reg);
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}
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if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
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/* Set or unset auto-negotiation 1G advertisement */
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hw->phy.ops.read_reg(hw,
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IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
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MDIO_MMD_AN,
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&autoneg_reg);
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autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
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if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
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autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
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hw->phy.ops.write_reg(hw,
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IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
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MDIO_MMD_AN,
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autoneg_reg);
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}
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if (speed & IXGBE_LINK_SPEED_100_FULL) {
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/* Set or unset auto-negotiation 100M advertisement */
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hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
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MDIO_MMD_AN,
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&autoneg_reg);
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autoneg_reg &= ~ADVERTISE_100FULL;
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if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
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autoneg_reg |= ADVERTISE_100FULL;
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hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
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MDIO_MMD_AN,
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autoneg_reg);
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}
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/* Restart PHY autonegotiation and wait for completion */
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/* Restart PHY autonegotiation and wait for completion */
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hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, &autoneg_reg);
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hw->phy.ops.read_reg(hw, MDIO_CTRL1,
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MDIO_MMD_AN, &autoneg_reg);
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autoneg_reg |= MDIO_AN_CTRL1_RESTART;
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autoneg_reg |= MDIO_AN_CTRL1_RESTART;
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hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, autoneg_reg);
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hw->phy.ops.write_reg(hw, MDIO_CTRL1,
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MDIO_MMD_AN, autoneg_reg);
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/* Wait for autonegotiation to finish */
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/* Wait for autonegotiation to finish */
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for (time_out = 0; time_out < max_time_out; time_out++) {
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for (time_out = 0; time_out < max_time_out; time_out++) {
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udelay(10);
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udelay(10);
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/* Restart PHY autonegotiation and wait for completion */
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/* Restart PHY autonegotiation and wait for completion */
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status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
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status = hw->phy.ops.read_reg(hw, MDIO_STAT1,
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&autoneg_reg);
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MDIO_MMD_AN,
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&autoneg_reg);
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autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
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autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
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if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) {
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if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) {
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status = 0;
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break;
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break;
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}
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}
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}
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}
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if (time_out == max_time_out)
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if (time_out == max_time_out) {
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status = IXGBE_ERR_LINK_SETUP;
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status = IXGBE_ERR_LINK_SETUP;
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hw_dbg(hw, "ixgbe_setup_phy_link_generic: time out");
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}
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return status;
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return status;
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}
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}
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@ -473,6 +513,9 @@ s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
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if (speed & IXGBE_LINK_SPEED_1GB_FULL)
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if (speed & IXGBE_LINK_SPEED_1GB_FULL)
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hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
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hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
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if (speed & IXGBE_LINK_SPEED_100_FULL)
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hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
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/* Setup link based on the new speed settings */
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/* Setup link based on the new speed settings */
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hw->phy.ops.setup_link(hw);
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hw->phy.ops.setup_link(hw);
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@ -512,6 +555,180 @@ s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
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return status;
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return status;
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}
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}
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/**
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* ixgbe_check_phy_link_tnx - Determine link and speed status
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* @hw: pointer to hardware structure
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*
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* Reads the VS1 register to determine if link is up and the current speed for
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* the PHY.
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**/
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s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
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bool *link_up)
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{
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s32 status = 0;
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u32 time_out;
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u32 max_time_out = 10;
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u16 phy_link = 0;
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u16 phy_speed = 0;
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u16 phy_data = 0;
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/* Initialize speed and link to default case */
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*link_up = false;
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*speed = IXGBE_LINK_SPEED_10GB_FULL;
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/*
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* Check current speed and link status of the PHY register.
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* This is a vendor specific register and may have to
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* be changed for other copper PHYs.
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*/
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for (time_out = 0; time_out < max_time_out; time_out++) {
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udelay(10);
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status = hw->phy.ops.read_reg(hw,
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MDIO_STAT1,
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MDIO_MMD_VEND1,
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&phy_data);
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phy_link = phy_data &
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IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
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phy_speed = phy_data &
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IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
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if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
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*link_up = true;
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if (phy_speed ==
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IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
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*speed = IXGBE_LINK_SPEED_1GB_FULL;
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break;
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}
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}
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return status;
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}
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/**
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* ixgbe_setup_phy_link_tnx - Set and restart autoneg
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* @hw: pointer to hardware structure
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*
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* Restart autonegotiation and PHY and waits for completion.
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**/
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s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
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{
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s32 status = 0;
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u32 time_out;
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u32 max_time_out = 10;
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u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
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bool autoneg = false;
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ixgbe_link_speed speed;
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ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
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if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
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/* Set or unset auto-negotiation 10G advertisement */
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hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
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MDIO_MMD_AN,
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&autoneg_reg);
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autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
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if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
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autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
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hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
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MDIO_MMD_AN,
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autoneg_reg);
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}
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if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
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/* Set or unset auto-negotiation 1G advertisement */
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hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
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MDIO_MMD_AN,
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&autoneg_reg);
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autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
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if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
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autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
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hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
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MDIO_MMD_AN,
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autoneg_reg);
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}
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if (speed & IXGBE_LINK_SPEED_100_FULL) {
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/* Set or unset auto-negotiation 100M advertisement */
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hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
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MDIO_MMD_AN,
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&autoneg_reg);
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autoneg_reg &= ~ADVERTISE_100FULL;
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if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
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autoneg_reg |= ADVERTISE_100FULL;
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hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
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MDIO_MMD_AN,
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autoneg_reg);
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}
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/* Restart PHY autonegotiation and wait for completion */
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hw->phy.ops.read_reg(hw, MDIO_CTRL1,
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MDIO_MMD_AN, &autoneg_reg);
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autoneg_reg |= MDIO_AN_CTRL1_RESTART;
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hw->phy.ops.write_reg(hw, MDIO_CTRL1,
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MDIO_MMD_AN, autoneg_reg);
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/* Wait for autonegotiation to finish */
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for (time_out = 0; time_out < max_time_out; time_out++) {
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udelay(10);
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/* Restart PHY autonegotiation and wait for completion */
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status = hw->phy.ops.read_reg(hw, MDIO_STAT1,
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MDIO_MMD_AN,
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&autoneg_reg);
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autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
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if (autoneg_reg == MDIO_AN_STAT1_COMPLETE)
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break;
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}
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if (time_out == max_time_out) {
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status = IXGBE_ERR_LINK_SETUP;
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hw_dbg(hw, "ixgbe_setup_phy_link_tnx: time out");
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}
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return status;
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}
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/**
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* ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
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* @hw: pointer to hardware structure
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* @firmware_version: pointer to the PHY Firmware Version
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**/
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s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
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u16 *firmware_version)
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{
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s32 status = 0;
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status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
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MDIO_MMD_VEND1,
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firmware_version);
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return status;
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}
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/**
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* ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
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* @hw: pointer to hardware structure
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* @firmware_version: pointer to the PHY Firmware Version
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**/
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s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
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u16 *firmware_version)
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{
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s32 status = 0;
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status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
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MDIO_MMD_VEND1,
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firmware_version);
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return status;
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}
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/**
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/**
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* ixgbe_reset_phy_nl - Performs a PHY reset
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* ixgbe_reset_phy_nl - Performs a PHY reset
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* @hw: pointer to hardware structure
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* @hw: pointer to hardware structure
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@ -1476,86 +1693,6 @@ static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
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ixgbe_i2c_stop(hw);
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ixgbe_i2c_stop(hw);
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}
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}
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/**
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* ixgbe_check_phy_link_tnx - Determine link and speed status
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* @hw: pointer to hardware structure
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*
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* Reads the VS1 register to determine if link is up and the current speed for
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* the PHY.
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**/
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s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
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bool *link_up)
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{
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s32 status = 0;
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u32 time_out;
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u32 max_time_out = 10;
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u16 phy_link = 0;
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u16 phy_speed = 0;
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u16 phy_data = 0;
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/* Initialize speed and link to default case */
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*link_up = false;
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*speed = IXGBE_LINK_SPEED_10GB_FULL;
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/*
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* Check current speed and link status of the PHY register.
|
|
||||||
* This is a vendor specific register and may have to
|
|
||||||
* be changed for other copper PHYs.
|
|
||||||
*/
|
|
||||||
for (time_out = 0; time_out < max_time_out; time_out++) {
|
|
||||||
udelay(10);
|
|
||||||
status = hw->phy.ops.read_reg(hw,
|
|
||||||
IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
|
|
||||||
MDIO_MMD_VEND1,
|
|
||||||
&phy_data);
|
|
||||||
phy_link = phy_data &
|
|
||||||
IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
|
|
||||||
phy_speed = phy_data &
|
|
||||||
IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
|
|
||||||
if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
|
|
||||||
*link_up = true;
|
|
||||||
if (phy_speed ==
|
|
||||||
IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
|
|
||||||
*speed = IXGBE_LINK_SPEED_1GB_FULL;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return status;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
|
|
||||||
* @hw: pointer to hardware structure
|
|
||||||
* @firmware_version: pointer to the PHY Firmware Version
|
|
||||||
**/
|
|
||||||
s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
|
|
||||||
u16 *firmware_version)
|
|
||||||
{
|
|
||||||
s32 status = 0;
|
|
||||||
|
|
||||||
status = hw->phy.ops.read_reg(hw, TNX_FW_REV, MDIO_MMD_VEND1,
|
|
||||||
firmware_version);
|
|
||||||
|
|
||||||
return status;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
|
|
||||||
* @hw: pointer to hardware structure
|
|
||||||
* @firmware_version: pointer to the PHY Firmware Version
|
|
||||||
**/
|
|
||||||
s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
|
|
||||||
u16 *firmware_version)
|
|
||||||
{
|
|
||||||
s32 status = 0;
|
|
||||||
|
|
||||||
status = hw->phy.ops.read_reg(hw, AQ_FW_REV, MDIO_MMD_VEND1,
|
|
||||||
firmware_version);
|
|
||||||
|
|
||||||
return status;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* ixgbe_tn_check_overtemp - Checks if an overtemp occured.
|
* ixgbe_tn_check_overtemp - Checks if an overtemp occured.
|
||||||
* @hw: pointer to hardware structure
|
* @hw: pointer to hardware structure
|
||||||
|
|
|
@ -108,6 +108,7 @@ s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
|
||||||
s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
|
s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
|
||||||
ixgbe_link_speed *speed,
|
ixgbe_link_speed *speed,
|
||||||
bool *link_up);
|
bool *link_up);
|
||||||
|
s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);
|
||||||
s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
|
s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
|
||||||
u16 *firmware_version);
|
u16 *firmware_version);
|
||||||
s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
|
s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
|
||||||
|
|
|
@ -1009,6 +1009,13 @@
|
||||||
#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
|
#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
|
||||||
#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */
|
#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */
|
||||||
|
|
||||||
|
/* MII clause 22/28 definitions */
|
||||||
|
#define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */
|
||||||
|
#define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17 /* 1G XNP Transmit */
|
||||||
|
#define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000 /* full duplex, bit:14*/
|
||||||
|
#define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000 /* full duplex, bit:15*/
|
||||||
|
#define IXGBE_MII_AUTONEG_REG 0x0
|
||||||
|
|
||||||
#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
|
#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
|
||||||
#define IXGBE_MAX_PHY_ADDR 32
|
#define IXGBE_MAX_PHY_ADDR 32
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue