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interconnect changes for 5.10 

Here are the interconnect changes for the 5.10-rc1 merge window
 consisting of core changes, new drivers and cleanups.
 
 Core changes:
  - New bulk API helpers for managing multiple interconnect paths.
  - New xlate_extended() interface for parsing additional data from DT.
  - Support for sync_state().
 
 Driver changes:
  - New drivers for SM8150 and SM8250 platforms.
  - New drivers for the Qualcomm OSM and EPSS hardware blocks.
  - Per-BCM scaling factor support.
  - Misc cleanups.
 
 Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
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Merge tag 'icc-5.10-rc1' of https://git.linaro.org/people/georgi.djakov/linux into char-misc-next

Georgi writes:

interconnect changes for 5.10

Here are the interconnect changes for the 5.10-rc1 merge window
consisting of core changes, new drivers and cleanups.

Core changes:
 - New bulk API helpers for managing multiple interconnect paths.
 - New xlate_extended() interface for parsing additional data from DT.
 - Support for sync_state().

Driver changes:
 - New drivers for SM8150 and SM8250 platforms.
 - New drivers for the Qualcomm OSM and EPSS hardware blocks.
 - Per-BCM scaling factor support.
 - Misc cleanups.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>

* tag 'icc-5.10-rc1' of https://git.linaro.org/people/georgi.djakov/linux: (28 commits)
  interconnect: imx: simplify the return expression of imx_icc_unregister
  interconnect: imx: Simplify with dev_err_probe()
  interconnect: core: Simplify with dev_err_probe()
  interconnect: qcom: Use icc_sync_state
  interconnect: Add sync state support
  interconnect: Add get_bw() callback
  interconnect: qcom: osm-l3: Mark more structures const
  interconnect: qcom: Add EPSS L3 support on SM8250
  dt-bindings: interconnect: Add EPSS L3 DT binding on SM8250
  interconnect: qcom: Lay the groundwork for adding EPSS support
  interconnect: qcom: Add OSM L3 support on SM8150
  dt-bindings: interconnect: Add OSM L3 DT binding on SM8150
  interconnect: qcom: sc7180: Replace xlate with xlate_extended
  interconnect: qcom: sdm845: Replace xlate with xlate_extended
  interconnect: qcom: Implement xlate_extended() to parse tags
  dt-bindings: interconnect: Document the support of optional path tag
  interconnect: Introduce xlate_extended() callback
  interconnect: qcom: Add support for per-BCM scaling factors
  interconnect: qcom: Only wait for completion in AMC/WAKE by default
  interconnect: qcom: Support bcm-voter-specific TCS wait behavior
  ...
This commit is contained in:
Greg Kroah-Hartman 2020-09-24 15:15:11 +02:00
parent 26ed5146bd 86d6e5793e
commit 9eb29f2ed9
27 changed files with 2490 additions and 176 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
Documentation/devicetree/bindings/interconnect/interconnect.txt
View File

@ -19,7 +19,8 @@ directly.
Required properties:
- compatible : contains the interconnect provider compatible string
- #interconnect-cells : number of cells in a interconnect specifier needed to
encode the interconnect node id
encode the interconnect node id and optionally add a
path tag
Example:
@ -44,6 +45,10 @@ components it has to interact with.
Required properties:
interconnects : Pairs of phandles and interconnect provider specifier to denote
the edge source and destination ports of the interconnect path.
An optional path tag value could specified as additional argument
to both endpoints and in such cases, this information will be passed
to the interconnect framework to do aggregation based on the attached
tag.
Optional properties:
interconnect-names : List of interconnect path name strings sorted in the same
@ -62,3 +67,20 @@ Example:
interconnects = <&pnoc MASTER_SDCC_1 &bimc SLAVE_EBI_CH0>;
interconnect-names = "sdhc-mem";
};
Example with path tags:
gnoc: interconnect@17900000 {
...
interconnect-cells = <2>;
};
mnoc: interconnect@1380000 {
...
interconnect-cells = <2>;
};
cpu@0 {
...
interconnects = <&gnoc MASTER_APPSS_PROC 3 &mnoc SLAVE_EBI1 3>;
}

20
Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml
View File

@ -21,6 +21,23 @@ properties:
enum:
- qcom,bcm-voter
qcom,tcs-wait:
description: |
Optional mask of which TCSs (Triggered Command Sets) wait for completion
upon triggering. If not specified, then the AMC and WAKE sets wait for
completion. The mask bits are available in the QCOM_ICC_TAG_* defines.
The AMC TCS is triggered immediately when icc_set_bw() is called. The
WAKE/SLEEP TCSs are triggered when the RSC transitions between active and
sleep modes.
In most cases, it's necessary to wait in both the AMC and WAKE sets to
ensure resources are available before use. If a specific RSC and its use
cases can ensure sufficient delay by other means, then this can be
overridden to reduce latencies.
$ref: /schemas/types.yaml#/definitions/uint32
required:
- compatible
@ -39,7 +56,10 @@ examples:
# as defined in Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt
- |
#include <dt-bindings/interconnect/qcom,icc.h>
disp_bcm_voter: bcm_voter {
compatible = "qcom,bcm-voter";
qcom,tcs-wait = <QCOM_ICC_TAG_AMC>;
};
...

2
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
View File

@ -19,6 +19,8 @@ properties:
enum:
- qcom,sc7180-osm-l3
- qcom,sdm845-osm-l3
- qcom,sm8150-osm-l3
- qcom,sm8250-epss-l3
reg:
maxItems: 1

42
Documentation/devicetree/bindings/interconnect/qcom,sdm845.yaml → Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
View File

@ -1,16 +1,17 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,sdm845.yaml#
$id: http://devicetree.org/schemas/interconnect/qcom,rpmh.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SDM845 Network-On-Chip Interconnect
title: Qualcomm RPMh Network-On-Chip Interconnect
maintainers:
- Georgi Djakov <georgi.djakov@linaro.org>
- Odelu Kukatla <okukatla@codeaurora.org>
description: |
SDM845 interconnect providers support system bandwidth requirements through
RPMh interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
able to communicate with the BCM through the Resource State Coordinator (RSC)
associated with each execution environment. Provider nodes must point to at
@ -23,6 +24,19 @@ properties:
compatible:
enum:
- qcom,sc7180-aggre1-noc
- qcom,sc7180-aggre2-noc
- qcom,sc7180-camnoc-virt
- qcom,sc7180-compute-noc
- qcom,sc7180-config-noc
- qcom,sc7180-dc-noc
- qcom,sc7180-gem-noc
- qcom,sc7180-ipa-virt
- qcom,sc7180-mc-virt
- qcom,sc7180-mmss-noc
- qcom,sc7180-npu-noc
- qcom,sc7180-qup-virt
- qcom,sc7180-system-noc
- qcom,sdm845-aggre1-noc
- qcom,sdm845-aggre2-noc
- qcom,sdm845-config-noc
@ -31,6 +45,28 @@ properties:
- qcom,sdm845-mem-noc
- qcom,sdm845-mmss-noc
- qcom,sdm845-system-noc
- qcom,sm8150-aggre1-noc
- qcom,sm8150-aggre2-noc
- qcom,sm8150-camnoc-noc
- qcom,sm8150-compute-noc
- qcom,sm8150-config-noc
- qcom,sm8150-dc-noc
- qcom,sm8150-gem-noc
- qcom,sm8150-ipa-virt
- qcom,sm8150-mc-virt
- qcom,sm8150-mmss-noc
- qcom,sm8150-system-noc
- qcom,sm8250-aggre1-noc
- qcom,sm8250-aggre2-noc
- qcom,sm8250-compute-noc
- qcom,sm8250-config-noc
- qcom,sm8250-dc-noc
- qcom,sm8250-gem-noc
- qcom,sm8250-ipa-virt
- qcom,sm8250-mc-virt
- qcom,sm8250-mmss-noc
- qcom,sm8250-npu-noc
- qcom,sm8250-system-noc
'#interconnect-cells':
const: 1

85
Documentation/devicetree/bindings/interconnect/qcom,sc7180.yaml
View File

@ -1,85 +0,0 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,sc7180.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SC7180 Network-On-Chip Interconnect
maintainers:
- Odelu Kukatla <okukatla@codeaurora.org>
description: |
SC7180 interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
able to communicate with the BCM through the Resource State Coordinator (RSC)
associated with each execution environment. Provider nodes must point to at
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.
properties:
reg:
maxItems: 1
compatible:
enum:
- qcom,sc7180-aggre1-noc
- qcom,sc7180-aggre2-noc
- qcom,sc7180-camnoc-virt
- qcom,sc7180-compute-noc
- qcom,sc7180-config-noc
- qcom,sc7180-dc-noc
- qcom,sc7180-gem-noc
- qcom,sc7180-ipa-virt
- qcom,sc7180-mc-virt
- qcom,sc7180-mmss-noc
- qcom,sc7180-npu-noc
- qcom,sc7180-qup-virt
- qcom,sc7180-system-noc
'#interconnect-cells':
const: 1
qcom,bcm-voters:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: |
List of phandles to qcom,bcm-voter nodes that are required by
this interconnect to send RPMh commands.
qcom,bcm-voter-names:
$ref: /schemas/types.yaml#/definitions/string-array
description: |
Names for each of the qcom,bcm-voters specified.
required:
- compatible
- reg
- '#interconnect-cells'
- qcom,bcm-voters
additionalProperties: false
examples:
- |
#include <dt-bindings/interconnect/qcom,sc7180.h>
config_noc: interconnect@1500000 {
compatible = "qcom,sc7180-config-noc";
reg = <0x01500000 0x28000>;
#interconnect-cells = <1>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
system_noc: interconnect@1620000 {
compatible = "qcom,sc7180-system-noc";
reg = <0x01620000 0x17080>;
#interconnect-cells = <1>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mmss_noc: interconnect@1740000 {
compatible = "qcom,sc7180-mmss-noc";
reg = <0x01740000 0x1c100>;
#interconnect-cells = <1>;
qcom,bcm-voters = <&apps_bcm_voter>;
};

2
drivers/interconnect/Makefile
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
CFLAGS_core.o := -I$(src)
icc-core-objs := core.o
icc-core-objs := core.o bulk.o
obj-$(CONFIG_INTERCONNECT) += icc-core.o
obj-$(CONFIG_INTERCONNECT_IMX) += imx/

117
drivers/interconnect/bulk.c Normal file
View File

@ -0,0 +1,117 @@
// SPDX-License-Identifier: GPL-2.0
#include <linux/interconnect-provider.h>
#include <linux/device.h>
#include <linux/export.h>
/**
* of_icc_bulk_get() - get interconnect paths
* @dev: the device requesting the path
* @num_paths: the number of icc_bulk_data
* @paths: the table with the paths we want to get
*
* Returns 0 on success or negative errno otherwise.
*/
int __must_check of_icc_bulk_get(struct device *dev, int num_paths,
struct icc_bulk_data *paths)
{
int ret, i;
for (i = 0; i < num_paths; i++) {
paths[i].path = of_icc_get(dev, paths[i].name);
if (IS_ERR(paths[i].path)) {
ret = PTR_ERR(paths[i].path);
if (ret != -EPROBE_DEFER)
dev_err(dev, "of_icc_get() failed on path %s (%d)\n",
paths[i].name, ret);
paths[i].path = NULL;
goto err;
}
}
return 0;
err:
icc_bulk_put(i, paths);
return ret;
}
EXPORT_SYMBOL_GPL(of_icc_bulk_get);
/**
* icc_bulk_put() - put a list of interconnect paths
* @num_paths: the number of icc_bulk_data
* @paths: the icc_bulk_data table with the paths being put
*/
void icc_bulk_put(int num_paths, struct icc_bulk_data *paths)
{
while (--num_paths >= 0) {
icc_put(paths[num_paths].path);
paths[num_paths].path = NULL;
}
}
EXPORT_SYMBOL_GPL(icc_bulk_put);
/**
* icc_bulk_set() - set bandwidth to a set of paths
* @num_paths: the number of icc_bulk_data
* @paths: the icc_bulk_data table containing the paths and bandwidth
*
* Returns 0 on success or negative errno otherwise.
*/
int icc_bulk_set_bw(int num_paths, const struct icc_bulk_data *paths)
{
int ret = 0;
int i;
for (i = 0; i < num_paths; i++) {
ret = icc_set_bw(paths[i].path, paths[i].avg_bw, paths[i].peak_bw);
if (ret) {
pr_err("icc_set_bw() failed on path %s (%d)\n", paths[i].name, ret);
return ret;
}
}
return ret;
}
EXPORT_SYMBOL_GPL(icc_bulk_set_bw);
/**
* icc_bulk_enable() - enable a previously disabled set of paths
* @num_paths: the number of icc_bulk_data
* @paths: the icc_bulk_data table containing the paths and bandwidth
*
* Returns 0 on success or negative errno otherwise.
*/
int icc_bulk_enable(int num_paths, const struct icc_bulk_data *paths)
{
int ret, i;
for (i = 0; i < num_paths; i++) {
ret = icc_enable(paths[i].path);
if (ret) {
pr_err("icc_enable() failed on path %s (%d)\n", paths[i].name, ret);
goto err;
}
}
return 0;
err:
icc_bulk_disable(i, paths);
return ret;
}
EXPORT_SYMBOL_GPL(icc_bulk_enable);
/**
* icc_bulk_disable() - disable a set of interconnect paths
* @num_paths: the number of icc_bulk_data
* @paths: the icc_bulk_data table containing the paths and bandwidth
*/
void icc_bulk_disable(int num_paths, const struct icc_bulk_data *paths)
{
while (--num_paths >= 0)
icc_disable(paths[num_paths].path);
}
EXPORT_SYMBOL_GPL(icc_bulk_disable);

140
drivers/interconnect/core.c
View File

@ -26,6 +26,8 @@
static DEFINE_IDR(icc_idr);
static LIST_HEAD(icc_providers);
static int providers_count;
static bool synced_state;
static DEFINE_MUTEX(icc_lock);
static struct dentry *icc_debugfs_dir;
@ -267,6 +269,12 @@ static int aggregate_requests(struct icc_node *node)
}
p->aggregate(node, r->tag, avg_bw, peak_bw,
&node->avg_bw, &node->peak_bw);
/* during boot use the initial bandwidth as a floor value */
if (!synced_state) {
node->avg_bw = max(node->avg_bw, node->init_avg);
node->peak_bw = max(node->peak_bw, node->init_peak);
}
}
return 0;
@ -342,12 +350,13 @@ EXPORT_SYMBOL_GPL(of_icc_xlate_onecell);
* Looks for interconnect provider under the node specified by @spec and if
* found, uses xlate function of the provider to map phandle args to node.
*
* Returns a valid pointer to struct icc_node on success or ERR_PTR()
* Returns a valid pointer to struct icc_node_data on success or ERR_PTR()
* on failure.
*/
struct icc_node *of_icc_get_from_provider(struct of_phandle_args *spec)
struct icc_node_data *of_icc_get_from_provider(struct of_phandle_args *spec)
{
struct icc_node *node = ERR_PTR(-EPROBE_DEFER);
struct icc_node_data *data = NULL;
struct icc_provider *provider;
if (!spec)
@ -355,14 +364,33 @@ struct icc_node *of_icc_get_from_provider(struct of_phandle_args *spec)
mutex_lock(&icc_lock);
list_for_each_entry(provider, &icc_providers, provider_list) {
if (provider->dev->of_node == spec->np)
node = provider->xlate(spec, provider->data);
if (!IS_ERR(node))
break;
if (provider->dev->of_node == spec->np) {
if (provider->xlate_extended) {
data = provider->xlate_extended(spec, provider->data);
if (!IS_ERR(data)) {
node = data->node;
break;
}
} else {
node = provider->xlate(spec, provider->data);
if (!IS_ERR(node))
break;
}
}
}
mutex_unlock(&icc_lock);
return node;
if (IS_ERR(node))
return ERR_CAST(node);
if (!data) {
data = kzalloc(sizeof(*data), GFP_KERNEL);
if (!data)
return ERR_PTR(-ENOMEM);
data->node = node;
}
return data;
}
EXPORT_SYMBOL_GPL(of_icc_get_from_provider);
@ -409,7 +437,7 @@ EXPORT_SYMBOL_GPL(devm_of_icc_get);
struct icc_path *of_icc_get_by_index(struct device *dev, int idx)
{
struct icc_path *path;
struct icc_node *src_node, *dst_node;
struct icc_node_data *src_data, *dst_data;
struct device_node *np;
struct of_phandle_args src_args, dst_args;
int ret;
@ -447,39 +475,42 @@ struct icc_path *of_icc_get_by_index(struct device *dev, int idx)
of_node_put(dst_args.np);
src_node = of_icc_get_from_provider(&src_args);
src_data = of_icc_get_from_provider(&src_args);
if (IS_ERR(src_node)) {
if (PTR_ERR(src_node) != -EPROBE_DEFER)
dev_err(dev, "error finding src node: %ld\n",
PTR_ERR(src_node));
return ERR_CAST(src_node);
if (IS_ERR(src_data)) {
dev_err_probe(dev, PTR_ERR(src_data), "error finding src node\n");
return ERR_CAST(src_data);
}
dst_node = of_icc_get_from_provider(&dst_args);
dst_data = of_icc_get_from_provider(&dst_args);
if (IS_ERR(dst_node)) {
if (PTR_ERR(dst_node) != -EPROBE_DEFER)
dev_err(dev, "error finding dst node: %ld\n",
PTR_ERR(dst_node));
return ERR_CAST(dst_node);
if (IS_ERR(dst_data)) {
dev_err_probe(dev, PTR_ERR(dst_data), "error finding dst node\n");
kfree(src_data);
return ERR_CAST(dst_data);
}
mutex_lock(&icc_lock);
path = path_find(dev, src_node, dst_node);
path = path_find(dev, src_data->node, dst_data->node);
mutex_unlock(&icc_lock);
if (IS_ERR(path)) {
dev_err(dev, "%s: invalid path=%ld\n", __func__, PTR_ERR(path));
return path;
goto free_icc_data;
}
if (src_data->tag && src_data->tag == dst_data->tag)
icc_set_tag(path, src_data->tag);
path->name = kasprintf(GFP_KERNEL, "%s-%s",
src_node->name, dst_node->name);
src_data->node->name, dst_data->node->name);
if (!path->name) {
kfree(path);
return ERR_PTR(-ENOMEM);
path = ERR_PTR(-ENOMEM);
}
free_icc_data:
kfree(src_data);
kfree(dst_data);
return path;
}
EXPORT_SYMBOL_GPL(of_icc_get_by_index);
@ -931,6 +962,19 @@ void icc_node_add(struct icc_node *node, struct icc_provider *provider)
node->provider = provider;
list_add_tail(&node->node_list, &provider->nodes);
/* get the initial bandwidth values and sync them with hardware */
if (provider->get_bw) {
provider->get_bw(node, &node->init_avg, &node->init_peak);
} else {
node->init_avg = INT_MAX;
node->init_peak = INT_MAX;
}
node->avg_bw = node->init_avg;
node->peak_bw = node->init_peak;
provider->set(node, node);
node->avg_bw = 0;
node->peak_bw = 0;
mutex_unlock(&icc_lock);
}
EXPORT_SYMBOL_GPL(icc_node_add);
@ -981,7 +1025,7 @@ int icc_provider_add(struct icc_provider *provider)
{
if (WARN_ON(!provider->set))
return -EINVAL;
if (WARN_ON(!provider->xlate))
if (WARN_ON(!provider->xlate && !provider->xlate_extended))
return -EINVAL;
mutex_lock(&icc_lock);
@ -1026,8 +1070,54 @@ int icc_provider_del(struct icc_provider *provider)
}
EXPORT_SYMBOL_GPL(icc_provider_del);
static int of_count_icc_providers(struct device_node *np)
{
struct device_node *child;
int count = 0;
for_each_available_child_of_node(np, child) {
if (of_property_read_bool(child, "#interconnect-cells"))
count++;
count += of_count_icc_providers(child);
}
of_node_put(np);
return count;
}
void icc_sync_state(struct device *dev)
{
struct icc_provider *p;
struct icc_node *n;
static int count;
count++;
if (count < providers_count)
return;
mutex_lock(&icc_lock);
synced_state = true;
list_for_each_entry(p, &icc_providers, provider_list) {
dev_dbg(p->dev, "interconnect provider is in synced state\n");
list_for_each_entry(n, &p->nodes, node_list) {
if (n->init_avg || n->init_peak) {
aggregate_requests(n);
p->set(n, n);
}
}
}
mutex_unlock(&icc_lock);
}
EXPORT_SYMBOL_GPL(icc_sync_state);
static int __init icc_init(void)
{
struct device_node *root = of_find_node_by_path("/");
providers_count = of_count_icc_providers(root);
of_node_put(root);
icc_debugfs_dir = debugfs_create_dir("interconnect", NULL);
debugfs_create_file("interconnect_summary", 0444,
icc_debugfs_dir, NULL, &icc_summary_fops);

13
drivers/interconnect/imx/imx.c
View File

@ -184,10 +184,8 @@ static int imx_icc_register_nodes(struct icc_provider *provider,
node = imx_icc_node_add(provider, node_desc);
if (IS_ERR(node)) {
ret = PTR_ERR(node);
if (ret != -EPROBE_DEFER)
dev_err(provider->dev, "failed to add %s: %d\n",
node_desc->name, ret);
ret = dev_err_probe(provider->dev, PTR_ERR(node),
"failed to add %s\n", node_desc->name);
goto err;
}
provider_data->nodes[node->id] = node;
@ -269,15 +267,10 @@ EXPORT_SYMBOL_GPL(imx_icc_register);
int imx_icc_unregister(struct platform_device *pdev)
{
struct icc_provider *provider = platform_get_drvdata(pdev);
int ret;
imx_icc_unregister_nodes(provider);
ret = icc_provider_del(provider);
if (ret)
return ret;
return 0;
return icc_provider_del(provider);
}
EXPORT_SYMBOL_GPL(imx_icc_unregister);

20
drivers/interconnect/qcom/Kconfig
View File

@ -65,5 +65,25 @@ config INTERCONNECT_QCOM_SDM845
This is a driver for the Qualcomm Network-on-Chip on sdm845-based
platforms.
config INTERCONNECT_QCOM_SM8150
tristate "Qualcomm SM8150 interconnect driver"
depends on INTERCONNECT_QCOM
depends on (QCOM_RPMH && QCOM_COMMAND_DB && OF) || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
help
This is a driver for the Qualcomm Network-on-Chip on sm8150-based
platforms.
config INTERCONNECT_QCOM_SM8250
tristate "Qualcomm SM8250 interconnect driver"
depends on INTERCONNECT_QCOM
depends on (QCOM_RPMH && QCOM_COMMAND_DB && OF) || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
help
This is a driver for the Qualcomm Network-on-Chip on sm8250-based
platforms.
config INTERCONNECT_QCOM_SMD_RPM
tristate

4
drivers/interconnect/qcom/Makefile
View File

@ -8,6 +8,8 @@ qnoc-qcs404-objs := qcs404.o
icc-rpmh-obj := icc-rpmh.o
qnoc-sc7180-objs := sc7180.o
qnoc-sdm845-objs := sdm845.o
qnoc-sm8150-objs := sm8150.o
qnoc-sm8250-objs := sm8250.o
icc-smd-rpm-objs := smd-rpm.o
obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o
@ -18,4 +20,6 @@ obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o
obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o
obj-$(CONFIG_INTERCONNECT_QCOM_SC7180) += qnoc-sc7180.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM8150) += qnoc-sm8150.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM8250) += qnoc-sm8250.o
obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += icc-smd-rpm.o

36
drivers/interconnect/qcom/bcm-voter.c
View File

@ -27,6 +27,7 @@ static DEFINE_MUTEX(bcm_voter_lock);
* @commit_list: list containing bcms to be committed to hardware
* @ws_list: list containing bcms that have different wake/sleep votes
* @voter_node: list of bcm voters
* @tcs_wait: mask for which buckets require TCS completion
*/
struct bcm_voter {
struct device *dev;
@ -35,6 +36,7 @@ struct bcm_voter {
struct list_head commit_list;
struct list_head ws_list;
struct list_head voter_node;
u32 tcs_wait;
};
static int cmp_vcd(void *priv, struct list_head *a, struct list_head *b)
@ -83,10 +85,10 @@ static void bcm_aggregate(struct qcom_icc_bcm *bcm)
agg_peak[bucket] = max(agg_peak[bucket], temp);
}
temp = agg_avg[bucket] * 1000ULL;
temp = agg_avg[bucket] * bcm->vote_scale;
bcm->vote_x[bucket] = bcm_div(temp, bcm->aux_data.unit);
temp = agg_peak[bucket] * 1000ULL;
temp = agg_peak[bucket] * bcm->vote_scale;
bcm->vote_y[bucket] = bcm_div(temp, bcm->aux_data.unit);
}
@ -100,7 +102,7 @@ static void bcm_aggregate(struct qcom_icc_bcm *bcm)
}
static inline void tcs_cmd_gen(struct tcs_cmd *cmd, u64 vote_x, u64 vote_y,
u32 addr, bool commit)
u32 addr, bool commit, bool wait)
{
bool valid = true;
@ -125,15 +127,16 @@ static inline void tcs_cmd_gen(struct tcs_cmd *cmd, u64 vote_x, u64 vote_y,
* Set the wait for completion flag on command that need to be completed
* before the next command.
*/
cmd->wait = commit;
cmd->wait = wait;
}
static void tcs_list_gen(struct list_head *bcm_list, int bucket,
struct tcs_cmd tcs_list[MAX_BCMS],
static void tcs_list_gen(struct bcm_voter *voter, int bucket,
struct tcs_cmd tcs_list[MAX_VCD],
int n[MAX_VCD + 1])
{
struct list_head *bcm_list = &voter->commit_list;
struct qcom_icc_bcm *bcm;
bool commit;
bool commit, wait;
size_t idx = 0, batch = 0, cur_vcd_size = 0;
memset(n, 0, sizeof(int) * (MAX_VCD + 1));
@ -146,8 +149,11 @@ static void tcs_list_gen(struct list_head *bcm_list, int bucket,
commit = true;
cur_vcd_size = 0;
}
wait = commit && (voter->tcs_wait & BIT(bucket));
tcs_cmd_gen(&tcs_list[idx], bcm->vote_x[bucket],
bcm->vote_y[bucket], bcm->addr, commit);
bcm->vote_y[bucket], bcm->addr, commit, wait);
idx++;
n[batch]++;
/*
@ -272,8 +278,7 @@ int qcom_icc_bcm_voter_commit(struct bcm_voter *voter)
* Construct the command list based on a pre ordered list of BCMs
* based on VCD.
*/
tcs_list_gen(&voter->commit_list, QCOM_ICC_BUCKET_AMC, cmds, commit_idx);
tcs_list_gen(voter, QCOM_ICC_BUCKET_AMC, cmds, commit_idx);
if (!commit_idx[0])
goto out;
@ -309,7 +314,7 @@ int qcom_icc_bcm_voter_commit(struct bcm_voter *voter)
list_sort(NULL, &voter->commit_list, cmp_vcd);
tcs_list_gen(&voter->commit_list, QCOM_ICC_BUCKET_WAKE, cmds, commit_idx);
tcs_list_gen(voter, QCOM_ICC_BUCKET_WAKE, cmds, commit_idx);
ret = rpmh_write_batch(voter->dev, RPMH_WAKE_ONLY_STATE, cmds, commit_idx);
if (ret) {
@ -317,7 +322,7 @@ int qcom_icc_bcm_voter_commit(struct bcm_voter *voter)
goto out;
}
tcs_list_gen(&voter->commit_list, QCOM_ICC_BUCKET_SLEEP, cmds, commit_idx);
tcs_list_gen(voter, QCOM_ICC_BUCKET_SLEEP, cmds, commit_idx);
ret = rpmh_write_batch(voter->dev, RPMH_SLEEP_STATE, cmds, commit_idx);
if (ret) {
@ -336,6 +341,7 @@ EXPORT_SYMBOL_GPL(qcom_icc_bcm_voter_commit);
static int qcom_icc_bcm_voter_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct bcm_voter *voter;
voter = devm_kzalloc(&pdev->dev, sizeof(*voter), GFP_KERNEL);
@ -343,7 +349,11 @@ static int qcom_icc_bcm_voter_probe(struct platform_device *pdev)
return -ENOMEM;
voter->dev = &pdev->dev;
voter->np = pdev->dev.of_node;
voter->np = np;
if (of_property_read_u32(np, "qcom,tcs-wait", &voter->tcs_wait))
voter->tcs_wait = QCOM_ICC_TAG_ACTIVE_ONLY;
mutex_init(&voter->lock);
INIT_LIST_HEAD(&voter->commit_list);
INIT_LIST_HEAD(&voter->ws_list);

30
drivers/interconnect/qcom/icc-rpmh.c
View File

@ -6,6 +6,8 @@
#include <linux/interconnect.h>
#include <linux/interconnect-provider.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/slab.h>
#include "bcm-voter.h"
#include "icc-rpmh.h"
@ -92,6 +94,31 @@ int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
}
EXPORT_SYMBOL_GPL(qcom_icc_set);
struct icc_node_data *qcom_icc_xlate_extended(struct of_phandle_args *spec, void *data)
{
struct icc_node_data *ndata;
struct icc_node *node;
node = of_icc_xlate_onecell(spec, data);
if (IS_ERR(node))
return ERR_CAST(node);
ndata = kzalloc(sizeof(*ndata), GFP_KERNEL);
if (!ndata)
return ERR_PTR(-ENOMEM);
ndata->node = node;
if (spec->args_count == 2)
ndata->tag = spec->args[1];
if (spec->args_count > 2)
pr_warn("%pOF: Too many arguments, path tag is not parsed\n", spec->np);
return ndata;
}
EXPORT_SYMBOL_GPL(qcom_icc_xlate_extended);
/**
* qcom_icc_bcm_init - populates bcm aux data and connect qnodes
* @bcm: bcm to be initialized
@ -136,6 +163,9 @@ int qcom_icc_bcm_init(struct qcom_icc_bcm *bcm, struct device *dev)
INIT_LIST_HEAD(&bcm->list);
INIT_LIST_HEAD(&bcm->ws_list);
if (!bcm->vote_scale)
bcm->vote_scale = 1000;
/* Link Qnodes to their respective BCMs */
for (i = 0; i < bcm->num_nodes; i++) {
qn = bcm->nodes[i];

21
drivers/interconnect/qcom/icc-rpmh.h
View File

@ -6,6 +6,8 @@
#ifndef __DRIVERS_INTERCONNECT_QCOM_ICC_RPMH_H__
#define __DRIVERS_INTERCONNECT_QCOM_ICC_RPMH_H__
#include <dt-bindings/interconnect/qcom,icc.h>
#define to_qcom_provider(_provider) \
container_of(_provider, struct qcom_icc_provider, provider)
@ -44,22 +46,6 @@ struct bcm_db {
#define MAX_BCM_PER_NODE 3
#define MAX_VCD 10
/*
* The AMC bucket denotes constraints that are applied to hardware when
* icc_set_bw() completes, whereas the WAKE and SLEEP constraints are applied
* when the execution environment transitions between active and low power mode.
*/
#define QCOM_ICC_BUCKET_AMC 0
#define QCOM_ICC_BUCKET_WAKE 1
#define QCOM_ICC_BUCKET_SLEEP 2
#define QCOM_ICC_NUM_BUCKETS 3
#define QCOM_ICC_TAG_AMC BIT(QCOM_ICC_BUCKET_AMC)
#define QCOM_ICC_TAG_WAKE BIT(QCOM_ICC_BUCKET_WAKE)
#define QCOM_ICC_TAG_SLEEP BIT(QCOM_ICC_BUCKET_SLEEP)
#define QCOM_ICC_TAG_ACTIVE_ONLY (QCOM_ICC_TAG_AMC | QCOM_ICC_TAG_WAKE)
#define QCOM_ICC_TAG_ALWAYS (QCOM_ICC_TAG_AMC | QCOM_ICC_TAG_WAKE |\
QCOM_ICC_TAG_SLEEP)
/**
* struct qcom_icc_node - Qualcomm specific interconnect nodes
* @name: the node name used in debugfs
@ -94,6 +80,7 @@ struct qcom_icc_node {
* @addr: address offsets used when voting to RPMH
* @vote_x: aggregated threshold values, represents sum_bw when @type is bw bcm
* @vote_y: aggregated threshold values, represents peak_bw when @type is bw bcm
* @vote_scale: scaling factor for vote_x and vote_y
* @dirty: flag used to indicate whether the bcm needs to be committed
* @keepalive: flag used to indicate whether a keepalive is required
* @aux_data: auxiliary data used when calculating threshold values and
@ -109,6 +96,7 @@ struct qcom_icc_bcm {
u32 addr;
u64 vote_x[QCOM_ICC_NUM_BUCKETS];
u64 vote_y[QCOM_ICC_NUM_BUCKETS];
u64 vote_scale;
bool dirty;
bool keepalive;
struct bcm_db aux_data;
@ -143,6 +131,7 @@ struct qcom_icc_desc {
int qcom_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
u32 peak_bw, u32 *agg_avg, u32 *agg_peak);
int qcom_icc_set(struct icc_node *src, struct icc_node *dst);
struct icc_node_data *qcom_icc_xlate_extended(struct of_phandle_args *spec, void *data);
int qcom_icc_bcm_init(struct qcom_icc_bcm *bcm, struct device *dev);
void qcom_icc_pre_aggregate(struct icc_node *node);

91
drivers/interconnect/qcom/osm-l3.c
View File

@ -16,17 +16,24 @@
#include "sc7180.h"
#include "sdm845.h"
#include "sm8150.h"
#include "sm8250.h"
#define LUT_MAX_ENTRIES 40U
#define LUT_SRC GENMASK(31, 30)
#define LUT_L_VAL GENMASK(7, 0)
#define LUT_ROW_SIZE 32
#define CLK_HW_DIV 2
/* Register offsets */
/* OSM Register offsets */
#define REG_ENABLE 0x0
#define REG_FREQ_LUT 0x110
#define REG_PERF_STATE 0x920
#define OSM_LUT_ROW_SIZE 32
#define OSM_REG_FREQ_LUT 0x110
#define OSM_REG_PERF_STATE 0x920
/* EPSS Register offsets */
#define EPSS_LUT_ROW_SIZE 4
#define EPSS_REG_FREQ_LUT 0x100
#define EPSS_REG_PERF_STATE 0x320
#define OSM_L3_MAX_LINKS 1
@ -36,6 +43,7 @@
struct qcom_osm_l3_icc_provider {
void __iomem *base;
unsigned int max_state;
unsigned int reg_perf_state;
unsigned long lut_tables[LUT_MAX_ENTRIES];
struct icc_provider provider;
};
@ -57,12 +65,15 @@ struct qcom_icc_node {
};
struct qcom_icc_desc {
struct qcom_icc_node **nodes;
const struct qcom_icc_node **nodes;
size_t num_nodes;
unsigned int lut_row_size;
unsigned int reg_freq_lut;
unsigned int reg_perf_state;
};
#define DEFINE_QNODE(_name, _id, _buswidth, ...) \
static struct qcom_icc_node _name = { \
static const struct qcom_icc_node _name = { \
.name = #_name, \
.id = _id, \
.buswidth = _buswidth, \
@ -73,7 +84,7 @@ struct qcom_icc_desc {
DEFINE_QNODE(sdm845_osm_apps_l3, SDM845_MASTER_OSM_L3_APPS, 16, SDM845_SLAVE_OSM_L3);
DEFINE_QNODE(sdm845_osm_l3, SDM845_SLAVE_OSM_L3, 16);
static struct qcom_icc_node *sdm845_osm_l3_nodes[] = {
static const struct qcom_icc_node *sdm845_osm_l3_nodes[] = {
[MASTER_OSM_L3_APPS] = &sdm845_osm_apps_l3,
[SLAVE_OSM_L3] = &sdm845_osm_l3,
};
@ -81,12 +92,15 @@ static struct qcom_icc_node *sdm845_osm_l3_nodes[] = {
static const struct qcom_icc_desc sdm845_icc_osm_l3 = {
.nodes = sdm845_osm_l3_nodes,
.num_nodes = ARRAY_SIZE(sdm845_osm_l3_nodes),
.lut_row_size = OSM_LUT_ROW_SIZE,
.reg_freq_lut = OSM_REG_FREQ_LUT,
.reg_perf_state = OSM_REG_PERF_STATE,
};
DEFINE_QNODE(sc7180_osm_apps_l3, SC7180_MASTER_OSM_L3_APPS, 16, SC7180_SLAVE_OSM_L3);
DEFINE_QNODE(sc7180_osm_l3, SC7180_SLAVE_OSM_L3, 16);
static struct qcom_icc_node *sc7180_osm_l3_nodes[] = {
static const struct qcom_icc_node *sc7180_osm_l3_nodes[] = {
[MASTER_OSM_L3_APPS] = &sc7180_osm_apps_l3,
[SLAVE_OSM_L3] = &sc7180_osm_l3,
};
@ -94,13 +108,48 @@ static struct qcom_icc_node *sc7180_osm_l3_nodes[] = {
static const struct qcom_icc_desc sc7180_icc_osm_l3 = {
.nodes = sc7180_osm_l3_nodes,
.num_nodes = ARRAY_SIZE(sc7180_osm_l3_nodes),
.lut_row_size = OSM_LUT_ROW_SIZE,
.reg_freq_lut = OSM_REG_FREQ_LUT,
.reg_perf_state = OSM_REG_PERF_STATE,
};
DEFINE_QNODE(sm8150_osm_apps_l3, SM8150_MASTER_OSM_L3_APPS, 32, SM8150_SLAVE_OSM_L3);
DEFINE_QNODE(sm8150_osm_l3, SM8150_SLAVE_OSM_L3, 32);
static const struct qcom_icc_node *sm8150_osm_l3_nodes[] = {
[MASTER_OSM_L3_APPS] = &sm8150_osm_apps_l3,
[SLAVE_OSM_L3] = &sm8150_osm_l3,
};
static const struct qcom_icc_desc sm8150_icc_osm_l3 = {
.nodes = sm8150_osm_l3_nodes,
.num_nodes = ARRAY_SIZE(sm8150_osm_l3_nodes),
.lut_row_size = OSM_LUT_ROW_SIZE,
.reg_freq_lut = OSM_REG_FREQ_LUT,
.reg_perf_state = OSM_REG_PERF_STATE,
};
DEFINE_QNODE(sm8250_epss_apps_l3, SM8250_MASTER_EPSS_L3_APPS, 32, SM8250_SLAVE_EPSS_L3);
DEFINE_QNODE(sm8250_epss_l3, SM8250_SLAVE_EPSS_L3, 32);
static const struct qcom_icc_node *sm8250_epss_l3_nodes[] = {
[MASTER_EPSS_L3_APPS] = &sm8250_epss_apps_l3,
[SLAVE_EPSS_L3_SHARED] = &sm8250_epss_l3,
};
static const struct qcom_icc_desc sm8250_icc_epss_l3 = {
.nodes = sm8250_epss_l3_nodes,
.num_nodes = ARRAY_SIZE(sm8250_epss_l3_nodes),
.lut_row_size = EPSS_LUT_ROW_SIZE,
.reg_freq_lut = EPSS_REG_FREQ_LUT,
.reg_perf_state = EPSS_REG_PERF_STATE,
};
static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
{
struct qcom_osm_l3_icc_provider *qp;
struct icc_provider *provider;
struct qcom_icc_node *qn;
const struct qcom_icc_node *qn;
struct icc_node *n;
unsigned int index;
u32 agg_peak = 0;
@ -124,7 +173,7 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
break;
}
writel_relaxed(index, qp->base + REG_PERF_STATE);
writel_relaxed(index, qp->base + qp->reg_perf_state);
return 0;
}
@ -145,7 +194,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
const struct qcom_icc_desc *desc;
struct icc_onecell_data *data;
struct icc_provider *provider;
struct qcom_icc_node **qnodes;
const struct qcom_icc_node **qnodes;
struct icc_node *node;
size_t num_nodes;
struct clk *clk;
@ -179,9 +228,15 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
return -ENODEV;
}
desc = device_get_match_data(&pdev->dev);
if (!desc)
return -EINVAL;
qp->reg_perf_state = desc->reg_perf_state;
for (i = 0; i < LUT_MAX_ENTRIES; i++) {
info = readl_relaxed(qp->base + REG_FREQ_LUT +
i * LUT_ROW_SIZE);
info = readl_relaxed(qp->base + desc->reg_freq_lut +
i * desc->lut_row_size);
src = FIELD_GET(LUT_SRC, info);
lval = FIELD_GET(LUT_L_VAL, info);
if (src)
@ -200,10 +255,6 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
}
qp->max_state = i;
desc = device_get_match_data(&pdev->dev);
if (!desc)
return -EINVAL;
qnodes = desc->nodes;
num_nodes = desc->num_nodes;
@ -235,7 +286,8 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
}
node->name = qnodes[i]->name;
node->data = qnodes[i];
/* Cast away const and add it back in qcom_icc_set() */
node->data = (void *)qnodes[i];
icc_node_add(node, provider);
for (j = 0; j < qnodes[i]->num_links; j++)
@ -258,6 +310,8 @@ err:
static const struct of_device_id osm_l3_of_match[] = {
{ .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 },
{ .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 },
{ .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 },
{ .compatible = "qcom,sm8250-epss-l3", .data = &sm8250_icc_epss_l3 },
{ }
};
MODULE_DEVICE_TABLE(of, osm_l3_of_match);
@ -268,6 +322,7 @@ static struct platform_driver osm_l3_driver = {
.driver = {
.name = "osm-l3",
.of_match_table = osm_l3_of_match,
.sync_state = icc_sync_state,
},
};
module_platform_driver(osm_l3_driver);

3
drivers/interconnect/qcom/sc7180.c
View File

@ -535,7 +535,7 @@ static int qnoc_probe(struct platform_device *pdev)
provider->set = qcom_icc_set;
provider->pre_aggregate = qcom_icc_pre_aggregate;
provider->aggregate = qcom_icc_aggregate;
provider->xlate = of_icc_xlate_onecell;
provider->xlate_extended = qcom_icc_xlate_extended;
INIT_LIST_HEAD(&provider->nodes);
provider->data = data;
@ -633,6 +633,7 @@ static struct platform_driver qnoc_driver = {
.driver = {
.name = "qnoc-sc7180",
.of_match_table = qnoc_of_match,
.sync_state = icc_sync_state,
},
};
module_platform_driver(qnoc_driver);

3
drivers/interconnect/qcom/sdm845.c
View File

@ -469,7 +469,7 @@ static int qnoc_probe(struct platform_device *pdev)
provider->set = qcom_icc_set;
provider->pre_aggregate = qcom_icc_pre_aggregate;
provider->aggregate = qcom_icc_aggregate;
provider->xlate = of_icc_xlate_onecell;
provider->xlate_extended = qcom_icc_xlate_extended;
INIT_LIST_HEAD(&provider->nodes);
provider->data = data;
@ -559,6 +559,7 @@ static struct platform_driver qnoc_driver = {
.driver = {
.name = "qnoc-sdm845",
.of_match_table = qnoc_of_match,
.sync_state = icc_sync_state,
},
};
module_platform_driver(qnoc_driver);

635
drivers/interconnect/qcom/sm8150.c Normal file
View File

@ -0,0 +1,635 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
*/
#include <linux/device.h>
#include <linux/interconnect.h>
#include <linux/interconnect-provider.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <dt-bindings/interconnect/qcom,sm8150.h>
#include "bcm-voter.h"
#include "icc-rpmh.h"
#include "sm8150.h"
DEFINE_QNODE(qhm_a1noc_cfg, SM8150_MASTER_A1NOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_A1NOC);
DEFINE_QNODE(qhm_qup0, SM8150_MASTER_QUP_0, 1, 4, SM8150_A1NOC_SNOC_SLV);
DEFINE_QNODE(xm_emac, SM8150_MASTER_EMAC, 1, 8, SM8150_A1NOC_SNOC_SLV);
DEFINE_QNODE(xm_ufs_mem, SM8150_MASTER_UFS_MEM, 1, 8, SM8150_A1NOC_SNOC_SLV);
DEFINE_QNODE(xm_usb3_0, SM8150_MASTER_USB3, 1, 8, SM8150_A1NOC_SNOC_SLV);
DEFINE_QNODE(xm_usb3_1, SM8150_MASTER_USB3_1, 1, 8, SM8150_A1NOC_SNOC_SLV);
DEFINE_QNODE(qhm_a2noc_cfg, SM8150_MASTER_A2NOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_A2NOC);
DEFINE_QNODE(qhm_qdss_bam, SM8150_MASTER_QDSS_BAM, 1, 4, SM8150_A2NOC_SNOC_SLV);
DEFINE_QNODE(qhm_qspi, SM8150_MASTER_QSPI, 1, 4, SM8150_A2NOC_SNOC_SLV);
DEFINE_QNODE(qhm_qup1, SM8150_MASTER_QUP_1, 1, 4, SM8150_A2NOC_SNOC_SLV);
DEFINE_QNODE(qhm_qup2, SM8150_MASTER_QUP_2, 1, 4, SM8150_A2NOC_SNOC_SLV);
DEFINE_QNODE(qhm_sensorss_ahb, SM8150_MASTER_SENSORS_AHB, 1, 4, SM8150_A2NOC_SNOC_SLV);
DEFINE_QNODE(qhm_tsif, SM8150_MASTER_TSIF, 1, 4, SM8150_A2NOC_SNOC_SLV);
DEFINE_QNODE(qnm_cnoc, SM8150_MASTER_CNOC_A2NOC, 1, 8, SM8150_A2NOC_SNOC_SLV);
DEFINE_QNODE(qxm_crypto, SM8150_MASTER_CRYPTO_CORE_0, 1, 8, SM8150_A2NOC_SNOC_SLV);
DEFINE_QNODE(qxm_ipa, SM8150_MASTER_IPA, 1, 8, SM8150_A2NOC_SNOC_SLV);
DEFINE_QNODE(xm_pcie3_0, SM8150_MASTER_PCIE, 1, 8, SM8150_SLAVE_ANOC_PCIE_GEM_NOC);
DEFINE_QNODE(xm_pcie3_1, SM8150_MASTER_PCIE_1, 1, 8, SM8150_SLAVE_ANOC_PCIE_GEM_NOC);
DEFINE_QNODE(xm_qdss_etr, SM8150_MASTER_QDSS_ETR, 1, 8, SM8150_A2NOC_SNOC_SLV);
DEFINE_QNODE(xm_sdc2, SM8150_MASTER_SDCC_2, 1, 8, SM8150_A2NOC_SNOC_SLV);
DEFINE_QNODE(xm_sdc4, SM8150_MASTER_SDCC_4, 1, 8, SM8150_A2NOC_SNOC_SLV);
DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SM8150_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SM8150_SLAVE_CAMNOC_UNCOMP);
DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SM8150_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SM8150_SLAVE_CAMNOC_UNCOMP);
DEFINE_QNODE(qxm_camnoc_sf_uncomp, SM8150_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SM8150_SLAVE_CAMNOC_UNCOMP);
DEFINE_QNODE(qnm_npu, SM8150_MASTER_NPU, 1, 32, SM8150_SLAVE_CDSP_MEM_NOC);
DEFINE_QNODE(qhm_spdm, SM8150_MASTER_SPDM, 1, 4, SM8150_SLAVE_CNOC_A2NOC);
DEFINE_QNODE(qnm_snoc, SM8150_SNOC_CNOC_MAS, 1, 8, SM8150_SLAVE_TLMM_SOUTH, SM8150_SLAVE_CDSP_CFG, SM8150_SLAVE_SPSS_CFG, SM8150_SLAVE_CAMERA_CFG, SM8150_SLAVE_SDCC_4, SM8150_SLAVE_SDCC_2, SM8150_SLAVE_CNOC_MNOC_CFG, SM8150_SLAVE_EMAC_CFG, SM8150_SLAVE_UFS_MEM_CFG, SM8150_SLAVE_TLMM_EAST, SM8150_SLAVE_SSC_CFG, SM8150_SLAVE_SNOC_CFG, SM8150_SLAVE_NORTH_PHY_CFG, SM8150_SLAVE_QUP_0, SM8150_SLAVE_GLM, SM8150_SLAVE_PCIE_1_CFG, SM8150_SLAVE_A2NOC_CFG, SM8150_SLAVE_QDSS_CFG, SM8150_SLAVE_DISPLAY_CFG, SM8150_SLAVE_TCSR, SM8150_SLAVE_CNOC_DDRSS, SM8150_SLAVE_RBCPR_MMCX_CFG, SM8150_SLAVE_NPU_CFG, SM8150_SLAVE_PCIE_0_CFG, SM8150_SLAVE_GRAPHICS_3D_CFG, SM8150_SLAVE_VENUS_CFG, SM8150_SLAVE_TSIF, SM8150_SLAVE_IPA_CFG, SM8150_SLAVE_CLK_CTL, SM8150_SLAVE_AOP, SM8150_SLAVE_QUP_1, SM8150_SLAVE_AHB2PHY_SOUTH, SM8150_SLAVE_USB3_1, SM8150_SLAVE_SERVICE_CNOC, SM8150_SLAVE_UFS_CARD_CFG, SM8150_SLAVE_QUP_2, SM8150_SLAVE_RBCPR_CX_CFG, SM8150_SLAVE_TLMM_WEST, SM8150_SLAVE_A1NOC_CFG, SM8150_SLAVE_AOSS, SM8150_SLAVE_PRNG, SM8150_SLAVE_VSENSE_CTRL_CFG, SM8150_SLAVE_QSPI, SM8150_SLAVE_USB3, SM8150_SLAVE_SPDM_WRAPPER, SM8150_SLAVE_CRYPTO_0_CFG, SM8150_SLAVE_PIMEM_CFG, SM8150_SLAVE_TLMM_NORTH, SM8150_SLAVE_RBCPR_MX_CFG, SM8150_SLAVE_IMEM_CFG);
DEFINE_QNODE(xm_qdss_dap, SM8150_MASTER_QDSS_DAP, 1, 8, SM8150_SLAVE_TLMM_SOUTH, SM8150_SLAVE_CDSP_CFG, SM8150_SLAVE_SPSS_CFG, SM8150_SLAVE_CAMERA_CFG, SM8150_SLAVE_SDCC_4, SM8150_SLAVE_SDCC_2, SM8150_SLAVE_CNOC_MNOC_CFG, SM8150_SLAVE_EMAC_CFG, SM8150_SLAVE_UFS_MEM_CFG, SM8150_SLAVE_TLMM_EAST, SM8150_SLAVE_SSC_CFG, SM8150_SLAVE_SNOC_CFG, SM8150_SLAVE_NORTH_PHY_CFG, SM8150_SLAVE_QUP_0, SM8150_SLAVE_GLM, SM8150_SLAVE_PCIE_1_CFG, SM8150_SLAVE_A2NOC_CFG, SM8150_SLAVE_QDSS_CFG, SM8150_SLAVE_DISPLAY_CFG, SM8150_SLAVE_TCSR, SM8150_SLAVE_CNOC_DDRSS, SM8150_SLAVE_CNOC_A2NOC, SM8150_SLAVE_RBCPR_MMCX_CFG, SM8150_SLAVE_NPU_CFG, SM8150_SLAVE_PCIE_0_CFG, SM8150_SLAVE_GRAPHICS_3D_CFG, SM8150_SLAVE_VENUS_CFG, SM8150_SLAVE_TSIF, SM8150_SLAVE_IPA_CFG, SM8150_SLAVE_CLK_CTL, SM8150_SLAVE_AOP, SM8150_SLAVE_QUP_1, SM8150_SLAVE_AHB2PHY_SOUTH, SM8150_SLAVE_USB3_1, SM8150_SLAVE_SERVICE_CNOC, SM8150_SLAVE_UFS_CARD_CFG, SM8150_SLAVE_QUP_2, SM8150_SLAVE_RBCPR_CX_CFG, SM8150_SLAVE_TLMM_WEST, SM8150_SLAVE_A1NOC_CFG, SM8150_SLAVE_AOSS, SM8150_SLAVE_PRNG, SM8150_SLAVE_VSENSE_CTRL_CFG, SM8150_SLAVE_QSPI, SM8150_SLAVE_USB3, SM8150_SLAVE_SPDM_WRAPPER, SM8150_SLAVE_CRYPTO_0_CFG, SM8150_SLAVE_PIMEM_CFG, SM8150_SLAVE_TLMM_NORTH, SM8150_SLAVE_RBCPR_MX_CFG, SM8150_SLAVE_IMEM_CFG);
DEFINE_QNODE(qhm_cnoc_dc_noc, SM8150_MASTER_CNOC_DC_NOC, 1, 4, SM8150_SLAVE_GEM_NOC_CFG, SM8150_SLAVE_LLCC_CFG);
DEFINE_QNODE(acm_apps, SM8150_MASTER_AMPSS_M0, 2, 32, SM8150_SLAVE_ECC, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
DEFINE_QNODE(acm_gpu_tcu, SM8150_MASTER_GPU_TCU, 1, 8, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
DEFINE_QNODE(acm_sys_tcu, SM8150_MASTER_SYS_TCU, 1, 8, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
DEFINE_QNODE(qhm_gemnoc_cfg, SM8150_MASTER_GEM_NOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_GEM_NOC, SM8150_SLAVE_MSS_PROC_MS_MPU_CFG);
DEFINE_QNODE(qnm_cmpnoc, SM8150_MASTER_COMPUTE_NOC, 2, 32, SM8150_SLAVE_ECC, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
DEFINE_QNODE(qnm_gpu, SM8150_MASTER_GRAPHICS_3D, 2, 32, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
DEFINE_QNODE(qnm_mnoc_hf, SM8150_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8150_SLAVE_LLCC);
DEFINE_QNODE(qnm_mnoc_sf, SM8150_MASTER_MNOC_SF_MEM_NOC, 1, 32, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
DEFINE_QNODE(qnm_pcie, SM8150_MASTER_GEM_NOC_PCIE_SNOC, 1, 16, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
DEFINE_QNODE(qnm_snoc_gc, SM8150_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8150_SLAVE_LLCC);
DEFINE_QNODE(qnm_snoc_sf, SM8150_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8150_SLAVE_LLCC);
DEFINE_QNODE(qxm_ecc, SM8150_MASTER_ECC, 2, 32, SM8150_SLAVE_LLCC);
DEFINE_QNODE(ipa_core_master, SM8150_MASTER_IPA_CORE, 1, 8, SM8150_SLAVE_IPA_CORE);
DEFINE_QNODE(llcc_mc, SM8150_MASTER_LLCC, 4, 4, SM8150_SLAVE_EBI_CH0);
DEFINE_QNODE(qhm_mnoc_cfg, SM8150_MASTER_CNOC_MNOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_MNOC);
DEFINE_QNODE(qxm_camnoc_hf0, SM8150_MASTER_CAMNOC_HF0, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
DEFINE_QNODE(qxm_camnoc_hf1, SM8150_MASTER_CAMNOC_HF1, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
DEFINE_QNODE(qxm_camnoc_sf, SM8150_MASTER_CAMNOC_SF, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC);
DEFINE_QNODE(qxm_mdp0, SM8150_MASTER_MDP_PORT0, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
DEFINE_QNODE(qxm_mdp1, SM8150_MASTER_MDP_PORT1, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
DEFINE_QNODE(qxm_rot, SM8150_MASTER_ROTATOR, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC);
DEFINE_QNODE(qxm_venus0, SM8150_MASTER_VIDEO_P0, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC);
DEFINE_QNODE(qxm_venus1, SM8150_MASTER_VIDEO_P1, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC);
DEFINE_QNODE(qxm_venus_arm9, SM8150_MASTER_VIDEO_PROC, 1, 8, SM8150_SLAVE_MNOC_SF_MEM_NOC);
DEFINE_QNODE(qhm_snoc_cfg, SM8150_MASTER_SNOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_SNOC);
DEFINE_QNODE(qnm_aggre1_noc, SM8150_A1NOC_SNOC_MAS, 1, 16, SM8150_SLAVE_SNOC_GEM_NOC_SF, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS, SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_QDSS_STM);
DEFINE_QNODE(qnm_aggre2_noc, SM8150_A2NOC_SNOC_MAS, 1, 16, SM8150_SLAVE_SNOC_GEM_NOC_SF, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS, SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_PCIE_0, SM8150_SLAVE_PCIE_1, SM8150_SLAVE_TCU, SM8150_SLAVE_QDSS_STM);
DEFINE_QNODE(qnm_gemnoc, SM8150_MASTER_GEM_NOC_SNOC, 1, 8, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS, SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_TCU, SM8150_SLAVE_QDSS_STM);
DEFINE_QNODE(qxm_pimem, SM8150_MASTER_PIMEM, 1, 8, SM8150_SLAVE_SNOC_GEM_NOC_GC, SM8150_SLAVE_OCIMEM);
DEFINE_QNODE(xm_gic, SM8150_MASTER_GIC, 1, 8, SM8150_SLAVE_SNOC_GEM_NOC_GC, SM8150_SLAVE_OCIMEM);
DEFINE_QNODE(qns_a1noc_snoc, SM8150_A1NOC_SNOC_SLV, 1, 16, SM8150_A1NOC_SNOC_MAS);
DEFINE_QNODE(srvc_aggre1_noc, SM8150_SLAVE_SERVICE_A1NOC, 1, 4);
DEFINE_QNODE(qns_a2noc_snoc, SM8150_A2NOC_SNOC_SLV, 1, 16, SM8150_A2NOC_SNOC_MAS);
DEFINE_QNODE(qns_pcie_mem_noc, SM8150_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM8150_MASTER_GEM_NOC_PCIE_SNOC);
DEFINE_QNODE(srvc_aggre2_noc, SM8150_SLAVE_SERVICE_A2NOC, 1, 4);
DEFINE_QNODE(qns_camnoc_uncomp, SM8150_SLAVE_CAMNOC_UNCOMP, 1, 32);
DEFINE_QNODE(qns_cdsp_mem_noc, SM8150_SLAVE_CDSP_MEM_NOC, 2, 32, SM8150_MASTER_COMPUTE_NOC);
DEFINE_QNODE(qhs_a1_noc_cfg, SM8150_SLAVE_A1NOC_CFG, 1, 4, SM8150_MASTER_A1NOC_CFG);
DEFINE_QNODE(qhs_a2_noc_cfg, SM8150_SLAVE_A2NOC_CFG, 1, 4, SM8150_MASTER_A2NOC_CFG);
DEFINE_QNODE(qhs_ahb2phy_south, SM8150_SLAVE_AHB2PHY_SOUTH, 1, 4);
DEFINE_QNODE(qhs_aop, SM8150_SLAVE_AOP, 1, 4);
DEFINE_QNODE(qhs_aoss, SM8150_SLAVE_AOSS, 1, 4);
DEFINE_QNODE(qhs_camera_cfg, SM8150_SLAVE_CAMERA_CFG, 1, 4);
DEFINE_QNODE(qhs_clk_ctl, SM8150_SLAVE_CLK_CTL, 1, 4);
DEFINE_QNODE(qhs_compute_dsp, SM8150_SLAVE_CDSP_CFG, 1, 4);
DEFINE_QNODE(qhs_cpr_cx, SM8150_SLAVE_RBCPR_CX_CFG, 1, 4);
DEFINE_QNODE(qhs_cpr_mmcx, SM8150_SLAVE_RBCPR_MMCX_CFG, 1, 4);
DEFINE_QNODE(qhs_cpr_mx, SM8150_SLAVE_RBCPR_MX_CFG, 1, 4);
DEFINE_QNODE(qhs_crypto0_cfg, SM8150_SLAVE_CRYPTO_0_CFG, 1, 4);
DEFINE_QNODE(qhs_ddrss_cfg, SM8150_SLAVE_CNOC_DDRSS, 1, 4, SM8150_MASTER_CNOC_DC_NOC);
DEFINE_QNODE(qhs_display_cfg, SM8150_SLAVE_DISPLAY_CFG, 1, 4);
DEFINE_QNODE(qhs_emac_cfg, SM8150_SLAVE_EMAC_CFG, 1, 4);
DEFINE_QNODE(qhs_glm, SM8150_SLAVE_GLM, 1, 4);
DEFINE_QNODE(qhs_gpuss_cfg, SM8150_SLAVE_GRAPHICS_3D_CFG, 1, 8);
DEFINE_QNODE(qhs_imem_cfg, SM8150_SLAVE_IMEM_CFG, 1, 4);
DEFINE_QNODE(qhs_ipa, SM8150_SLAVE_IPA_CFG, 1, 4);
DEFINE_QNODE(qhs_mnoc_cfg, SM8150_SLAVE_CNOC_MNOC_CFG, 1, 4, SM8150_MASTER_CNOC_MNOC_CFG);
DEFINE_QNODE(qhs_npu_cfg, SM8150_SLAVE_NPU_CFG, 1, 4);
DEFINE_QNODE(qhs_pcie0_cfg, SM8150_SLAVE_PCIE_0_CFG, 1, 4);
DEFINE_QNODE(qhs_pcie1_cfg, SM8150_SLAVE_PCIE_1_CFG, 1, 4);
DEFINE_QNODE(qhs_phy_refgen_north, SM8150_SLAVE_NORTH_PHY_CFG, 1, 4);
DEFINE_QNODE(qhs_pimem_cfg, SM8150_SLAVE_PIMEM_CFG, 1, 4);
DEFINE_QNODE(qhs_prng, SM8150_SLAVE_PRNG, 1, 4);
DEFINE_QNODE(qhs_qdss_cfg, SM8150_SLAVE_QDSS_CFG, 1, 4);
DEFINE_QNODE(qhs_qspi, SM8150_SLAVE_QSPI, 1, 4);
DEFINE_QNODE(qhs_qupv3_east, SM8150_SLAVE_QUP_2, 1, 4);
DEFINE_QNODE(qhs_qupv3_north, SM8150_SLAVE_QUP_1, 1, 4);
DEFINE_QNODE(qhs_qupv3_south, SM8150_SLAVE_QUP_0, 1, 4);
DEFINE_QNODE(qhs_sdc2, SM8150_SLAVE_SDCC_2, 1, 4);
DEFINE_QNODE(qhs_sdc4, SM8150_SLAVE_SDCC_4, 1, 4);
DEFINE_QNODE(qhs_snoc_cfg, SM8150_SLAVE_SNOC_CFG, 1, 4, SM8150_MASTER_SNOC_CFG);
DEFINE_QNODE(qhs_spdm, SM8150_SLAVE_SPDM_WRAPPER, 1, 4);
DEFINE_QNODE(qhs_spss_cfg, SM8150_SLAVE_SPSS_CFG, 1, 4);
DEFINE_QNODE(qhs_ssc_cfg, SM8150_SLAVE_SSC_CFG, 1, 4);
DEFINE_QNODE(qhs_tcsr, SM8150_SLAVE_TCSR, 1, 4);
DEFINE_QNODE(qhs_tlmm_east, SM8150_SLAVE_TLMM_EAST, 1, 4);
DEFINE_QNODE(qhs_tlmm_north, SM8150_SLAVE_TLMM_NORTH, 1, 4);
DEFINE_QNODE(qhs_tlmm_south, SM8150_SLAVE_TLMM_SOUTH, 1, 4);
DEFINE_QNODE(qhs_tlmm_west, SM8150_SLAVE_TLMM_WEST, 1, 4);
DEFINE_QNODE(qhs_tsif, SM8150_SLAVE_TSIF, 1, 4);
DEFINE_QNODE(qhs_ufs_card_cfg, SM8150_SLAVE_UFS_CARD_CFG, 1, 4);
DEFINE_QNODE(qhs_ufs_mem_cfg, SM8150_SLAVE_UFS_MEM_CFG, 1, 4);
DEFINE_QNODE(qhs_usb3_0, SM8150_SLAVE_USB3, 1, 4);
DEFINE_QNODE(qhs_usb3_1, SM8150_SLAVE_USB3_1, 1, 4);
DEFINE_QNODE(qhs_venus_cfg, SM8150_SLAVE_VENUS_CFG, 1, 4);
DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8150_SLAVE_VSENSE_CTRL_CFG, 1, 4);
DEFINE_QNODE(qns_cnoc_a2noc, SM8150_SLAVE_CNOC_A2NOC, 1, 8, SM8150_MASTER_CNOC_A2NOC);
DEFINE_QNODE(srvc_cnoc, SM8150_SLAVE_SERVICE_CNOC, 1, 4);
DEFINE_QNODE(qhs_llcc, SM8150_SLAVE_LLCC_CFG, 1, 4);
DEFINE_QNODE(qhs_memnoc, SM8150_SLAVE_GEM_NOC_CFG, 1, 4, SM8150_MASTER_GEM_NOC_CFG);
DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SM8150_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4);
DEFINE_QNODE(qns_ecc, SM8150_SLAVE_ECC, 1, 32);
DEFINE_QNODE(qns_gem_noc_snoc, SM8150_SLAVE_GEM_NOC_SNOC, 1, 8, SM8150_MASTER_GEM_NOC_SNOC);
DEFINE_QNODE(qns_llcc, SM8150_SLAVE_LLCC, 4, 16, SM8150_MASTER_LLCC);
DEFINE_QNODE(srvc_gemnoc, SM8150_SLAVE_SERVICE_GEM_NOC, 1, 4);
DEFINE_QNODE(ipa_core_slave, SM8150_SLAVE_IPA_CORE, 1, 8);
DEFINE_QNODE(ebi, SM8150_SLAVE_EBI_CH0, 4, 4);
DEFINE_QNODE(qns2_mem_noc, SM8150_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SM8150_MASTER_MNOC_SF_MEM_NOC);
DEFINE_QNODE(qns_mem_noc_hf, SM8150_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8150_MASTER_MNOC_HF_MEM_NOC);
DEFINE_QNODE(srvc_mnoc, SM8150_SLAVE_SERVICE_MNOC, 1, 4);
DEFINE_QNODE(qhs_apss, SM8150_SLAVE_APPSS, 1, 8);
DEFINE_QNODE(qns_cnoc, SM8150_SNOC_CNOC_SLV, 1, 8, SM8150_SNOC_CNOC_MAS);
DEFINE_QNODE(qns_gemnoc_gc, SM8150_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8150_MASTER_SNOC_GC_MEM_NOC);
DEFINE_QNODE(qns_gemnoc_sf, SM8150_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8150_MASTER_SNOC_SF_MEM_NOC);
DEFINE_QNODE(qxs_imem, SM8150_SLAVE_OCIMEM, 1, 8);
DEFINE_QNODE(qxs_pimem, SM8150_SLAVE_PIMEM, 1, 8);
DEFINE_QNODE(srvc_snoc, SM8150_SLAVE_SERVICE_SNOC, 1, 4);
DEFINE_QNODE(xs_pcie_0, SM8150_SLAVE_PCIE_0, 1, 8);
DEFINE_QNODE(xs_pcie_1, SM8150_SLAVE_PCIE_1, 1, 8);
DEFINE_QNODE(xs_qdss_stm, SM8150_SLAVE_QDSS_STM, 1, 4);
DEFINE_QNODE(xs_sys_tcu_cfg, SM8150_SLAVE_TCU, 1, 8);
DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
DEFINE_QBCM(bcm_mm1, "MM1", false, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0, &qxm_camnoc_hf1, &qxm_mdp0, &qxm_mdp1);
DEFINE_QBCM(bcm_sh2, "SH2", false, &qns_gem_noc_snoc);
DEFINE_QBCM(bcm_mm2, "MM2", false, &qxm_camnoc_sf, &qns2_mem_noc);
DEFINE_QBCM(bcm_sh3, "SH3", false, &acm_gpu_tcu, &acm_sys_tcu);
DEFINE_QBCM(bcm_mm3, "MM3", false, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9);
DEFINE_QBCM(bcm_sh4, "SH4", false, &qnm_cmpnoc);
DEFINE_QBCM(bcm_sh5, "SH5", false, &acm_apps);
DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_mem_noc);
DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
DEFINE_QBCM(bcm_co1, "CO1", false, &qnm_npu);
DEFINE_QBCM(bcm_ip0, "IP0", false, &ipa_core_slave);
DEFINE_QBCM(bcm_cn0, "CN0", true, &qhm_spdm, &qnm_snoc, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy_south, &qhs_aop, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_emac_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_npu_cfg, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_phy_refgen_north, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qspi, &qhs_qupv3_east, &qhs_qupv3_north, &qhs_qupv3_south, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_spdm, &qhs_spss_cfg, &qhs_ssc_cfg, &qhs_tcsr, &qhs_tlmm_east, &qhs_tlmm_north, &qhs_tlmm_south, &qhs_tlmm_west, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc);
DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup0, &qhm_qup1, &qhm_qup2);
DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);
DEFINE_QBCM(bcm_sn3, "SN3", false, &srvc_aggre1_noc, &srvc_aggre2_noc, &qns_cnoc);
DEFINE_QBCM(bcm_sn4, "SN4", false, &qxs_pimem);
DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_qdss_stm);
DEFINE_QBCM(bcm_sn8, "SN8", false, &xs_pcie_0, &xs_pcie_1);
DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_aggre1_noc);
DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_aggre2_noc);
DEFINE_QBCM(bcm_sn12, "SN12", false, &qxm_pimem, &xm_gic);
DEFINE_QBCM(bcm_sn14, "SN14", false, &qns_pcie_mem_noc);
DEFINE_QBCM(bcm_sn15, "SN15", false, &qnm_gemnoc);
static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
&bcm_qup0,
&bcm_sn3,
};
static struct qcom_icc_node *aggre1_noc_nodes[] = {
[MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
[MASTER_QUP_0] = &qhm_qup0,
[MASTER_EMAC] = &xm_emac,
[MASTER_UFS_MEM] = &xm_ufs_mem,
[MASTER_USB3] = &xm_usb3_0,
[MASTER_USB3_1] = &xm_usb3_1,
[A1NOC_SNOC_SLV] = &qns_a1noc_snoc,
[SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
};
static struct qcom_icc_desc sm8150_aggre1_noc = {
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
};
static struct qcom_icc_bcm *aggre2_noc_bcms[] = {
&bcm_ce0,
&bcm_qup0,
&bcm_sn14,
&bcm_sn3,
};
static struct qcom_icc_node *aggre2_noc_nodes[] = {
[MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
[MASTER_QDSS_BAM] = &qhm_qdss_bam,
[MASTER_QSPI] = &qhm_qspi,
[MASTER_QUP_1] = &qhm_qup1,
[MASTER_QUP_2] = &qhm_qup2,
[MASTER_SENSORS_AHB] = &qhm_sensorss_ahb,
[MASTER_TSIF] = &qhm_tsif,
[MASTER_CNOC_A2NOC] = &qnm_cnoc,
[MASTER_CRYPTO_CORE_0] = &qxm_crypto,
[MASTER_IPA] = &qxm_ipa,
[MASTER_PCIE] = &xm_pcie3_0,
[MASTER_PCIE_1] = &xm_pcie3_1,
[MASTER_QDSS_ETR] = &xm_qdss_etr,
[MASTER_SDCC_2] = &xm_sdc2,
[MASTER_SDCC_4] = &xm_sdc4,
[A2NOC_SNOC_SLV] = &qns_a2noc_snoc,
[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
[SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
};
static struct qcom_icc_desc sm8150_aggre2_noc = {
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
};
static struct qcom_icc_bcm *camnoc_virt_bcms[] = {
&bcm_mm1,
};
static struct qcom_icc_node *camnoc_virt_nodes[] = {
[MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
[MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp,
[MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
[SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
};
static struct qcom_icc_desc sm8150_camnoc_virt = {
.nodes = camnoc_virt_nodes,
.num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
.bcms = camnoc_virt_bcms,
.num_bcms = ARRAY_SIZE(camnoc_virt_bcms),
};
static struct qcom_icc_bcm *compute_noc_bcms[] = {
&bcm_co0,
&bcm_co1,
};
static struct qcom_icc_node *compute_noc_nodes[] = {
[MASTER_NPU] = &qnm_npu,
[SLAVE_CDSP_MEM_NOC] = &qns_cdsp_mem_noc,
};
static struct qcom_icc_desc sm8150_compute_noc = {
.nodes = compute_noc_nodes,
.num_nodes = ARRAY_SIZE(compute_noc_nodes),
.bcms = compute_noc_bcms,
.num_bcms = ARRAY_SIZE(compute_noc_bcms),
};
static struct qcom_icc_bcm *config_noc_bcms[] = {
&bcm_cn0,
};
static struct qcom_icc_node *config_noc_nodes[] = {
[MASTER_SPDM] = &qhm_spdm,
[SNOC_CNOC_MAS] = &qnm_snoc,
[MASTER_QDSS_DAP] = &xm_qdss_dap,
[SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
[SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
[SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy_south,
[SLAVE_AOP] = &qhs_aop,
[SLAVE_AOSS] = &qhs_aoss,
[SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
[SLAVE_CLK_CTL] = &qhs_clk_ctl,
[SLAVE_CDSP_CFG] = &qhs_compute_dsp,
[SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
[SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
[SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
[SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
[SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
[SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
[SLAVE_EMAC_CFG] = &qhs_emac_cfg,
[SLAVE_GLM] = &qhs_glm,
[SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg,
[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
[SLAVE_IPA_CFG] = &qhs_ipa,
[SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
[SLAVE_NPU_CFG] = &qhs_npu_cfg,
[SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
[SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
[SLAVE_NORTH_PHY_CFG] = &qhs_phy_refgen_north,
[SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
[SLAVE_PRNG] = &qhs_prng,
[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
[SLAVE_QSPI] = &qhs_qspi,
[SLAVE_QUP_2] = &qhs_qupv3_east,
[SLAVE_QUP_1] = &qhs_qupv3_north,
[SLAVE_QUP_0] = &qhs_qupv3_south,
[SLAVE_SDCC_2] = &qhs_sdc2,
[SLAVE_SDCC_4] = &qhs_sdc4,
[SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
[SLAVE_SPDM_WRAPPER] = &qhs_spdm,
[SLAVE_SPSS_CFG] = &qhs_spss_cfg,
[SLAVE_SSC_CFG] = &qhs_ssc_cfg,
[SLAVE_TCSR] = &qhs_tcsr,
[SLAVE_TLMM_EAST] = &qhs_tlmm_east,
[SLAVE_TLMM_NORTH] = &qhs_tlmm_north,
[SLAVE_TLMM_SOUTH] = &qhs_tlmm_south,
[SLAVE_TLMM_WEST] = &qhs_tlmm_west,
[SLAVE_TSIF] = &qhs_tsif,
[SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
[SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
[SLAVE_USB3] = &qhs_usb3_0,
[SLAVE_USB3_1] = &qhs_usb3_1,
[SLAVE_VENUS_CFG] = &qhs_venus_cfg,
[SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
[SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
[SLAVE_SERVICE_CNOC] = &srvc_cnoc,
};
static struct qcom_icc_desc sm8150_config_noc = {
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
.num_bcms = ARRAY_SIZE(config_noc_bcms),
};
static struct qcom_icc_bcm *dc_noc_bcms[] = {
};
static struct qcom_icc_node *dc_noc_nodes[] = {
[MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc,
[SLAVE_LLCC_CFG] = &qhs_llcc,
[SLAVE_GEM_NOC_CFG] = &qhs_memnoc,
};
static struct qcom_icc_desc sm8150_dc_noc = {
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
.bcms = dc_noc_bcms,
.num_bcms = ARRAY_SIZE(dc_noc_bcms),
};
static struct qcom_icc_bcm *gem_noc_bcms[] = {
&bcm_sh0,
&bcm_sh2,
&bcm_sh3,
&bcm_sh4,
&bcm_sh5,
};
static struct qcom_icc_node *gem_noc_nodes[] = {
[MASTER_AMPSS_M0] = &acm_apps,
[MASTER_GPU_TCU] = &acm_gpu_tcu,
[MASTER_SYS_TCU] = &acm_sys_tcu,
[MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg,
[MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
[MASTER_GRAPHICS_3D] = &qnm_gpu,
[MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
[MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_pcie,
[MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
[MASTER_ECC] = &qxm_ecc,
[SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
[SLAVE_ECC] = &qns_ecc,
[SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc,
[SLAVE_LLCC] = &qns_llcc,
[SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc,
};
static struct qcom_icc_desc sm8150_gem_noc = {
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
};
static struct qcom_icc_bcm *ipa_virt_bcms[] = {
&bcm_ip0,
};
static struct qcom_icc_node *ipa_virt_nodes[] = {
[MASTER_IPA_CORE] = &ipa_core_master,
[SLAVE_IPA_CORE] = &ipa_core_slave,
};
static struct qcom_icc_desc sm8150_ipa_virt = {
.nodes = ipa_virt_nodes,
.num_nodes = ARRAY_SIZE(ipa_virt_nodes),
.bcms = ipa_virt_bcms,
.num_bcms = ARRAY_SIZE(ipa_virt_bcms),
};
static struct qcom_icc_bcm *mc_virt_bcms[] = {
&bcm_acv,
&bcm_mc0,
};
static struct qcom_icc_node *mc_virt_nodes[] = {
[MASTER_LLCC] = &llcc_mc,
[SLAVE_EBI_CH0] = &ebi,
};
static struct qcom_icc_desc sm8150_mc_virt = {
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
.num_bcms = ARRAY_SIZE(mc_virt_bcms),
};
static struct qcom_icc_bcm *mmss_noc_bcms[] = {
&bcm_mm0,
&bcm_mm1,
&bcm_mm2,
&bcm_mm3,
};
static struct qcom_icc_node *mmss_noc_nodes[] = {
[MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
[MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0,
[MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1,
[MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
[MASTER_MDP_PORT0] = &qxm_mdp0,
[MASTER_MDP_PORT1] = &qxm_mdp1,
[MASTER_ROTATOR] = &qxm_rot,
[MASTER_VIDEO_P0] = &qxm_venus0,
[MASTER_VIDEO_P1] = &qxm_venus1,
[MASTER_VIDEO_PROC] = &qxm_venus_arm9,
[SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc,
[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
};
static struct qcom_icc_desc sm8150_mmss_noc = {
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
};
static struct qcom_icc_bcm *system_noc_bcms[] = {
&bcm_sn0,
&bcm_sn1,
&bcm_sn11,
&bcm_sn12,
&bcm_sn15,
&bcm_sn2,
&bcm_sn3,
&bcm_sn4,
&bcm_sn5,
&bcm_sn8,
&bcm_sn9,
};
static struct qcom_icc_node *system_noc_nodes[] = {
[MASTER_SNOC_CFG] = &qhm_snoc_cfg,
[A1NOC_SNOC_MAS] = &qnm_aggre1_noc,
[A2NOC_SNOC_MAS] = &qnm_aggre2_noc,
[MASTER_GEM_NOC_SNOC] = &qnm_gemnoc,
[MASTER_PIMEM] = &qxm_pimem,
[MASTER_GIC] = &xm_gic,
[SLAVE_APPSS] = &qhs_apss,
[SNOC_CNOC_SLV] = &qns_cnoc,
[SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
[SLAVE_OCIMEM] = &qxs_imem,
[SLAVE_PIMEM] = &qxs_pimem,
[SLAVE_SERVICE_SNOC] = &srvc_snoc,
[SLAVE_PCIE_0] = &xs_pcie_0,
[SLAVE_PCIE_1] = &xs_pcie_1,
[SLAVE_QDSS_STM] = &xs_qdss_stm,
[SLAVE_TCU] = &xs_sys_tcu_cfg,
};
static struct qcom_icc_desc sm8150_system_noc = {
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
.num_bcms = ARRAY_SIZE(system_noc_bcms),
};
static int qnoc_probe(struct platform_device *pdev)
{
const struct qcom_icc_desc *desc;
struct icc_onecell_data *data;
struct icc_provider *provider;
struct qcom_icc_node **qnodes;
struct qcom_icc_provider *qp;
struct icc_node *node;
size_t num_nodes, i;
int ret;
desc = device_get_match_data(&pdev->dev);
if (!desc)
return -EINVAL;
qnodes = desc->nodes;
num_nodes = desc->num_nodes;
qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
if (!qp)
return -ENOMEM;
data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
if (!data)
return -ENOMEM;
provider = &qp->provider;
provider->dev = &pdev->dev;
provider->set = qcom_icc_set;
provider->pre_aggregate = qcom_icc_pre_aggregate;
provider->aggregate = qcom_icc_aggregate;
provider->xlate = of_icc_xlate_onecell;
INIT_LIST_HEAD(&provider->nodes);
provider->data = data;
qp->dev = &pdev->dev;
qp->bcms = desc->bcms;
qp->num_bcms = desc->num_bcms;
qp->voter = of_bcm_voter_get(qp->dev, NULL);
if (IS_ERR(qp->voter))
return PTR_ERR(qp->voter);
ret = icc_provider_add(provider);
if (ret) {
dev_err(&pdev->dev, "error adding interconnect provider\n");
return ret;
}
for (i = 0; i < num_nodes; i++) {
size_t j;
if (!qnodes[i])
continue;
node = icc_node_create(qnodes[i]->id);
if (IS_ERR(node)) {
ret = PTR_ERR(node);
goto err;
}
node->name = qnodes[i]->name;
node->data = qnodes[i];
icc_node_add(node, provider);
for (j = 0; j < qnodes[i]->num_links; j++)
icc_link_create(node, qnodes[i]->links[j]);
data->nodes[i] = node;
}
data->num_nodes = num_nodes;
for (i = 0; i < qp->num_bcms; i++)
qcom_icc_bcm_init(qp->bcms[i], &pdev->dev);
platform_set_drvdata(pdev, qp);
return 0;
err:
icc_nodes_remove(provider);
icc_provider_del(provider);
return ret;
}
static int qnoc_remove(struct platform_device *pdev)
{
struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
icc_nodes_remove(&qp->provider);
return icc_provider_del(&qp->provider);
}
static const struct of_device_id qnoc_of_match[] = {
{ .compatible = "qcom,sm8150-aggre1-noc",
.data = &sm8150_aggre1_noc},
{ .compatible = "qcom,sm8150-aggre2-noc",
.data = &sm8150_aggre2_noc},
{ .compatible = "qcom,sm8150-camnoc-virt",
.data = &sm8150_camnoc_virt},
{ .compatible = "qcom,sm8150-compute-noc",
.data = &sm8150_compute_noc},
{ .compatible = "qcom,sm8150-config-noc",
.data = &sm8150_config_noc},
{ .compatible = "qcom,sm8150-dc-noc",
.data = &sm8150_dc_noc},
{ .compatible = "qcom,sm8150-gem-noc",
.data = &sm8150_gem_noc},
{ .compatible = "qcom,sm8150-ipa-virt",
.data = &sm8150_ipa_virt},
{ .compatible = "qcom,sm8150-mc-virt",
.data = &sm8150_mc_virt},
{ .compatible = "qcom,sm8150-mmss-noc",
.data = &sm8150_mmss_noc},
{ .compatible = "qcom,sm8150-system-noc",
.data = &sm8150_system_noc},
{ }
};
MODULE_DEVICE_TABLE(of, qnoc_of_match);
static struct platform_driver qnoc_driver = {
.probe = qnoc_probe,
.remove = qnoc_remove,
.driver = {
.name = "qnoc-sm8150",
.of_match_table = qnoc_of_match,
},
};
module_platform_driver(qnoc_driver);
MODULE_DESCRIPTION("Qualcomm SM8150 NoC driver");
MODULE_LICENSE("GPL v2");

154
drivers/interconnect/qcom/sm8150.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Qualcomm #define SM8250 interconnect IDs
*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8150_H
#define __DRIVERS_INTERCONNECT_QCOM_SM8150_H
#define SM8150_A1NOC_SNOC_MAS 0
#define SM8150_A1NOC_SNOC_SLV 1
#define SM8150_A2NOC_SNOC_MAS 2
#define SM8150_A2NOC_SNOC_SLV 3
#define SM8150_MASTER_A1NOC_CFG 4
#define SM8150_MASTER_A2NOC_CFG 5
#define SM8150_MASTER_AMPSS_M0 6
#define SM8150_MASTER_CAMNOC_HF0 7
#define SM8150_MASTER_CAMNOC_HF0_UNCOMP 8
#define SM8150_MASTER_CAMNOC_HF1 9
#define SM8150_MASTER_CAMNOC_HF1_UNCOMP 10
#define SM8150_MASTER_CAMNOC_SF 11
#define SM8150_MASTER_CAMNOC_SF_UNCOMP 12
#define SM8150_MASTER_CNOC_A2NOC 13
#define SM8150_MASTER_CNOC_DC_NOC 14
#define SM8150_MASTER_CNOC_MNOC_CFG 15
#define SM8150_MASTER_COMPUTE_NOC 16
#define SM8150_MASTER_CRYPTO_CORE_0 17
#define SM8150_MASTER_ECC 18
#define SM8150_MASTER_EMAC 19
#define SM8150_MASTER_GEM_NOC_CFG 20
#define SM8150_MASTER_GEM_NOC_PCIE_SNOC 21
#define SM8150_MASTER_GEM_NOC_SNOC 22
#define SM8150_MASTER_GIC 23
#define SM8150_MASTER_GPU_TCU 24
#define SM8150_MASTER_GRAPHICS_3D 25
#define SM8150_MASTER_IPA 26
#define SM8150_MASTER_IPA_CORE 27
#define SM8150_MASTER_LLCC 28
#define SM8150_MASTER_MDP_PORT0 29
#define SM8150_MASTER_MDP_PORT1 30
#define SM8150_MASTER_MNOC_HF_MEM_NOC 31
#define SM8150_MASTER_MNOC_SF_MEM_NOC 32
#define SM8150_MASTER_NPU 33
#define SM8150_MASTER_PCIE 34
#define SM8150_MASTER_PCIE_1 35
#define SM8150_MASTER_PIMEM 36
#define SM8150_MASTER_QDSS_BAM 37
#define SM8150_MASTER_QDSS_DAP 38
#define SM8150_MASTER_QDSS_ETR 39
#define SM8150_MASTER_QSPI 40
#define SM8150_MASTER_QUP_0 41
#define SM8150_MASTER_QUP_1 42
#define SM8150_MASTER_QUP_2 43
#define SM8150_MASTER_ROTATOR 44
#define SM8150_MASTER_SDCC_2 45
#define SM8150_MASTER_SDCC_4 46
#define SM8150_MASTER_SENSORS_AHB 47
#define SM8150_MASTER_SNOC_CFG 48
#define SM8150_MASTER_SNOC_GC_MEM_NOC 49
#define SM8150_MASTER_SNOC_SF_MEM_NOC 50
#define SM8150_MASTER_SPDM 51
#define SM8150_MASTER_SYS_TCU 52
#define SM8150_MASTER_TSIF 53
#define SM8150_MASTER_UFS_MEM 54
#define SM8150_MASTER_USB3 55
#define SM8150_MASTER_USB3_1 56
#define SM8150_MASTER_VIDEO_P0 57
#define SM8150_MASTER_VIDEO_P1 58
#define SM8150_MASTER_VIDEO_PROC 59
#define SM8150_SLAVE_A1NOC_CFG 60
#define SM8150_SLAVE_A2NOC_CFG 61
#define SM8150_SLAVE_AHB2PHY_SOUTH 62
#define SM8150_SLAVE_ANOC_PCIE_GEM_NOC 63
#define SM8150_SLAVE_AOP 64
#define SM8150_SLAVE_AOSS 65
#define SM8150_SLAVE_APPSS 66
#define SM8150_SLAVE_CAMERA_CFG 67
#define SM8150_SLAVE_CAMNOC_UNCOMP 68
#define SM8150_SLAVE_CDSP_CFG 69
#define SM8150_SLAVE_CDSP_MEM_NOC 70
#define SM8150_SLAVE_CLK_CTL 71
#define SM8150_SLAVE_CNOC_A2NOC 72
#define SM8150_SLAVE_CNOC_DDRSS 73
#define SM8150_SLAVE_CNOC_MNOC_CFG 74
#define SM8150_SLAVE_CRYPTO_0_CFG 75
#define SM8150_SLAVE_DISPLAY_CFG 76
#define SM8150_SLAVE_EBI_CH0 77
#define SM8150_SLAVE_ECC 78
#define SM8150_SLAVE_EMAC_CFG 79
#define SM8150_SLAVE_GEM_NOC_CFG 80
#define SM8150_SLAVE_GEM_NOC_SNOC 81
#define SM8150_SLAVE_GLM 82
#define SM8150_SLAVE_GRAPHICS_3D_CFG 83
#define SM8150_SLAVE_IMEM_CFG 84
#define SM8150_SLAVE_IPA_CFG 85
#define SM8150_SLAVE_IPA_CORE 86
#define SM8150_SLAVE_LLCC 87
#define SM8150_SLAVE_LLCC_CFG 88
#define SM8150_SLAVE_MNOC_HF_MEM_NOC 89
#define SM8150_SLAVE_MNOC_SF_MEM_NOC 90
#define SM8150_SLAVE_MSS_PROC_MS_MPU_CFG 91
#define SM8150_SLAVE_NORTH_PHY_CFG 92
#define SM8150_SLAVE_NPU_CFG 93
#define SM8150_SLAVE_OCIMEM 94
#define SM8150_SLAVE_PCIE_0 95
#define SM8150_SLAVE_PCIE_0_CFG 96
#define SM8150_SLAVE_PCIE_1 97
#define SM8150_SLAVE_PCIE_1_CFG 98
#define SM8150_SLAVE_PIMEM 99
#define SM8150_SLAVE_PIMEM_CFG 100
#define SM8150_SLAVE_PRNG 101
#define SM8150_SLAVE_QDSS_CFG 102
#define SM8150_SLAVE_QDSS_STM 103
#define SM8150_SLAVE_QSPI 104
#define SM8150_SLAVE_QUP_0 105
#define SM8150_SLAVE_QUP_1 106
#define SM8150_SLAVE_QUP_2 107
#define SM8150_SLAVE_RBCPR_CX_CFG 108
#define SM8150_SLAVE_RBCPR_MMCX_CFG 109
#define SM8150_SLAVE_RBCPR_MX_CFG 110
#define SM8150_SLAVE_SDCC_2 111
#define SM8150_SLAVE_SDCC_4 112
#define SM8150_SLAVE_SERVICE_A1NOC 113
#define SM8150_SLAVE_SERVICE_A2NOC 114
#define SM8150_SLAVE_SERVICE_CNOC 115
#define SM8150_SLAVE_SERVICE_GEM_NOC 116
#define SM8150_SLAVE_SERVICE_MNOC 117
#define SM8150_SLAVE_SERVICE_SNOC 118
#define SM8150_SLAVE_SNOC_CFG 119
#define SM8150_SLAVE_SNOC_GEM_NOC_GC 120
#define SM8150_SLAVE_SNOC_GEM_NOC_SF 121
#define SM8150_SLAVE_SPDM_WRAPPER 122
#define SM8150_SLAVE_SPSS_CFG 123
#define SM8150_SLAVE_SSC_CFG 124
#define SM8150_SLAVE_TCSR 125
#define SM8150_SLAVE_TCU 126
#define SM8150_SLAVE_TLMM_EAST 127
#define SM8150_SLAVE_TLMM_NORTH 128
#define SM8150_SLAVE_TLMM_SOUTH 129
#define SM8150_SLAVE_TLMM_WEST 130
#define SM8150_SLAVE_TSIF 131
#define SM8150_SLAVE_UFS_CARD_CFG 132
#define SM8150_SLAVE_UFS_MEM_CFG 133
#define SM8150_SLAVE_USB3 134
#define SM8150_SLAVE_USB3_1 135
#define SM8150_SLAVE_VENUS_CFG 136
#define SM8150_SLAVE_VSENSE_CTRL_CFG 137
#define SM8150_SNOC_CNOC_MAS 138
#define SM8150_SNOC_CNOC_SLV 139
#define SM8150_MASTER_OSM_L3_APPS 140
#define SM8150_SLAVE_OSM_L3 141
#endif

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@ -0,0 +1,651 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
*/
#include <linux/device.h>
#include <linux/interconnect.h>
#include <linux/interconnect-provider.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <dt-bindings/interconnect/qcom,sm8250.h>
#include "bcm-voter.h"
#include "icc-rpmh.h"
#include "sm8250.h"
DEFINE_QNODE(qhm_a1noc_cfg, SM8250_MASTER_A1NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_A1NOC);
DEFINE_QNODE(qhm_qspi, SM8250_MASTER_QSPI_0, 1, 4, SM8250_A1NOC_SNOC_SLV);
DEFINE_QNODE(qhm_qup1, SM8250_MASTER_QUP_1, 1, 4, SM8250_A1NOC_SNOC_SLV);
DEFINE_QNODE(qhm_qup2, SM8250_MASTER_QUP_2, 1, 4, SM8250_A1NOC_SNOC_SLV);
DEFINE_QNODE(qhm_tsif, SM8250_MASTER_TSIF, 1, 4, SM8250_A1NOC_SNOC_SLV);
DEFINE_QNODE(xm_pcie3_modem, SM8250_MASTER_PCIE_2, 1, 8, SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1);
DEFINE_QNODE(xm_sdc4, SM8250_MASTER_SDCC_4, 1, 8, SM8250_A1NOC_SNOC_SLV);
DEFINE_QNODE(xm_ufs_mem, SM8250_MASTER_UFS_MEM, 1, 8, SM8250_A1NOC_SNOC_SLV);
DEFINE_QNODE(xm_usb3_0, SM8250_MASTER_USB3, 1, 8, SM8250_A1NOC_SNOC_SLV);
DEFINE_QNODE(xm_usb3_1, SM8250_MASTER_USB3_1, 1, 8, SM8250_A1NOC_SNOC_SLV);
DEFINE_QNODE(qhm_a2noc_cfg, SM8250_MASTER_A2NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_A2NOC);
DEFINE_QNODE(qhm_qdss_bam, SM8250_MASTER_QDSS_BAM, 1, 4, SM8250_A2NOC_SNOC_SLV);
DEFINE_QNODE(qhm_qup0, SM8250_MASTER_QUP_0, 1, 4, SM8250_A2NOC_SNOC_SLV);
DEFINE_QNODE(qnm_cnoc, SM8250_MASTER_CNOC_A2NOC, 1, 8, SM8250_A2NOC_SNOC_SLV);
DEFINE_QNODE(qxm_crypto, SM8250_MASTER_CRYPTO_CORE_0, 1, 8, SM8250_A2NOC_SNOC_SLV);
DEFINE_QNODE(qxm_ipa, SM8250_MASTER_IPA, 1, 8, SM8250_A2NOC_SNOC_SLV);
DEFINE_QNODE(xm_pcie3_0, SM8250_MASTER_PCIE, 1, 8, SM8250_SLAVE_ANOC_PCIE_GEM_NOC);
DEFINE_QNODE(xm_pcie3_1, SM8250_MASTER_PCIE_1, 1, 8, SM8250_SLAVE_ANOC_PCIE_GEM_NOC);
DEFINE_QNODE(xm_qdss_etr, SM8250_MASTER_QDSS_ETR, 1, 8, SM8250_A2NOC_SNOC_SLV);
DEFINE_QNODE(xm_sdc2, SM8250_MASTER_SDCC_2, 1, 8, SM8250_A2NOC_SNOC_SLV);
DEFINE_QNODE(xm_ufs_card, SM8250_MASTER_UFS_CARD, 1, 8, SM8250_A2NOC_SNOC_SLV);
DEFINE_QNODE(qnm_npu, SM8250_MASTER_NPU, 2, 32, SM8250_SLAVE_CDSP_MEM_NOC);
DEFINE_QNODE(qnm_snoc, SM8250_SNOC_CNOC_MAS, 1, 8, SM8250_SLAVE_CDSP_CFG, SM8250_SLAVE_CAMERA_CFG, SM8250_SLAVE_TLMM_SOUTH, SM8250_SLAVE_TLMM_NORTH, SM8250_SLAVE_SDCC_4, SM8250_SLAVE_TLMM_WEST, SM8250_SLAVE_SDCC_2, SM8250_SLAVE_CNOC_MNOC_CFG, SM8250_SLAVE_UFS_MEM_CFG, SM8250_SLAVE_SNOC_CFG, SM8250_SLAVE_PDM, SM8250_SLAVE_CX_RDPM, SM8250_SLAVE_PCIE_1_CFG, SM8250_SLAVE_A2NOC_CFG, SM8250_SLAVE_QDSS_CFG, SM8250_SLAVE_DISPLAY_CFG, SM8250_SLAVE_PCIE_2_CFG, SM8250_SLAVE_TCSR, SM8250_SLAVE_DCC_CFG, SM8250_SLAVE_CNOC_DDRSS, SM8250_SLAVE_IPC_ROUTER_CFG, SM8250_SLAVE_PCIE_0_CFG, SM8250_SLAVE_RBCPR_MMCX_CFG, SM8250_SLAVE_NPU_CFG, SM8250_SLAVE_AHB2PHY_SOUTH, SM8250_SLAVE_AHB2PHY_NORTH, SM8250_SLAVE_GRAPHICS_3D_CFG, SM8250_SLAVE_VENUS_CFG, SM8250_SLAVE_TSIF, SM8250_SLAVE_IPA_CFG, SM8250_SLAVE_IMEM_CFG, SM8250_SLAVE_USB3, SM8250_SLAVE_SERVICE_CNOC, SM8250_SLAVE_UFS_CARD_CFG, SM8250_SLAVE_USB3_1, SM8250_SLAVE_LPASS, SM8250_SLAVE_RBCPR_CX_CFG, SM8250_SLAVE_A1NOC_CFG, SM8250_SLAVE_AOSS, SM8250_SLAVE_PRNG, SM8250_SLAVE_VSENSE_CTRL_CFG, SM8250_SLAVE_QSPI_0, SM8250_SLAVE_CRYPTO_0_CFG, SM8250_SLAVE_PIMEM_CFG, SM8250_SLAVE_RBCPR_MX_CFG, SM8250_SLAVE_QUP_0, SM8250_SLAVE_QUP_1, SM8250_SLAVE_QUP_2, SM8250_SLAVE_CLK_CTL);
DEFINE_QNODE(xm_qdss_dap, SM8250_MASTER_QDSS_DAP, 1, 8, SM8250_SLAVE_CDSP_CFG, SM8250_SLAVE_CAMERA_CFG, SM8250_SLAVE_TLMM_SOUTH, SM8250_SLAVE_TLMM_NORTH, SM8250_SLAVE_SDCC_4, SM8250_SLAVE_TLMM_WEST, SM8250_SLAVE_SDCC_2, SM8250_SLAVE_CNOC_MNOC_CFG, SM8250_SLAVE_UFS_MEM_CFG, SM8250_SLAVE_SNOC_CFG, SM8250_SLAVE_PDM, SM8250_SLAVE_CX_RDPM, SM8250_SLAVE_PCIE_1_CFG, SM8250_SLAVE_A2NOC_CFG, SM8250_SLAVE_QDSS_CFG, SM8250_SLAVE_DISPLAY_CFG, SM8250_SLAVE_PCIE_2_CFG, SM8250_SLAVE_TCSR, SM8250_SLAVE_DCC_CFG, SM8250_SLAVE_CNOC_DDRSS, SM8250_SLAVE_IPC_ROUTER_CFG, SM8250_SLAVE_CNOC_A2NOC, SM8250_SLAVE_PCIE_0_CFG, SM8250_SLAVE_RBCPR_MMCX_CFG, SM8250_SLAVE_NPU_CFG, SM8250_SLAVE_AHB2PHY_SOUTH, SM8250_SLAVE_AHB2PHY_NORTH, SM8250_SLAVE_GRAPHICS_3D_CFG, SM8250_SLAVE_VENUS_CFG, SM8250_SLAVE_TSIF, SM8250_SLAVE_IPA_CFG, SM8250_SLAVE_IMEM_CFG, SM8250_SLAVE_USB3, SM8250_SLAVE_SERVICE_CNOC, SM8250_SLAVE_UFS_CARD_CFG, SM8250_SLAVE_USB3_1, SM8250_SLAVE_LPASS, SM8250_SLAVE_RBCPR_CX_CFG, SM8250_SLAVE_A1NOC_CFG, SM8250_SLAVE_AOSS, SM8250_SLAVE_PRNG, SM8250_SLAVE_VSENSE_CTRL_CFG, SM8250_SLAVE_QSPI_0, SM8250_SLAVE_CRYPTO_0_CFG, SM8250_SLAVE_PIMEM_CFG, SM8250_SLAVE_RBCPR_MX_CFG, SM8250_SLAVE_QUP_0, SM8250_SLAVE_QUP_1, SM8250_SLAVE_QUP_2, SM8250_SLAVE_CLK_CTL);
DEFINE_QNODE(qhm_cnoc_dc_noc, SM8250_MASTER_CNOC_DC_NOC, 1, 4, SM8250_SLAVE_GEM_NOC_CFG, SM8250_SLAVE_LLCC_CFG);
DEFINE_QNODE(alm_gpu_tcu, SM8250_MASTER_GPU_TCU, 1, 8, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
DEFINE_QNODE(alm_sys_tcu, SM8250_MASTER_SYS_TCU, 1, 8, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
DEFINE_QNODE(chm_apps, SM8250_MASTER_AMPSS_M0, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC, SM8250_SLAVE_MEM_NOC_PCIE_SNOC);
DEFINE_QNODE(qhm_gemnoc_cfg, SM8250_MASTER_GEM_NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_GEM_NOC_2, SM8250_SLAVE_SERVICE_GEM_NOC_1, SM8250_SLAVE_SERVICE_GEM_NOC);
DEFINE_QNODE(qnm_cmpnoc, SM8250_MASTER_COMPUTE_NOC, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
DEFINE_QNODE(qnm_gpu, SM8250_MASTER_GRAPHICS_3D, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
DEFINE_QNODE(qnm_mnoc_hf, SM8250_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8250_SLAVE_LLCC);
DEFINE_QNODE(qnm_mnoc_sf, SM8250_MASTER_MNOC_SF_MEM_NOC, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
DEFINE_QNODE(qnm_pcie, SM8250_MASTER_ANOC_PCIE_GEM_NOC, 1, 16, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
DEFINE_QNODE(qnm_snoc_gc, SM8250_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8250_SLAVE_LLCC);
DEFINE_QNODE(qnm_snoc_sf, SM8250_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC, SM8250_SLAVE_MEM_NOC_PCIE_SNOC);
DEFINE_QNODE(ipa_core_master, SM8250_MASTER_IPA_CORE, 1, 8, SM8250_SLAVE_IPA_CORE);
DEFINE_QNODE(llcc_mc, SM8250_MASTER_LLCC, 4, 4, SM8250_SLAVE_EBI_CH0);
DEFINE_QNODE(qhm_mnoc_cfg, SM8250_MASTER_CNOC_MNOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_MNOC);
DEFINE_QNODE(qnm_camnoc_hf, SM8250_MASTER_CAMNOC_HF, 2, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC);
DEFINE_QNODE(qnm_camnoc_icp, SM8250_MASTER_CAMNOC_ICP, 1, 8, SM8250_SLAVE_MNOC_SF_MEM_NOC);
DEFINE_QNODE(qnm_camnoc_sf, SM8250_MASTER_CAMNOC_SF, 2, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
DEFINE_QNODE(qnm_video0, SM8250_MASTER_VIDEO_P0, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
DEFINE_QNODE(qnm_video1, SM8250_MASTER_VIDEO_P1, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
DEFINE_QNODE(qnm_video_cvp, SM8250_MASTER_VIDEO_PROC, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
DEFINE_QNODE(qxm_mdp0, SM8250_MASTER_MDP_PORT0, 1, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC);
DEFINE_QNODE(qxm_mdp1, SM8250_MASTER_MDP_PORT1, 1, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC);
DEFINE_QNODE(qxm_rot, SM8250_MASTER_ROTATOR, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
DEFINE_QNODE(amm_npu_sys, SM8250_MASTER_NPU_SYS, 4, 32, SM8250_SLAVE_NPU_COMPUTE_NOC);
DEFINE_QNODE(amm_npu_sys_cdp_w, SM8250_MASTER_NPU_CDP, 2, 16, SM8250_SLAVE_NPU_COMPUTE_NOC);
DEFINE_QNODE(qhm_cfg, SM8250_MASTER_NPU_NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_NPU_NOC, SM8250_SLAVE_ISENSE_CFG, SM8250_SLAVE_NPU_LLM_CFG, SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, SM8250_SLAVE_NPU_CP, SM8250_SLAVE_NPU_TCM, SM8250_SLAVE_NPU_CAL_DP0, SM8250_SLAVE_NPU_CAL_DP1, SM8250_SLAVE_NPU_DPM);
DEFINE_QNODE(qhm_snoc_cfg, SM8250_MASTER_SNOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_SNOC);
DEFINE_QNODE(qnm_aggre1_noc, SM8250_A1NOC_SNOC_MAS, 1, 16, SM8250_SLAVE_SNOC_GEM_NOC_SF);
DEFINE_QNODE(qnm_aggre2_noc, SM8250_A2NOC_SNOC_MAS, 1, 16, SM8250_SLAVE_SNOC_GEM_NOC_SF);
DEFINE_QNODE(qnm_gemnoc, SM8250_MASTER_GEM_NOC_SNOC, 1, 16, SM8250_SLAVE_PIMEM, SM8250_SLAVE_OCIMEM, SM8250_SLAVE_APPSS, SM8250_SNOC_CNOC_SLV, SM8250_SLAVE_TCU, SM8250_SLAVE_QDSS_STM);
DEFINE_QNODE(qnm_gemnoc_pcie, SM8250_MASTER_GEM_NOC_PCIE_SNOC, 1, 8, SM8250_SLAVE_PCIE_2, SM8250_SLAVE_PCIE_0, SM8250_SLAVE_PCIE_1);
DEFINE_QNODE(qxm_pimem, SM8250_MASTER_PIMEM, 1, 8, SM8250_SLAVE_SNOC_GEM_NOC_GC);
DEFINE_QNODE(xm_gic, SM8250_MASTER_GIC, 1, 8, SM8250_SLAVE_SNOC_GEM_NOC_GC);
DEFINE_QNODE(qns_a1noc_snoc, SM8250_A1NOC_SNOC_SLV, 1, 16, SM8250_A1NOC_SNOC_MAS);
DEFINE_QNODE(qns_pcie_modem_mem_noc, SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1, 1, 16, SM8250_MASTER_ANOC_PCIE_GEM_NOC);
DEFINE_QNODE(srvc_aggre1_noc, SM8250_SLAVE_SERVICE_A1NOC, 1, 4);
DEFINE_QNODE(qns_a2noc_snoc, SM8250_A2NOC_SNOC_SLV, 1, 16, SM8250_A2NOC_SNOC_MAS);
DEFINE_QNODE(qns_pcie_mem_noc, SM8250_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM8250_MASTER_ANOC_PCIE_GEM_NOC);
DEFINE_QNODE(srvc_aggre2_noc, SM8250_SLAVE_SERVICE_A2NOC, 1, 4);
DEFINE_QNODE(qns_cdsp_mem_noc, SM8250_SLAVE_CDSP_MEM_NOC, 2, 32, SM8250_MASTER_COMPUTE_NOC);
DEFINE_QNODE(qhs_a1_noc_cfg, SM8250_SLAVE_A1NOC_CFG, 1, 4, SM8250_MASTER_A1NOC_CFG);
DEFINE_QNODE(qhs_a2_noc_cfg, SM8250_SLAVE_A2NOC_CFG, 1, 4, SM8250_MASTER_A2NOC_CFG);
DEFINE_QNODE(qhs_ahb2phy0, SM8250_SLAVE_AHB2PHY_SOUTH, 1, 4);
DEFINE_QNODE(qhs_ahb2phy1, SM8250_SLAVE_AHB2PHY_NORTH, 1, 4);
DEFINE_QNODE(qhs_aoss, SM8250_SLAVE_AOSS, 1, 4);
DEFINE_QNODE(qhs_camera_cfg, SM8250_SLAVE_CAMERA_CFG, 1, 4);
DEFINE_QNODE(qhs_clk_ctl, SM8250_SLAVE_CLK_CTL, 1, 4);
DEFINE_QNODE(qhs_compute_dsp, SM8250_SLAVE_CDSP_CFG, 1, 4);
DEFINE_QNODE(qhs_cpr_cx, SM8250_SLAVE_RBCPR_CX_CFG, 1, 4);
DEFINE_QNODE(qhs_cpr_mmcx, SM8250_SLAVE_RBCPR_MMCX_CFG, 1, 4);
DEFINE_QNODE(qhs_cpr_mx, SM8250_SLAVE_RBCPR_MX_CFG, 1, 4);
DEFINE_QNODE(qhs_crypto0_cfg, SM8250_SLAVE_CRYPTO_0_CFG, 1, 4);
DEFINE_QNODE(qhs_cx_rdpm, SM8250_SLAVE_CX_RDPM, 1, 4);
DEFINE_QNODE(qhs_dcc_cfg, SM8250_SLAVE_DCC_CFG, 1, 4);
DEFINE_QNODE(qhs_ddrss_cfg, SM8250_SLAVE_CNOC_DDRSS, 1, 4, SM8250_MASTER_CNOC_DC_NOC);
DEFINE_QNODE(qhs_display_cfg, SM8250_SLAVE_DISPLAY_CFG, 1, 4);
DEFINE_QNODE(qhs_gpuss_cfg, SM8250_SLAVE_GRAPHICS_3D_CFG, 1, 8);
DEFINE_QNODE(qhs_imem_cfg, SM8250_SLAVE_IMEM_CFG, 1, 4);
DEFINE_QNODE(qhs_ipa, SM8250_SLAVE_IPA_CFG, 1, 4);
DEFINE_QNODE(qhs_ipc_router, SM8250_SLAVE_IPC_ROUTER_CFG, 1, 4);
DEFINE_QNODE(qhs_lpass_cfg, SM8250_SLAVE_LPASS, 1, 4);
DEFINE_QNODE(qhs_mnoc_cfg, SM8250_SLAVE_CNOC_MNOC_CFG, 1, 4, SM8250_MASTER_CNOC_MNOC_CFG);
DEFINE_QNODE(qhs_npu_cfg, SM8250_SLAVE_NPU_CFG, 1, 4, SM8250_MASTER_NPU_NOC_CFG);
DEFINE_QNODE(qhs_pcie0_cfg, SM8250_SLAVE_PCIE_0_CFG, 1, 4);
DEFINE_QNODE(qhs_pcie1_cfg, SM8250_SLAVE_PCIE_1_CFG, 1, 4);
DEFINE_QNODE(qhs_pcie_modem_cfg, SM8250_SLAVE_PCIE_2_CFG, 1, 4);
DEFINE_QNODE(qhs_pdm, SM8250_SLAVE_PDM, 1, 4);
DEFINE_QNODE(qhs_pimem_cfg, SM8250_SLAVE_PIMEM_CFG, 1, 4);
DEFINE_QNODE(qhs_prng, SM8250_SLAVE_PRNG, 1, 4);
DEFINE_QNODE(qhs_qdss_cfg, SM8250_SLAVE_QDSS_CFG, 1, 4);
DEFINE_QNODE(qhs_qspi, SM8250_SLAVE_QSPI_0, 1, 4);
DEFINE_QNODE(qhs_qup0, SM8250_SLAVE_QUP_0, 1, 4);
DEFINE_QNODE(qhs_qup1, SM8250_SLAVE_QUP_1, 1, 4);
DEFINE_QNODE(qhs_qup2, SM8250_SLAVE_QUP_2, 1, 4);
DEFINE_QNODE(qhs_sdc2, SM8250_SLAVE_SDCC_2, 1, 4);
DEFINE_QNODE(qhs_sdc4, SM8250_SLAVE_SDCC_4, 1, 4);
DEFINE_QNODE(qhs_snoc_cfg, SM8250_SLAVE_SNOC_CFG, 1, 4, SM8250_MASTER_SNOC_CFG);
DEFINE_QNODE(qhs_tcsr, SM8250_SLAVE_TCSR, 1, 4);
DEFINE_QNODE(qhs_tlmm0, SM8250_SLAVE_TLMM_NORTH, 1, 4);
DEFINE_QNODE(qhs_tlmm1, SM8250_SLAVE_TLMM_SOUTH, 1, 4);
DEFINE_QNODE(qhs_tlmm2, SM8250_SLAVE_TLMM_WEST, 1, 4);
DEFINE_QNODE(qhs_tsif, SM8250_SLAVE_TSIF, 1, 4);
DEFINE_QNODE(qhs_ufs_card_cfg, SM8250_SLAVE_UFS_CARD_CFG, 1, 4);
DEFINE_QNODE(qhs_ufs_mem_cfg, SM8250_SLAVE_UFS_MEM_CFG, 1, 4);
DEFINE_QNODE(qhs_usb3_0, SM8250_SLAVE_USB3, 1, 4);
DEFINE_QNODE(qhs_usb3_1, SM8250_SLAVE_USB3_1, 1, 4);
DEFINE_QNODE(qhs_venus_cfg, SM8250_SLAVE_VENUS_CFG, 1, 4);
DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8250_SLAVE_VSENSE_CTRL_CFG, 1, 4);
DEFINE_QNODE(qns_cnoc_a2noc, SM8250_SLAVE_CNOC_A2NOC, 1, 8, SM8250_MASTER_CNOC_A2NOC);
DEFINE_QNODE(srvc_cnoc, SM8250_SLAVE_SERVICE_CNOC, 1, 4);
DEFINE_QNODE(qhs_llcc, SM8250_SLAVE_LLCC_CFG, 1, 4);
DEFINE_QNODE(qhs_memnoc, SM8250_SLAVE_GEM_NOC_CFG, 1, 4, SM8250_MASTER_GEM_NOC_CFG);
DEFINE_QNODE(qns_gem_noc_snoc, SM8250_SLAVE_GEM_NOC_SNOC, 1, 16, SM8250_MASTER_GEM_NOC_SNOC);
DEFINE_QNODE(qns_llcc, SM8250_SLAVE_LLCC, 4, 16, SM8250_MASTER_LLCC);
DEFINE_QNODE(qns_sys_pcie, SM8250_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8, SM8250_MASTER_GEM_NOC_PCIE_SNOC);
DEFINE_QNODE(srvc_even_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC_1, 1, 4);
DEFINE_QNODE(srvc_odd_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC_2, 1, 4);
DEFINE_QNODE(srvc_sys_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC, 1, 4);
DEFINE_QNODE(ipa_core_slave, SM8250_SLAVE_IPA_CORE, 1, 8);
DEFINE_QNODE(ebi, SM8250_SLAVE_EBI_CH0, 4, 4);
DEFINE_QNODE(qns_mem_noc_hf, SM8250_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8250_MASTER_MNOC_HF_MEM_NOC);
DEFINE_QNODE(qns_mem_noc_sf, SM8250_SLAVE_MNOC_SF_MEM_NOC, 2, 32, SM8250_MASTER_MNOC_SF_MEM_NOC);
DEFINE_QNODE(srvc_mnoc, SM8250_SLAVE_SERVICE_MNOC, 1, 4);
DEFINE_QNODE(qhs_cal_dp0, SM8250_SLAVE_NPU_CAL_DP0, 1, 4);
DEFINE_QNODE(qhs_cal_dp1, SM8250_SLAVE_NPU_CAL_DP1, 1, 4);
DEFINE_QNODE(qhs_cp, SM8250_SLAVE_NPU_CP, 1, 4);
DEFINE_QNODE(qhs_dma_bwmon, SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, 1, 4);
DEFINE_QNODE(qhs_dpm, SM8250_SLAVE_NPU_DPM, 1, 4);
DEFINE_QNODE(qhs_isense, SM8250_SLAVE_ISENSE_CFG, 1, 4);
DEFINE_QNODE(qhs_llm, SM8250_SLAVE_NPU_LLM_CFG, 1, 4);
DEFINE_QNODE(qhs_tcm, SM8250_SLAVE_NPU_TCM, 1, 4);
DEFINE_QNODE(qns_npu_sys, SM8250_SLAVE_NPU_COMPUTE_NOC, 2, 32);
DEFINE_QNODE(srvc_noc, SM8250_SLAVE_SERVICE_NPU_NOC, 1, 4);
DEFINE_QNODE(qhs_apss, SM8250_SLAVE_APPSS, 1, 8);
DEFINE_QNODE(qns_cnoc, SM8250_SNOC_CNOC_SLV, 1, 8, SM8250_SNOC_CNOC_MAS);
DEFINE_QNODE(qns_gemnoc_gc, SM8250_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8250_MASTER_SNOC_GC_MEM_NOC);
DEFINE_QNODE(qns_gemnoc_sf, SM8250_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8250_MASTER_SNOC_SF_MEM_NOC);
DEFINE_QNODE(qxs_imem, SM8250_SLAVE_OCIMEM, 1, 8);
DEFINE_QNODE(qxs_pimem, SM8250_SLAVE_PIMEM, 1, 8);
DEFINE_QNODE(srvc_snoc, SM8250_SLAVE_SERVICE_SNOC, 1, 4);
DEFINE_QNODE(xs_pcie_0, SM8250_SLAVE_PCIE_0, 1, 8);
DEFINE_QNODE(xs_pcie_1, SM8250_SLAVE_PCIE_1, 1, 8);
DEFINE_QNODE(xs_pcie_modem, SM8250_SLAVE_PCIE_2, 1, 8);
DEFINE_QNODE(xs_qdss_stm, SM8250_SLAVE_QDSS_STM, 1, 4);
DEFINE_QNODE(xs_sys_tcu_cfg, SM8250_SLAVE_TCU, 1, 8);
DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
DEFINE_QBCM(bcm_ip0, "IP0", false, &ipa_core_slave);
DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1);
DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu);
DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf);
DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup1, &qhm_qup2, &qhm_qup0);
DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc);
DEFINE_QBCM(bcm_mm3, "MM3", false, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp);
DEFINE_QBCM(bcm_sh4, "SH4", false, &chm_apps);
DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_mem_noc);
DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_cx_rdpm, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_ipc_router, &qhs_lpass_cfg, &qhs_mnoc_cfg, &qhs_npu_cfg, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_pcie_modem_cfg, &qhs_pdm, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qspi, &qhs_qup0, &qhs_qup1, &qhs_qup2, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_tcsr, &qhs_tlmm0, &qhs_tlmm1, &qhs_tlmm2, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc);
DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);
DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu);
DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem);
DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm);
DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_pcie_modem);
DEFINE_QBCM(bcm_sn6, "SN6", false, &xs_pcie_0, &xs_pcie_1);
DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc);
DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre2_noc);
DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_gemnoc_pcie);
DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_gemnoc);
DEFINE_QBCM(bcm_sn12, "SN12", false, &qns_pcie_modem_mem_noc, &qns_pcie_mem_noc);
static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
&bcm_qup0,
&bcm_sn12,
};
static struct qcom_icc_node *aggre1_noc_nodes[] = {
[MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
[MASTER_QSPI_0] = &qhm_qspi,
[MASTER_QUP_1] = &qhm_qup1,
[MASTER_QUP_2] = &qhm_qup2,
[MASTER_TSIF] = &qhm_tsif,
[MASTER_PCIE_2] = &xm_pcie3_modem,
[MASTER_SDCC_4] = &xm_sdc4,
[MASTER_UFS_MEM] = &xm_ufs_mem,
[MASTER_USB3] = &xm_usb3_0,
[MASTER_USB3_1] = &xm_usb3_1,
[A1NOC_SNOC_SLV] = &qns_a1noc_snoc,
[SLAVE_ANOC_PCIE_GEM_NOC_1] = &qns_pcie_modem_mem_noc,
[SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
};
static struct qcom_icc_desc sm8250_aggre1_noc = {
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
};
static struct qcom_icc_bcm *aggre2_noc_bcms[] = {
&bcm_ce0,
&bcm_qup0,
&bcm_sn12,
};
static struct qcom_icc_node *aggre2_noc_nodes[] = {
[MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
[MASTER_QDSS_BAM] = &qhm_qdss_bam,
[MASTER_QUP_0] = &qhm_qup0,
[MASTER_CNOC_A2NOC] = &qnm_cnoc,
[MASTER_CRYPTO_CORE_0] = &qxm_crypto,
[MASTER_IPA] = &qxm_ipa,
[MASTER_PCIE] = &xm_pcie3_0,
[MASTER_PCIE_1] = &xm_pcie3_1,
[MASTER_QDSS_ETR] = &xm_qdss_etr,
[MASTER_SDCC_2] = &xm_sdc2,
[MASTER_UFS_CARD] = &xm_ufs_card,
[A2NOC_SNOC_SLV] = &qns_a2noc_snoc,
[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
[SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
};
static struct qcom_icc_desc sm8250_aggre2_noc = {
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
};
static struct qcom_icc_bcm *compute_noc_bcms[] = {
&bcm_co0,
&bcm_co2,
};
static struct qcom_icc_node *compute_noc_nodes[] = {
[MASTER_NPU] = &qnm_npu,
[SLAVE_CDSP_MEM_NOC] = &qns_cdsp_mem_noc,
};
static struct qcom_icc_desc sm8250_compute_noc = {
.nodes = compute_noc_nodes,
.num_nodes = ARRAY_SIZE(compute_noc_nodes),
.bcms = compute_noc_bcms,
.num_bcms = ARRAY_SIZE(compute_noc_bcms),
};
static struct qcom_icc_bcm *config_noc_bcms[] = {
&bcm_cn0,
};
static struct qcom_icc_node *config_noc_nodes[] = {
[SNOC_CNOC_MAS] = &qnm_snoc,
[MASTER_QDSS_DAP] = &xm_qdss_dap,
[SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
[SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
[SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
[SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
[SLAVE_AOSS] = &qhs_aoss,
[SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
[SLAVE_CLK_CTL] = &qhs_clk_ctl,
[SLAVE_CDSP_CFG] = &qhs_compute_dsp,
[SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
[SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
[SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
[SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
[SLAVE_CX_RDPM] = &qhs_cx_rdpm,
[SLAVE_DCC_CFG] = &qhs_dcc_cfg,
[SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
[SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
[SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg,
[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
[SLAVE_IPA_CFG] = &qhs_ipa,
[SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
[SLAVE_LPASS] = &qhs_lpass_cfg,
[SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
[SLAVE_NPU_CFG] = &qhs_npu_cfg,
[SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
[SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
[SLAVE_PCIE_2_CFG] = &qhs_pcie_modem_cfg,
[SLAVE_PDM] = &qhs_pdm,
[SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
[SLAVE_PRNG] = &qhs_prng,
[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
[SLAVE_QSPI_0] = &qhs_qspi,
[SLAVE_QUP_0] = &qhs_qup0,
[SLAVE_QUP_1] = &qhs_qup1,
[SLAVE_QUP_2] = &qhs_qup2,
[SLAVE_SDCC_2] = &qhs_sdc2,
[SLAVE_SDCC_4] = &qhs_sdc4,
[SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
[SLAVE_TCSR] = &qhs_tcsr,
[SLAVE_TLMM_NORTH] = &qhs_tlmm0,
[SLAVE_TLMM_SOUTH] = &qhs_tlmm1,
[SLAVE_TLMM_WEST] = &qhs_tlmm2,
[SLAVE_TSIF] = &qhs_tsif,
[SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
[SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
[SLAVE_USB3] = &qhs_usb3_0,
[SLAVE_USB3_1] = &qhs_usb3_1,
[SLAVE_VENUS_CFG] = &qhs_venus_cfg,
[SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
[SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
[SLAVE_SERVICE_CNOC] = &srvc_cnoc,
};
static struct qcom_icc_desc sm8250_config_noc = {
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
.num_bcms = ARRAY_SIZE(config_noc_bcms),
};
static struct qcom_icc_bcm *dc_noc_bcms[] = {
};
static struct qcom_icc_node *dc_noc_nodes[] = {
[MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc,
[SLAVE_LLCC_CFG] = &qhs_llcc,
[SLAVE_GEM_NOC_CFG] = &qhs_memnoc,
};
static struct qcom_icc_desc sm8250_dc_noc = {
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
.bcms = dc_noc_bcms,
.num_bcms = ARRAY_SIZE(dc_noc_bcms),
};
static struct qcom_icc_bcm *gem_noc_bcms[] = {
&bcm_sh0,
&bcm_sh2,
&bcm_sh3,
&bcm_sh4,
};
static struct qcom_icc_node *gem_noc_nodes[] = {
[MASTER_GPU_TCU] = &alm_gpu_tcu,
[MASTER_SYS_TCU] = &alm_sys_tcu,
[MASTER_AMPSS_M0] = &chm_apps,
[MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg,
[MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
[MASTER_GRAPHICS_3D] = &qnm_gpu,
[MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
[MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
[MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
[MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
[SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc,
[SLAVE_LLCC] = &qns_llcc,
[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_sys_pcie,
[SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
[SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
[SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
};
static struct qcom_icc_desc sm8250_gem_noc = {
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
};
static struct qcom_icc_bcm *ipa_virt_bcms[] = {
&bcm_ip0,
};
static struct qcom_icc_node *ipa_virt_nodes[] = {
[MASTER_IPA_CORE] = &ipa_core_master,
[SLAVE_IPA_CORE] = &ipa_core_slave,
};
static struct qcom_icc_desc sm8250_ipa_virt = {
.nodes = ipa_virt_nodes,
.num_nodes = ARRAY_SIZE(ipa_virt_nodes),
.bcms = ipa_virt_bcms,
.num_bcms = ARRAY_SIZE(ipa_virt_bcms),
};
static struct qcom_icc_bcm *mc_virt_bcms[] = {
&bcm_acv,
&bcm_mc0,
};
static struct qcom_icc_node *mc_virt_nodes[] = {
[MASTER_LLCC] = &llcc_mc,
[SLAVE_EBI_CH0] = &ebi,
};
static struct qcom_icc_desc sm8250_mc_virt = {
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
.num_bcms = ARRAY_SIZE(mc_virt_bcms),
};
static struct qcom_icc_bcm *mmss_noc_bcms[] = {
&bcm_mm0,
&bcm_mm1,
&bcm_mm2,
&bcm_mm3,
};
static struct qcom_icc_node *mmss_noc_nodes[] = {
[MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
[MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
[MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
[MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
[MASTER_VIDEO_P0] = &qnm_video0,
[MASTER_VIDEO_P1] = &qnm_video1,
[MASTER_VIDEO_PROC] = &qnm_video_cvp,
[MASTER_MDP_PORT0] = &qxm_mdp0,
[MASTER_MDP_PORT1] = &qxm_mdp1,
[MASTER_ROTATOR] = &qxm_rot,
[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
[SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
};
static struct qcom_icc_desc sm8250_mmss_noc = {
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
};
static struct qcom_icc_bcm *npu_noc_bcms[] = {
};
static struct qcom_icc_node *npu_noc_nodes[] = {
[MASTER_NPU_SYS] = &amm_npu_sys,
[MASTER_NPU_CDP] = &amm_npu_sys_cdp_w,
[MASTER_NPU_NOC_CFG] = &qhm_cfg,
[SLAVE_NPU_CAL_DP0] = &qhs_cal_dp0,
[SLAVE_NPU_CAL_DP1] = &qhs_cal_dp1,
[SLAVE_NPU_CP] = &qhs_cp,
[SLAVE_NPU_INT_DMA_BWMON_CFG] = &qhs_dma_bwmon,
[SLAVE_NPU_DPM] = &qhs_dpm,
[SLAVE_ISENSE_CFG] = &qhs_isense,
[SLAVE_NPU_LLM_CFG] = &qhs_llm,
[SLAVE_NPU_TCM] = &qhs_tcm,
[SLAVE_NPU_COMPUTE_NOC] = &qns_npu_sys,
[SLAVE_SERVICE_NPU_NOC] = &srvc_noc,
};
static struct qcom_icc_desc sm8250_npu_noc = {
.nodes = npu_noc_nodes,
.num_nodes = ARRAY_SIZE(npu_noc_nodes),
.bcms = npu_noc_bcms,
.num_bcms = ARRAY_SIZE(npu_noc_bcms),
};
static struct qcom_icc_bcm *system_noc_bcms[] = {
&bcm_sn0,
&bcm_sn1,
&bcm_sn11,
&bcm_sn2,
&bcm_sn3,
&bcm_sn4,
&bcm_sn5,
&bcm_sn6,
&bcm_sn7,
&bcm_sn8,
&bcm_sn9,
};
static struct qcom_icc_node *system_noc_nodes[] = {
[MASTER_SNOC_CFG] = &qhm_snoc_cfg,
[A1NOC_SNOC_MAS] = &qnm_aggre1_noc,
[A2NOC_SNOC_MAS] = &qnm_aggre2_noc,
[MASTER_GEM_NOC_SNOC] = &qnm_gemnoc,
[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
[MASTER_PIMEM] = &qxm_pimem,
[MASTER_GIC] = &xm_gic,
[SLAVE_APPSS] = &qhs_apss,
[SNOC_CNOC_SLV] = &qns_cnoc,
[SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
[SLAVE_OCIMEM] = &qxs_imem,
[SLAVE_PIMEM] = &qxs_pimem,
[SLAVE_SERVICE_SNOC] = &srvc_snoc,
[SLAVE_PCIE_0] = &xs_pcie_0,
[SLAVE_PCIE_1] = &xs_pcie_1,
[SLAVE_PCIE_2] = &xs_pcie_modem,
[SLAVE_QDSS_STM] = &xs_qdss_stm,
[SLAVE_TCU] = &xs_sys_tcu_cfg,
};
static struct qcom_icc_desc sm8250_system_noc = {
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
.num_bcms = ARRAY_SIZE(system_noc_bcms),
};
static int qnoc_probe(struct platform_device *pdev)
{
const struct qcom_icc_desc *desc;
struct icc_onecell_data *data;
struct icc_provider *provider;
struct qcom_icc_node **qnodes;
struct qcom_icc_provider *qp;
struct icc_node *node;
size_t num_nodes, i;
int ret;
desc = device_get_match_data(&pdev->dev);
if (!desc)
return -EINVAL;
qnodes = desc->nodes;
num_nodes = desc->num_nodes;
qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
if (!qp)
return -ENOMEM;
data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
if (!data)
return -ENOMEM;
provider = &qp->provider;
provider->dev = &pdev->dev;
provider->set = qcom_icc_set;
provider->pre_aggregate = qcom_icc_pre_aggregate;
provider->aggregate = qcom_icc_aggregate;
provider->xlate = of_icc_xlate_onecell;
INIT_LIST_HEAD(&provider->nodes);
provider->data = data;
qp->dev = &pdev->dev;
qp->bcms = desc->bcms;
qp->num_bcms = desc->num_bcms;
qp->voter = of_bcm_voter_get(qp->dev, NULL);
if (IS_ERR(qp->voter))
return PTR_ERR(qp->voter);
ret = icc_provider_add(provider);
if (ret) {
dev_err(&pdev->dev, "error adding interconnect provider\n");
return ret;
}
for (i = 0; i < num_nodes; i++) {
size_t j;
if (!qnodes[i])
continue;
node = icc_node_create(qnodes[i]->id);
if (IS_ERR(node)) {
ret = PTR_ERR(node);
goto err;
}
node->name = qnodes[i]->name;
node->data = qnodes[i];
icc_node_add(node, provider);
for (j = 0; j < qnodes[i]->num_links; j++)
icc_link_create(node, qnodes[i]->links[j]);
data->nodes[i] = node;
}
data->num_nodes = num_nodes;
for (i = 0; i < qp->num_bcms; i++)
qcom_icc_bcm_init(qp->bcms[i], &pdev->dev);
platform_set_drvdata(pdev, qp);
return 0;
err:
icc_nodes_remove(provider);
icc_provider_del(provider);
return ret;
}
static int qnoc_remove(struct platform_device *pdev)
{
struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
icc_nodes_remove(&qp->provider);
return icc_provider_del(&qp->provider);
}
static const struct of_device_id qnoc_of_match[] = {
{ .compatible = "qcom,sm8250-aggre1-noc",
.data = &sm8250_aggre1_noc},
{ .compatible = "qcom,sm8250-aggre2-noc",
.data = &sm8250_aggre2_noc},
{ .compatible = "qcom,sm8250-compute-noc",
.data = &sm8250_compute_noc},
{ .compatible = "qcom,sm8250-config-noc",
.data = &sm8250_config_noc},
{ .compatible = "qcom,sm8250-dc-noc",
.data = &sm8250_dc_noc},
{ .compatible = "qcom,sm8250-gem-noc",
.data = &sm8250_gem_noc},
{ .compatible = "qcom,sm8250-ipa-virt",
.data = &sm8250_ipa_virt},
{ .compatible = "qcom,sm8250-mc-virt",
.data = &sm8250_mc_virt},
{ .compatible = "qcom,sm8250-mmss-noc",
.data = &sm8250_mmss_noc},
{ .compatible = "qcom,sm8250-npu-noc",
.data = &sm8250_npu_noc},
{ .compatible = "qcom,sm8250-system-noc",
.data = &sm8250_system_noc},
{ }
};
MODULE_DEVICE_TABLE(of, qnoc_of_match);
static struct platform_driver qnoc_driver = {
.probe = qnoc_probe,
.remove = qnoc_remove,
.driver = {
.name = "qnoc-sm8250",
.of_match_table = qnoc_of_match,
},
};
module_platform_driver(qnoc_driver);
MODULE_DESCRIPTION("Qualcomm SM8250 NoC driver");
MODULE_LICENSE("GPL v2");

164
drivers/interconnect/qcom/sm8250.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Qualcomm #define SM8250 interconnect IDs
*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8250_H
#define __DRIVERS_INTERCONNECT_QCOM_SM8250_H
#define SM8250_A1NOC_SNOC_MAS 0
#define SM8250_A1NOC_SNOC_SLV 1
#define SM8250_A2NOC_SNOC_MAS 2
#define SM8250_A2NOC_SNOC_SLV 3
#define SM8250_MASTER_A1NOC_CFG 4
#define SM8250_MASTER_A2NOC_CFG 5
#define SM8250_MASTER_AMPSS_M0 6
#define SM8250_MASTER_ANOC_PCIE_GEM_NOC 7
#define SM8250_MASTER_CAMNOC_HF 8
#define SM8250_MASTER_CAMNOC_ICP 9
#define SM8250_MASTER_CAMNOC_SF 10
#define SM8250_MASTER_CNOC_A2NOC 11
#define SM8250_MASTER_CNOC_DC_NOC 12
#define SM8250_MASTER_CNOC_MNOC_CFG 13
#define SM8250_MASTER_COMPUTE_NOC 14
#define SM8250_MASTER_CRYPTO_CORE_0 15
#define SM8250_MASTER_GEM_NOC_CFG 16
#define SM8250_MASTER_GEM_NOC_PCIE_SNOC 17
#define SM8250_MASTER_GEM_NOC_SNOC 18
#define SM8250_MASTER_GIC 19
#define SM8250_MASTER_GPU_TCU 20
#define SM8250_MASTER_GRAPHICS_3D 21
#define SM8250_MASTER_IPA 22
#define SM8250_MASTER_IPA_CORE 23
#define SM8250_MASTER_LLCC 24
#define SM8250_MASTER_MDP_PORT0 25
#define SM8250_MASTER_MDP_PORT1 26
#define SM8250_MASTER_MNOC_HF_MEM_NOC 27
#define SM8250_MASTER_MNOC_SF_MEM_NOC 28
#define SM8250_MASTER_NPU 29
#define SM8250_MASTER_NPU_CDP 30
#define SM8250_MASTER_NPU_NOC_CFG 31
#define SM8250_MASTER_NPU_SYS 32
#define SM8250_MASTER_PCIE 33
#define SM8250_MASTER_PCIE_1 34
#define SM8250_MASTER_PCIE_2 35
#define SM8250_MASTER_PIMEM 36
#define SM8250_MASTER_QDSS_BAM 37
#define SM8250_MASTER_QDSS_DAP 38
#define SM8250_MASTER_QDSS_ETR 39
#define SM8250_MASTER_QSPI_0 40
#define SM8250_MASTER_QUP_0 41
#define SM8250_MASTER_QUP_1 42
#define SM8250_MASTER_QUP_2 43
#define SM8250_MASTER_ROTATOR 44
#define SM8250_MASTER_SDCC_2 45
#define SM8250_MASTER_SDCC_4 46
#define SM8250_MASTER_SNOC_CFG 47
#define SM8250_MASTER_SNOC_GC_MEM_NOC 48
#define SM8250_MASTER_SNOC_SF_MEM_NOC 49
#define SM8250_MASTER_SYS_TCU 50
#define SM8250_MASTER_TSIF 51
#define SM8250_MASTER_UFS_CARD 52
#define SM8250_MASTER_UFS_MEM 53
#define SM8250_MASTER_USB3 54
#define SM8250_MASTER_USB3_1 55
#define SM8250_MASTER_VIDEO_P0 56
#define SM8250_MASTER_VIDEO_P1 57
#define SM8250_MASTER_VIDEO_PROC 58
#define SM8250_SLAVE_A1NOC_CFG 59
#define SM8250_SLAVE_A2NOC_CFG 60
#define SM8250_SLAVE_AHB2PHY_NORTH 61
#define SM8250_SLAVE_AHB2PHY_SOUTH 62
#define SM8250_SLAVE_ANOC_PCIE_GEM_NOC 63
#define SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1 64
#define SM8250_SLAVE_AOSS 65
#define SM8250_SLAVE_APPSS 66
#define SM8250_SLAVE_CAMERA_CFG 67
#define SM8250_SLAVE_CDSP_CFG 68
#define SM8250_SLAVE_CDSP_MEM_NOC 69
#define SM8250_SLAVE_CLK_CTL 70
#define SM8250_SLAVE_CNOC_A2NOC 71
#define SM8250_SLAVE_CNOC_DDRSS 72
#define SM8250_SLAVE_CNOC_MNOC_CFG 73
#define SM8250_SLAVE_CRYPTO_0_CFG 74
#define SM8250_SLAVE_CX_RDPM 75
#define SM8250_SLAVE_DCC_CFG 76
#define SM8250_SLAVE_DISPLAY_CFG 77
#define SM8250_SLAVE_EBI_CH0 78
#define SM8250_SLAVE_GEM_NOC_CFG 79
#define SM8250_SLAVE_GEM_NOC_SNOC 80
#define SM8250_SLAVE_GRAPHICS_3D_CFG 81
#define SM8250_SLAVE_IMEM_CFG 82
#define SM8250_SLAVE_IPA_CFG 83
#define SM8250_SLAVE_IPA_CORE 84
#define SM8250_SLAVE_IPC_ROUTER_CFG 85
#define SM8250_SLAVE_ISENSE_CFG 86
#define SM8250_SLAVE_LLCC 87
#define SM8250_SLAVE_LLCC_CFG 88
#define SM8250_SLAVE_LPASS 89
#define SM8250_SLAVE_MEM_NOC_PCIE_SNOC 90
#define SM8250_SLAVE_MNOC_HF_MEM_NOC 91
#define SM8250_SLAVE_MNOC_SF_MEM_NOC 92
#define SM8250_SLAVE_NPU_CAL_DP0 93
#define SM8250_SLAVE_NPU_CAL_DP1 94
#define SM8250_SLAVE_NPU_CFG 95
#define SM8250_SLAVE_NPU_COMPUTE_NOC 96
#define SM8250_SLAVE_NPU_CP 97
#define SM8250_SLAVE_NPU_DPM 98
#define SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG 99
#define SM8250_SLAVE_NPU_LLM_CFG 100
#define SM8250_SLAVE_NPU_TCM 101
#define SM8250_SLAVE_OCIMEM 102
#define SM8250_SLAVE_PCIE_0 103
#define SM8250_SLAVE_PCIE_0_CFG 104
#define SM8250_SLAVE_PCIE_1 105
#define SM8250_SLAVE_PCIE_1_CFG 106
#define SM8250_SLAVE_PCIE_2 107
#define SM8250_SLAVE_PCIE_2_CFG 108
#define SM8250_SLAVE_PDM 109
#define SM8250_SLAVE_PIMEM 110
#define SM8250_SLAVE_PIMEM_CFG 111
#define SM8250_SLAVE_PRNG 112
#define SM8250_SLAVE_QDSS_CFG 113
#define SM8250_SLAVE_QDSS_STM 114
#define SM8250_SLAVE_QSPI_0 115
#define SM8250_SLAVE_QUP_0 116
#define SM8250_SLAVE_QUP_1 117
#define SM8250_SLAVE_QUP_2 118
#define SM8250_SLAVE_RBCPR_CX_CFG 119
#define SM8250_SLAVE_RBCPR_MMCX_CFG 120
#define SM8250_SLAVE_RBCPR_MX_CFG 121
#define SM8250_SLAVE_SDCC_2 122
#define SM8250_SLAVE_SDCC_4 123
#define SM8250_SLAVE_SERVICE_A1NOC 124
#define SM8250_SLAVE_SERVICE_A2NOC 125
#define SM8250_SLAVE_SERVICE_CNOC 126
#define SM8250_SLAVE_SERVICE_GEM_NOC 127
#define SM8250_SLAVE_SERVICE_GEM_NOC_1 128
#define SM8250_SLAVE_SERVICE_GEM_NOC_2 129
#define SM8250_SLAVE_SERVICE_MNOC 130
#define SM8250_SLAVE_SERVICE_NPU_NOC 131
#define SM8250_SLAVE_SERVICE_SNOC 132
#define SM8250_SLAVE_SNOC_CFG 133
#define SM8250_SLAVE_SNOC_GEM_NOC_GC 134
#define SM8250_SLAVE_SNOC_GEM_NOC_SF 135
#define SM8250_SLAVE_TCSR 136
#define SM8250_SLAVE_TCU 137
#define SM8250_SLAVE_TLMM_NORTH 138
#define SM8250_SLAVE_TLMM_SOUTH 139
#define SM8250_SLAVE_TLMM_WEST 140
#define SM8250_SLAVE_TSIF 141
#define SM8250_SLAVE_UFS_CARD_CFG 142
#define SM8250_SLAVE_UFS_MEM_CFG 143
#define SM8250_SLAVE_USB3 144
#define SM8250_SLAVE_USB3_1 145
#define SM8250_SLAVE_VENUS_CFG 146
#define SM8250_SLAVE_VSENSE_CTRL_CFG 147
#define SM8250_SNOC_CNOC_MAS 148
#define SM8250_SNOC_CNOC_SLV 149
#define SM8250_MASTER_EPSS_L3_APPS 150
#define SM8250_SLAVE_EPSS_L3 151
#endif

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include/dt-bindings/interconnect/qcom,icc.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_ICC_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_ICC_H
/*
* The AMC bucket denotes constraints that are applied to hardware when
* icc_set_bw() completes, whereas the WAKE and SLEEP constraints are applied
* when the execution environment transitions between active and low power mode.
*/
#define QCOM_ICC_BUCKET_AMC 0
#define QCOM_ICC_BUCKET_WAKE 1
#define QCOM_ICC_BUCKET_SLEEP 2
#define QCOM_ICC_NUM_BUCKETS 3
#define QCOM_ICC_TAG_AMC (1 << QCOM_ICC_BUCKET_AMC)
#define QCOM_ICC_TAG_WAKE (1 << QCOM_ICC_BUCKET_WAKE)
#define QCOM_ICC_TAG_SLEEP (1 << QCOM_ICC_BUCKET_SLEEP)
#define QCOM_ICC_TAG_ACTIVE_ONLY (QCOM_ICC_TAG_AMC | QCOM_ICC_TAG_WAKE)
#define QCOM_ICC_TAG_ALWAYS (QCOM_ICC_TAG_AMC | QCOM_ICC_TAG_WAKE |\
QCOM_ICC_TAG_SLEEP)
#endif

3
include/dt-bindings/interconnect/qcom,osm-l3.h
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@ -9,4 +9,7 @@
#define MASTER_OSM_L3_APPS 0
#define SLAVE_OSM_L3 1
#define MASTER_EPSS_L3_APPS 0
#define SLAVE_EPSS_L3_SHARED 1
#endif

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include/dt-bindings/interconnect/qcom,sm8150.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Qualcomm SM8150 interconnect IDs
*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8150_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_SM8150_H
#define MASTER_A1NOC_CFG 0
#define MASTER_QUP_0 1
#define MASTER_EMAC 2
#define MASTER_UFS_MEM 3
#define MASTER_USB3 4
#define MASTER_USB3_1 5
#define A1NOC_SNOC_SLV 6
#define SLAVE_SERVICE_A1NOC 7
#define MASTER_A2NOC_CFG 0
#define MASTER_QDSS_BAM 1
#define MASTER_QSPI 2
#define MASTER_QUP_1 3
#define MASTER_QUP_2 4
#define MASTER_SENSORS_AHB 5
#define MASTER_TSIF 6
#define MASTER_CNOC_A2NOC 7
#define MASTER_CRYPTO_CORE_0 8
#define MASTER_IPA 9
#define MASTER_PCIE 10
#define MASTER_PCIE_1 11
#define MASTER_QDSS_ETR 12
#define MASTER_SDCC_2 13
#define MASTER_SDCC_4 14
#define A2NOC_SNOC_SLV 15
#define SLAVE_ANOC_PCIE_GEM_NOC 16
#define SLAVE_SERVICE_A2NOC 17
#define MASTER_CAMNOC_HF0_UNCOMP 0
#define MASTER_CAMNOC_HF1_UNCOMP 1
#define MASTER_CAMNOC_SF_UNCOMP 2
#define SLAVE_CAMNOC_UNCOMP 3
#define MASTER_NPU 0
#define SLAVE_CDSP_MEM_NOC 1
#define MASTER_SPDM 0
#define SNOC_CNOC_MAS 1
#define MASTER_QDSS_DAP 2
#define SLAVE_A1NOC_CFG 3
#define SLAVE_A2NOC_CFG 4
#define SLAVE_AHB2PHY_SOUTH 5
#define SLAVE_AOP 6
#define SLAVE_AOSS 7
#define SLAVE_CAMERA_CFG 8
#define SLAVE_CLK_CTL 9
#define SLAVE_CDSP_CFG 10
#define SLAVE_RBCPR_CX_CFG 11
#define SLAVE_RBCPR_MMCX_CFG 12
#define SLAVE_RBCPR_MX_CFG 13
#define SLAVE_CRYPTO_0_CFG 14
#define SLAVE_CNOC_DDRSS 15
#define SLAVE_DISPLAY_CFG 16
#define SLAVE_EMAC_CFG 17
#define SLAVE_GLM 18
#define SLAVE_GRAPHICS_3D_CFG 19
#define SLAVE_IMEM_CFG 20
#define SLAVE_IPA_CFG 21
#define SLAVE_CNOC_MNOC_CFG 22
#define SLAVE_NPU_CFG 23
#define SLAVE_PCIE_0_CFG 24
#define SLAVE_PCIE_1_CFG 25
#define SLAVE_NORTH_PHY_CFG 26
#define SLAVE_PIMEM_CFG 27
#define SLAVE_PRNG 28
#define SLAVE_QDSS_CFG 29
#define SLAVE_QSPI 30
#define SLAVE_QUP_2 31
#define SLAVE_QUP_1 32
#define SLAVE_QUP_0 33
#define SLAVE_SDCC_2 34
#define SLAVE_SDCC_4 35
#define SLAVE_SNOC_CFG 36
#define SLAVE_SPDM_WRAPPER 37
#define SLAVE_SPSS_CFG 38
#define SLAVE_SSC_CFG 39
#define SLAVE_TCSR 40
#define SLAVE_TLMM_EAST 41
#define SLAVE_TLMM_NORTH 42
#define SLAVE_TLMM_SOUTH 43
#define SLAVE_TLMM_WEST 44
#define SLAVE_TSIF 45
#define SLAVE_UFS_CARD_CFG 46
#define SLAVE_UFS_MEM_CFG 47
#define SLAVE_USB3 48
#define SLAVE_USB3_1 49
#define SLAVE_VENUS_CFG 50
#define SLAVE_VSENSE_CTRL_CFG 51
#define SLAVE_CNOC_A2NOC 52
#define SLAVE_SERVICE_CNOC 53
#define MASTER_CNOC_DC_NOC 0
#define SLAVE_LLCC_CFG 1
#define SLAVE_GEM_NOC_CFG 2
#define MASTER_AMPSS_M0 0
#define MASTER_GPU_TCU 1
#define MASTER_SYS_TCU 2
#define MASTER_GEM_NOC_CFG 3
#define MASTER_COMPUTE_NOC 4
#define MASTER_GRAPHICS_3D 5
#define MASTER_MNOC_HF_MEM_NOC 6
#define MASTER_MNOC_SF_MEM_NOC 7
#define MASTER_GEM_NOC_PCIE_SNOC 8
#define MASTER_SNOC_GC_MEM_NOC 9
#define MASTER_SNOC_SF_MEM_NOC 10
#define MASTER_ECC 11
#define SLAVE_MSS_PROC_MS_MPU_CFG 12
#define SLAVE_ECC 13
#define SLAVE_GEM_NOC_SNOC 14
#define SLAVE_LLCC 15
#define SLAVE_SERVICE_GEM_NOC 16
#define MASTER_IPA_CORE 0
#define SLAVE_IPA_CORE 1
#define MASTER_LLCC 0
#define SLAVE_EBI_CH0 1
#define MASTER_CNOC_MNOC_CFG 0
#define MASTER_CAMNOC_HF0 1
#define MASTER_CAMNOC_HF1 2
#define MASTER_CAMNOC_SF 3
#define MASTER_MDP_PORT0 4
#define MASTER_MDP_PORT1 5
#define MASTER_ROTATOR 6
#define MASTER_VIDEO_P0 7
#define MASTER_VIDEO_P1 8
#define MASTER_VIDEO_PROC 9
#define SLAVE_MNOC_SF_MEM_NOC 10
#define SLAVE_MNOC_HF_MEM_NOC 11
#define SLAVE_SERVICE_MNOC 12
#define MASTER_SNOC_CFG 0
#define A1NOC_SNOC_MAS 1
#define A2NOC_SNOC_MAS 2
#define MASTER_GEM_NOC_SNOC 3
#define MASTER_PIMEM 4
#define MASTER_GIC 5
#define SLAVE_APPSS 6
#define SNOC_CNOC_SLV 7
#define SLAVE_SNOC_GEM_NOC_GC 8
#define SLAVE_SNOC_GEM_NOC_SF 9
#define SLAVE_OCIMEM 10
#define SLAVE_PIMEM 11
#define SLAVE_SERVICE_SNOC 12
#define SLAVE_PCIE_0 13
#define SLAVE_PCIE_1 14
#define SLAVE_QDSS_STM 15
#define SLAVE_TCU 16
#endif

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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Qualcomm SM8250 interconnect IDs
*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8250_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_SM8250_H
#define MASTER_A1NOC_CFG 0
#define MASTER_QSPI_0 1
#define MASTER_QUP_1 2
#define MASTER_QUP_2 3
#define MASTER_TSIF 4
#define MASTER_PCIE_2 5
#define MASTER_SDCC_4 6
#define MASTER_UFS_MEM 7
#define MASTER_USB3 8
#define MASTER_USB3_1 9
#define A1NOC_SNOC_SLV 10
#define SLAVE_ANOC_PCIE_GEM_NOC_1 11
#define SLAVE_SERVICE_A1NOC 12
#define MASTER_A2NOC_CFG 0
#define MASTER_QDSS_BAM 1
#define MASTER_QUP_0 2
#define MASTER_CNOC_A2NOC 3
#define MASTER_CRYPTO_CORE_0 4
#define MASTER_IPA 5
#define MASTER_PCIE 6
#define MASTER_PCIE_1 7
#define MASTER_QDSS_ETR 8
#define MASTER_SDCC_2 9
#define MASTER_UFS_CARD 10
#define A2NOC_SNOC_SLV 11
#define SLAVE_ANOC_PCIE_GEM_NOC 12
#define SLAVE_SERVICE_A2NOC 13
#define MASTER_NPU 0
#define SLAVE_CDSP_MEM_NOC 1
#define SNOC_CNOC_MAS 0
#define MASTER_QDSS_DAP 1
#define SLAVE_A1NOC_CFG 2
#define SLAVE_A2NOC_CFG 3
#define SLAVE_AHB2PHY_SOUTH 4
#define SLAVE_AHB2PHY_NORTH 5
#define SLAVE_AOSS 6
#define SLAVE_CAMERA_CFG 7
#define SLAVE_CLK_CTL 8
#define SLAVE_CDSP_CFG 9
#define SLAVE_RBCPR_CX_CFG 10
#define SLAVE_RBCPR_MMCX_CFG 11
#define SLAVE_RBCPR_MX_CFG 12
#define SLAVE_CRYPTO_0_CFG 13
#define SLAVE_CX_RDPM 14
#define SLAVE_DCC_CFG 15
#define SLAVE_CNOC_DDRSS 16
#define SLAVE_DISPLAY_CFG 17
#define SLAVE_GRAPHICS_3D_CFG 18
#define SLAVE_IMEM_CFG 19
#define SLAVE_IPA_CFG 20
#define SLAVE_IPC_ROUTER_CFG 21
#define SLAVE_LPASS 22
#define SLAVE_CNOC_MNOC_CFG 23
#define SLAVE_NPU_CFG 24
#define SLAVE_PCIE_0_CFG 25
#define SLAVE_PCIE_1_CFG 26
#define SLAVE_PCIE_2_CFG 27
#define SLAVE_PDM 28
#define SLAVE_PIMEM_CFG 29
#define SLAVE_PRNG 30
#define SLAVE_QDSS_CFG 31
#define SLAVE_QSPI_0 32
#define SLAVE_QUP_0 33
#define SLAVE_QUP_1 34
#define SLAVE_QUP_2 35
#define SLAVE_SDCC_2 36
#define SLAVE_SDCC_4 37
#define SLAVE_SNOC_CFG 38
#define SLAVE_TCSR 39
#define SLAVE_TLMM_NORTH 40
#define SLAVE_TLMM_SOUTH 41
#define SLAVE_TLMM_WEST 42
#define SLAVE_TSIF 43
#define SLAVE_UFS_CARD_CFG 44
#define SLAVE_UFS_MEM_CFG 45
#define SLAVE_USB3 46
#define SLAVE_USB3_1 47
#define SLAVE_VENUS_CFG 48
#define SLAVE_VSENSE_CTRL_CFG 49
#define SLAVE_CNOC_A2NOC 50
#define SLAVE_SERVICE_CNOC 51
#define MASTER_CNOC_DC_NOC 0
#define SLAVE_LLCC_CFG 1
#define SLAVE_GEM_NOC_CFG 2
#define MASTER_GPU_TCU 0
#define MASTER_SYS_TCU 1
#define MASTER_AMPSS_M0 2
#define MASTER_GEM_NOC_CFG 3
#define MASTER_COMPUTE_NOC 4
#define MASTER_GRAPHICS_3D 5
#define MASTER_MNOC_HF_MEM_NOC 6
#define MASTER_MNOC_SF_MEM_NOC 7
#define MASTER_ANOC_PCIE_GEM_NOC 8
#define MASTER_SNOC_GC_MEM_NOC 9
#define MASTER_SNOC_SF_MEM_NOC 10
#define SLAVE_GEM_NOC_SNOC 11
#define SLAVE_LLCC 12
#define SLAVE_MEM_NOC_PCIE_SNOC 13
#define SLAVE_SERVICE_GEM_NOC_1 14
#define SLAVE_SERVICE_GEM_NOC_2 15
#define SLAVE_SERVICE_GEM_NOC 16
#define MASTER_IPA_CORE 0
#define SLAVE_IPA_CORE 1
#define MASTER_LLCC 0
#define SLAVE_EBI_CH0 1
#define MASTER_CNOC_MNOC_CFG 0
#define MASTER_CAMNOC_HF 1
#define MASTER_CAMNOC_ICP 2
#define MASTER_CAMNOC_SF 3
#define MASTER_VIDEO_P0 4
#define MASTER_VIDEO_P1 5
#define MASTER_VIDEO_PROC 6
#define MASTER_MDP_PORT0 7
#define MASTER_MDP_PORT1 8
#define MASTER_ROTATOR 9
#define SLAVE_MNOC_HF_MEM_NOC 10
#define SLAVE_MNOC_SF_MEM_NOC 11
#define SLAVE_SERVICE_MNOC 12
#define MASTER_NPU_SYS 0
#define MASTER_NPU_CDP 1
#define MASTER_NPU_NOC_CFG 2
#define SLAVE_NPU_CAL_DP0 3
#define SLAVE_NPU_CAL_DP1 4
#define SLAVE_NPU_CP 5
#define SLAVE_NPU_INT_DMA_BWMON_CFG 6
#define SLAVE_NPU_DPM 7
#define SLAVE_ISENSE_CFG 8
#define SLAVE_NPU_LLM_CFG 9
#define SLAVE_NPU_TCM 10
#define SLAVE_NPU_COMPUTE_NOC 11
#define SLAVE_SERVICE_NPU_NOC 12
#define MASTER_SNOC_CFG 0
#define A1NOC_SNOC_MAS 1
#define A2NOC_SNOC_MAS 2
#define MASTER_GEM_NOC_SNOC 3
#define MASTER_GEM_NOC_PCIE_SNOC 4
#define MASTER_PIMEM 5
#define MASTER_GIC 6
#define SLAVE_APPSS 7
#define SNOC_CNOC_SLV 8
#define SLAVE_SNOC_GEM_NOC_GC 9
#define SLAVE_SNOC_GEM_NOC_SF 10
#define SLAVE_OCIMEM 11
#define SLAVE_PIMEM 12
#define SLAVE_SERVICE_SNOC 13
#define SLAVE_PCIE_0 14
#define SLAVE_PCIE_1 15
#define SLAVE_PCIE_2 16
#define SLAVE_QDSS_STM 17
#define SLAVE_TCU 18
#endif

24
include/linux/interconnect-provider.h
View File

@ -14,6 +14,17 @@
struct icc_node;
struct of_phandle_args;
/**
* struct icc_node_data - icc node data
*
* @node: icc node
* @tag: tag
*/
struct icc_node_data {
struct icc_node *node;
u32 tag;
};
/**
* struct icc_onecell_data - driver data for onecell interconnect providers
*
@ -38,7 +49,9 @@ struct icc_node *of_icc_xlate_onecell(struct of_phandle_args *spec,
* @aggregate: pointer to device specific aggregate operation function
* @pre_aggregate: pointer to device specific function that is called
* before the aggregation begins (optional)
* @get_bw: pointer to device specific function to get current bandwidth
* @xlate: provider-specific callback for mapping nodes from phandle arguments
* @xlate_extended: vendor-specific callback for mapping node data from phandle arguments
* @dev: the device this interconnect provider belongs to
* @users: count of active users
* @inter_set: whether inter-provider pairs will be configured with @set
@ -51,7 +64,9 @@ struct icc_provider {
int (*aggregate)(struct icc_node *node, u32 tag, u32 avg_bw,
u32 peak_bw, u32 *agg_avg, u32 *agg_peak);
void (*pre_aggregate)(struct icc_node *node);
int (*get_bw)(struct icc_node *node, u32 *avg, u32 *peak);
struct icc_node* (*xlate)(struct of_phandle_args *spec, void *data);
struct icc_node_data* (*xlate_extended)(struct of_phandle_args *spec, void *data);
struct device *dev;
int users;
bool inter_set;
@ -73,6 +88,8 @@ struct icc_provider {
* @req_list: a list of QoS constraint requests associated with this node
* @avg_bw: aggregated value of average bandwidth requests from all consumers
* @peak_bw: aggregated value of peak bandwidth requests from all consumers
* @init_avg: average bandwidth value that is read from the hardware during init
* @init_peak: peak bandwidth value that is read from the hardware during init
* @data: pointer to private data
*/
struct icc_node {
@ -89,6 +106,8 @@ struct icc_node {
struct hlist_head req_list;
u32 avg_bw;
u32 peak_bw;
u32 init_avg;
u32 init_peak;
void *data;
};
@ -105,7 +124,8 @@ void icc_node_del(struct icc_node *node);
int icc_nodes_remove(struct icc_provider *provider);
int icc_provider_add(struct icc_provider *provider);
int icc_provider_del(struct icc_provider *provider);
struct icc_node *of_icc_get_from_provider(struct of_phandle_args *spec);
struct icc_node_data *of_icc_get_from_provider(struct of_phandle_args *spec);
void icc_sync_state(struct device *dev);
#else
@ -157,7 +177,7 @@ static inline int icc_provider_del(struct icc_provider *provider)
return -ENOTSUPP;
}
static inline struct icc_node *of_icc_get_from_provider(struct of_phandle_args *spec)
static inline struct icc_node_data *of_icc_get_from_provider(struct of_phandle_args *spec)
{
return ERR_PTR(-ENOTSUPP);
}

22
include/linux/interconnect.h
View File

@ -23,6 +23,28 @@
struct icc_path;
struct device;
/**
* struct icc_bulk_data - Data used for bulk icc operations.
*
* @path: reference to the interconnect path (internal use)
* @name: the name from the "interconnect-names" DT property
* @avg_bw: average bandwidth in icc units
* @peak_bw: peak bandwidth in icc units
*/
struct icc_bulk_data {
struct icc_path *path;
const char *name;
u32 avg_bw;
u32 peak_bw;
};
int __must_check of_icc_bulk_get(struct device *dev, int num_paths,
struct icc_bulk_data *paths);
void icc_bulk_put(int num_paths, struct icc_bulk_data *paths);
int icc_bulk_set_bw(int num_paths, const struct icc_bulk_data *paths);
int icc_bulk_enable(int num_paths, const struct icc_bulk_data *paths);
void icc_bulk_disable(int num_paths, const struct icc_bulk_data *paths);
#if IS_ENABLED(CONFIG_INTERCONNECT)
struct icc_path *icc_get(struct device *dev, const int src_id,