iwlwifi: 802.11n add support to 8K A-MSDU Rx frames
This patch give the iwlwifi the ability to support A-MSDU up to 8K Please notice - in order to work in 8K A-MSDU ucode support is needed, version 4.44.1.19 (soon to be published). 4K A-MSDU works in current ucode version as well. Signed-off-by: Ron Rindjunsky <ron.rindjunsky@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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270243a505
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@ -646,9 +646,6 @@ struct iwl3945_eeprom {
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#define RX_FREE_BUFFERS 64
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#define RX_LOW_WATERMARK 8
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/* Size of one Rx buffer in host DRAM */
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#define IWL_RX_BUF_SIZE 3000
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/* Sizes and addresses for instruction and data memory (SRAM) in
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* 3945's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */
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#define RTC_INST_LOWER_BOUND (0x000000)
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@ -2229,7 +2229,8 @@ int iwl3945_hw_set_hw_setting(struct iwl3945_priv *priv)
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}
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priv->hw_setting.ac_queue_count = AC_NUM;
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priv->hw_setting.rx_buffer_size = IWL_RX_BUF_SIZE;
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priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE;
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priv->hw_setting.max_pkt_size = 2342;
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priv->hw_setting.tx_cmd_len = sizeof(struct iwl3945_tx_cmd);
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priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE;
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priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG;
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@ -75,6 +75,7 @@ enum iwl3945_antenna {
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* else RTS for data/management frames where MPDU is larger
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* than RTS value.
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*/
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#define IWL_RX_BUF_SIZE 3000U
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#define DEFAULT_RTS_THRESHOLD 2347U
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#define MIN_RTS_THRESHOLD 0U
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#define MAX_RTS_THRESHOLD 2347U
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@ -452,6 +453,30 @@ union iwl3945_ht_rate_supp {
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};
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};
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#ifdef CONFIG_IWL3945_HT
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#define CFG_HT_RX_AMPDU_FACTOR_DEF (0x3)
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#define CFG_HT_MPDU_DENSITY_2USEC (0x5)
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#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_2USEC
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struct sta_ht_info {
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u8 is_ht;
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u16 rx_mimo_ps_mode;
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u16 tx_mimo_ps_mode;
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u16 control_channel;
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u8 max_amsdu_size;
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u8 ampdu_factor;
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u8 mpdu_density;
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u8 operating_mode;
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u8 supported_chan_width;
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u8 extension_chan_offset;
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u8 is_green_field;
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u8 sgf;
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u8 supp_rates[16];
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u8 tx_chan_width;
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u8 chan_width_cap;
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};
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#endif /*CONFIG_IWL3945_HT */
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#ifdef CONFIG_IWL3945_QOS
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union iwl3945_qos_capabity {
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@ -535,7 +560,8 @@ struct iwl3945_ibss_seq {
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* @ac_queue_count: # Tx queues for EDCA Access Categories (AC)
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* @tx_cmd_len: Size of Tx command (but not including frame itself)
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* @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
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* @rx_buffer_size:
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* @rx_buf_size:
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* @max_pkt_size:
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* @max_rxq_log: Log-base-2 of max_rxq_size
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* @max_stations:
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* @bcast_sta_id:
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@ -547,7 +573,8 @@ struct iwl3945_driver_hw_info {
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u16 ac_queue_count;
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u16 tx_cmd_len;
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u16 max_rxq_size;
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u32 rx_buffer_size;
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u32 rx_buf_size;
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u32 max_pkt_size;
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u16 max_rxq_log;
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u8 max_stations;
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u8 bcast_sta_id;
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@ -609,7 +609,8 @@ struct iwl4965_eeprom {
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#define RX_LOW_WATERMARK 8
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/* Size of one Rx buffer in host DRAM */
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#define IWL_RX_BUF_SIZE (4 * 1024)
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#define IWL_RX_BUF_SIZE_4K (4 * 1024)
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#define IWL_RX_BUF_SIZE_8K (8 * 1024)
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/* Sizes and addresses for instruction and data memory (SRAM) in
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* 4965's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */
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@ -1457,13 +1458,17 @@ enum {
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#define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MASK (0xC0000000) /* bits 30-31 */
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#define FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT (20)
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#define FH_RCSR_RX_CONFIG_RB_SIZE_BITSHIFT (16)
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#define FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_BITSHIFT (4)
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#define RX_RB_TIMEOUT (0x10)
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#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
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#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
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#define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
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#define IWL_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
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#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
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#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
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#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
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#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
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#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
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#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
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@ -226,6 +226,7 @@ static int iwl4965_rx_init(struct iwl4965_priv *priv, struct iwl4965_rx_queue *r
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{
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int rc;
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unsigned long flags;
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unsigned int rb_size;
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spin_lock_irqsave(&priv->lock, flags);
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rc = iwl4965_grab_nic_access(priv);
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@ -234,6 +235,11 @@ static int iwl4965_rx_init(struct iwl4965_priv *priv, struct iwl4965_rx_queue *r
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return rc;
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}
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if (iwl4965_param_amsdu_size_8K)
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rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
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else
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rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
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/* Stop Rx DMA */
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iwl4965_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
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@ -253,7 +259,7 @@ static int iwl4965_rx_init(struct iwl4965_priv *priv, struct iwl4965_rx_queue *r
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iwl4965_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
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FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
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FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
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IWL_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K |
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rb_size |
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/*0x10 << 4 | */
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(RX_QUEUE_SIZE_LOG <<
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FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
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@ -1771,7 +1777,11 @@ int iwl4965_hw_set_hw_setting(struct iwl4965_priv *priv)
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priv->hw_setting.tx_cmd_len = sizeof(struct iwl4965_tx_cmd);
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priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE;
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priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG;
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if (iwl4965_param_amsdu_size_8K)
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priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE_8K;
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else
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priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE_4K;
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priv->hw_setting.max_pkt_size = priv->hw_setting.rx_buf_size - 256;
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priv->hw_setting.max_stations = IWL4965_STATION_COUNT;
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priv->hw_setting.bcast_sta_id = IWL4965_BROADCAST_ID;
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return 0;
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@ -3619,7 +3629,7 @@ static void iwl4965_handle_data_packet(struct iwl4965_priv *priv, int is_data,
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rx_start->byte_count = amsdu->byte_count;
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rx_end = (__le32 *) (((u8 *) hdr) + len);
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}
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if (len > IWL_RX_BUF_SIZE || len < 16) {
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if (len > priv->hw_setting.max_pkt_size || len < 16) {
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IWL_WARNING("byte count out of range [16,4K]"
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" : %d\n", len);
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return;
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@ -3785,6 +3795,10 @@ void iwl4965_init_ht_hw_capab(struct ieee80211_ht_info *ht_info, int mode)
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ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
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ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
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(IWL_MIMO_PS_NONE << 2));
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if (iwl4965_param_amsdu_size_8K) {
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printk(KERN_DEBUG "iwl4965 in A-MSDU 8K support mode\n");
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ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
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}
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ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
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ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
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@ -60,6 +60,7 @@ extern struct pci_device_id iwl4965_hw_card_ids[];
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/* Module parameters accessible from iwl-*.c */
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extern int iwl4965_param_hwcrypto;
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extern int iwl4965_param_queues_num;
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extern int iwl4965_param_amsdu_size_8K;
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enum iwl4965_antenna {
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IWL_ANTENNA_DIVERSITY,
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@ -506,7 +507,6 @@ union iwl4965_ht_rate_supp {
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#ifdef CONFIG_IWL4965_HT
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#define CFG_HT_RX_AMPDU_FACTOR_DEF (0x3)
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#define HT_IE_MAX_AMSDU_SIZE_4K (0)
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#define CFG_HT_MPDU_DENSITY_2USEC (0x5)
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#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_2USEC
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@ -618,7 +618,8 @@ struct iwl4965_driver_hw_info {
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u16 ac_queue_count;
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u16 tx_cmd_len;
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u16 max_rxq_size;
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u32 rx_buffer_size;
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u32 rx_buf_size;
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u32 max_pkt_size;
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u16 max_rxq_log;
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u8 max_stations;
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u8 bcast_sta_id;
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@ -70,6 +70,7 @@ static int iwl4965_param_antenna; /* def: 0 = both antennas (use diversity) */
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int iwl4965_param_hwcrypto; /* def: using software encryption */
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static int iwl4965_param_qos_enable = 1; /* def: 1 = use quality of service */
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int iwl4965_param_queues_num = IWL_MAX_NUM_QUEUES; /* def: 16 Tx queues */
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int iwl4965_param_amsdu_size_8K; /* def: enable 8K amsdu size */
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/*
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* module name, copyright, version, etc.
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@ -3263,7 +3264,7 @@ void iwl4965_handle_data_packet_monitor(struct iwl4965_priv *priv,
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__le16 phy_flags_hw = cpu_to_le16(phy_flags);
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/* We received data from the HW, so stop the watchdog */
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if (len > IWL_RX_BUF_SIZE - sizeof(*iwl4965_rt)) {
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if (len > priv->hw_setting.rx_buf_size - sizeof(*iwl4965_rt)) {
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IWL_DEBUG_DROP("Dropping too large packet in monitor\n");
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return;
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}
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@ -4506,7 +4507,8 @@ static void iwl4965_rx_allocate(struct iwl4965_priv *priv)
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/* Alloc a new receive buffer */
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rxb->skb =
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alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
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alloc_skb(priv->hw_setting.rx_buf_size,
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__GFP_NOWARN | GFP_ATOMIC);
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if (!rxb->skb) {
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if (net_ratelimit())
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printk(KERN_CRIT DRV_NAME
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@ -4522,7 +4524,7 @@ static void iwl4965_rx_allocate(struct iwl4965_priv *priv)
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/* Get physical address of RB/SKB */
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rxb->dma_addr =
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pci_map_single(priv->pci_dev, rxb->skb->data,
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IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
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priv->hw_setting.rx_buf_size, PCI_DMA_FROMDEVICE);
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list_add_tail(&rxb->list, &rxq->rx_free);
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rxq->free_count++;
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}
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@ -4565,7 +4567,8 @@ static void iwl4965_rx_queue_free(struct iwl4965_priv *priv, struct iwl4965_rx_q
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if (rxq->pool[i].skb != NULL) {
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pci_unmap_single(priv->pci_dev,
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rxq->pool[i].dma_addr,
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IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
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priv->hw_setting.rx_buf_size,
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PCI_DMA_FROMDEVICE);
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dev_kfree_skb(rxq->pool[i].skb);
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}
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}
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@ -4616,7 +4619,8 @@ void iwl4965_rx_queue_reset(struct iwl4965_priv *priv, struct iwl4965_rx_queue *
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if (rxq->pool[i].skb != NULL) {
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pci_unmap_single(priv->pci_dev,
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rxq->pool[i].dma_addr,
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IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
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priv->hw_setting.rx_buf_size,
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PCI_DMA_FROMDEVICE);
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priv->alloc_rxb_skb--;
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dev_kfree_skb(rxq->pool[i].skb);
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rxq->pool[i].skb = NULL;
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rxq->queue[i] = NULL;
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pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
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IWL_RX_BUF_SIZE,
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priv->hw_setting.rx_buf_size,
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PCI_DMA_FROMDEVICE);
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pkt = (struct iwl4965_rx_packet *)rxb->skb->data;
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}
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pci_unmap_single(priv->pci_dev, rxb->dma_addr,
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IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
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priv->hw_setting.rx_buf_size,
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PCI_DMA_FROMDEVICE);
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spin_lock_irqsave(&rxq->lock, flags);
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list_add_tail(&rxb->list, &priv->rxq.rx_used);
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spin_unlock_irqrestore(&rxq->lock, flags);
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@ -9523,6 +9528,8 @@ MODULE_PARM_DESC(queues_num, "number of hw queues.");
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/* QoS */
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module_param_named(qos_enable, iwl4965_param_qos_enable, int, 0444);
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MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
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module_param_named(amsdu_size_8K, iwl4965_param_amsdu_size_8K, int, 0444);
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MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
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module_exit(iwl4965_exit);
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module_init(iwl4965_init);
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