mmc: renesas_sdhi_internal_dmac: fix #define RST_RESERVED_BITS
The DM_CM_RST register actually has bits 0-31 defaulting to 1s and bits
32-63 defaulting to 0s -- fix off-by-one in #define RST_RESERVED_BITS.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Fixes: 2a68ea7896
("mmc: renesas-sdhi: add support for R-Car Gen3 SDHI DMAC")
Cc: stable@vger.kernel.org # v4.14+
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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@ -45,7 +45,7 @@
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/* DM_CM_RST */
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#define RST_DTRANRST1 BIT(9)
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#define RST_DTRANRST0 BIT(8)
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#define RST_RESERVED_BITS GENMASK_ULL(32, 0)
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#define RST_RESERVED_BITS GENMASK_ULL(31, 0)
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/* DM_CM_INFO1 and DM_CM_INFO1_MASK */
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#define INFO1_CLEAR 0
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