Merge branch 'hns3-next'
Peng Li says: ==================== net: hns3: code optimizations & bugfixes for HNS3 driver This patchset includes bugfixes and code optimizations for the HNS3 ethernet controller driver ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
a01aa7680e
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@ -240,7 +240,6 @@ static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,
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tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;
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tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;
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tqp_vector->int_adapt_down = HNS3_INT_ADAPT_DOWN_START;
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tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;
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tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;
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}
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@ -2846,10 +2845,10 @@ static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
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struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
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bool rx_update, tx_update;
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if (tqp_vector->int_adapt_down > 0) {
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tqp_vector->int_adapt_down--;
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/* update param every 1000ms */
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if (time_before(jiffies,
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tqp_vector->last_jiffies + msecs_to_jiffies(1000)))
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return;
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}
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if (rx_group->coal.gl_adapt_enable) {
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rx_update = hns3_get_new_int_gl(rx_group);
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@ -2866,7 +2865,6 @@ static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
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}
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tqp_vector->last_jiffies = jiffies;
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tqp_vector->int_adapt_down = HNS3_INT_ADAPT_DOWN_START;
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}
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static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
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@ -2909,8 +2907,8 @@ static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
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if (!clean_complete)
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return budget;
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if (likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) &&
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napi_complete(napi)) {
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if (napi_complete(napi) &&
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likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
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hns3_update_new_int_gl(tqp_vector);
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hns3_mask_vector_irq(tqp_vector, 1);
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}
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@ -2993,9 +2991,10 @@ err_free_chain:
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cur_chain = head->next;
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while (cur_chain) {
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chain = cur_chain->next;
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devm_kfree(&pdev->dev, chain);
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devm_kfree(&pdev->dev, cur_chain);
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cur_chain = chain;
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}
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head->next = NULL;
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return -ENOMEM;
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}
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@ -3086,7 +3085,7 @@ static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
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ret = hns3_get_vector_ring_chain(tqp_vector,
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&vector_ring_chain);
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if (ret)
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return ret;
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goto map_ring_fail;
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ret = h->ae_algo->ops->map_ring_to_vector(h,
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tqp_vector->vector_irq, &vector_ring_chain);
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@ -3180,12 +3179,12 @@ static int hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
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hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
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if (priv->tqp_vector[i].irq_init_flag == HNS3_VECTOR_INITED) {
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(void)irq_set_affinity_hint(
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priv->tqp_vector[i].vector_irq,
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NULL);
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free_irq(priv->tqp_vector[i].vector_irq,
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&priv->tqp_vector[i]);
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if (tqp_vector->irq_init_flag == HNS3_VECTOR_INITED) {
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irq_set_affinity_notifier(tqp_vector->vector_irq,
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NULL);
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irq_set_affinity_hint(tqp_vector->vector_irq, NULL);
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free_irq(tqp_vector->vector_irq, tqp_vector);
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tqp_vector->irq_init_flag = HNS3_VECTOR_NOT_INITED;
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}
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priv->ring_data[i].ring->irq_init_flag = HNS3_VECTOR_NOT_INITED;
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@ -476,8 +476,6 @@ enum hns3_link_mode_bits {
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#define HNS3_INT_RL_MAX 0x00EC
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#define HNS3_INT_RL_ENABLE_MASK 0x40
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#define HNS3_INT_ADAPT_DOWN_START 100
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struct hns3_enet_coalesce {
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u16 int_gl;
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u8 gl_adapt_enable;
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@ -512,8 +510,6 @@ struct hns3_enet_tqp_vector {
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char name[HNAE3_INT_NAME_LEN];
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/* when 0 should adjust interrupt coalesce parameter */
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u8 int_adapt_down;
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unsigned long last_jiffies;
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} ____cacheline_internodealigned_in_smp;
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@ -420,7 +420,9 @@ struct hclge_pf_res_cmd {
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#define HCLGE_PF_VEC_NUM_M GENMASK(7, 0)
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__le16 pf_intr_vector_number;
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__le16 pf_own_fun_number;
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__le32 rsv[3];
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__le16 tx_buf_size;
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__le16 dv_buf_size;
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__le32 rsv[2];
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};
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#define HCLGE_CFG_OFFSET_S 0
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@ -839,6 +841,7 @@ struct hclge_serdes_lb_cmd {
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#define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */
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#define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */
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#define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */
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#define HCLGE_NON_DCB_ADDITIONAL_BUF 0x200 /* 512 byte */
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#define HCLGE_TYPE_CRQ 0
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#define HCLGE_TYPE_CSQ 1
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@ -26,6 +26,8 @@
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#define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
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#define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
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#define HCLGE_BUF_SIZE_UNIT 256
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static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps);
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static int hclge_init_vlan_config(struct hclge_dev *hdev);
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static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
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@ -687,6 +689,22 @@ static int hclge_query_pf_resource(struct hclge_dev *hdev)
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hdev->num_tqps = __le16_to_cpu(req->tqp_num);
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hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
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if (req->tx_buf_size)
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hdev->tx_buf_size =
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__le16_to_cpu(req->tx_buf_size) << HCLGE_BUF_UNIT_S;
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else
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hdev->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
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hdev->tx_buf_size = roundup(hdev->tx_buf_size, HCLGE_BUF_SIZE_UNIT);
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if (req->dv_buf_size)
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hdev->dv_buf_size =
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__le16_to_cpu(req->dv_buf_size) << HCLGE_BUF_UNIT_S;
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else
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hdev->dv_buf_size = HCLGE_DEFAULT_DV;
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hdev->dv_buf_size = roundup(hdev->dv_buf_size, HCLGE_BUF_SIZE_UNIT);
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if (hnae3_dev_roce_supported(hdev)) {
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hdev->roce_base_msix_offset =
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hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee),
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@ -1368,40 +1386,51 @@ static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev,
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{
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u32 shared_buf_min, shared_buf_tc, shared_std;
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int tc_num, pfc_enable_num;
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u32 shared_buf;
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u32 shared_buf, aligned_mps;
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u32 rx_priv;
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int i;
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tc_num = hclge_get_tc_num(hdev);
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pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
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aligned_mps = roundup(hdev->mps, HCLGE_BUF_SIZE_UNIT);
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if (hnae3_dev_dcb_supported(hdev))
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shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
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shared_buf_min = 2 * aligned_mps + hdev->dv_buf_size;
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else
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shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
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shared_buf_min = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF
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+ hdev->dv_buf_size;
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shared_buf_tc = pfc_enable_num * hdev->mps +
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(tc_num - pfc_enable_num) * hdev->mps / 2 +
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hdev->mps;
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shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
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shared_buf_tc = pfc_enable_num * aligned_mps +
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(tc_num - pfc_enable_num) * aligned_mps / 2 +
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aligned_mps;
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shared_std = roundup(max_t(u32, shared_buf_min, shared_buf_tc),
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HCLGE_BUF_SIZE_UNIT);
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rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
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if (rx_all <= rx_priv + shared_std)
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if (rx_all < rx_priv + shared_std)
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return false;
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shared_buf = rx_all - rx_priv;
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shared_buf = rounddown(rx_all - rx_priv, HCLGE_BUF_SIZE_UNIT);
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buf_alloc->s_buf.buf_size = shared_buf;
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buf_alloc->s_buf.self.high = shared_buf;
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buf_alloc->s_buf.self.low = 2 * hdev->mps;
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if (hnae3_dev_dcb_supported(hdev)) {
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buf_alloc->s_buf.self.high = shared_buf - hdev->dv_buf_size;
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buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
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- roundup(aligned_mps / 2, HCLGE_BUF_SIZE_UNIT);
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} else {
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buf_alloc->s_buf.self.high = aligned_mps +
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HCLGE_NON_DCB_ADDITIONAL_BUF;
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buf_alloc->s_buf.self.low =
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roundup(aligned_mps / 2, HCLGE_BUF_SIZE_UNIT);
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}
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for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
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if ((hdev->hw_tc_map & BIT(i)) &&
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(hdev->tm_info.hw_pfc_map & BIT(i))) {
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buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
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buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
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buf_alloc->s_buf.tc_thrd[i].low = aligned_mps;
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buf_alloc->s_buf.tc_thrd[i].high = 2 * aligned_mps;
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} else {
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buf_alloc->s_buf.tc_thrd[i].low = 0;
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buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
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buf_alloc->s_buf.tc_thrd[i].high = aligned_mps;
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}
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}
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@ -1419,11 +1448,11 @@ static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
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for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
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struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
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if (total_size < HCLGE_DEFAULT_TX_BUF)
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if (total_size < hdev->tx_buf_size)
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return -ENOMEM;
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if (hdev->hw_tc_map & BIT(i))
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priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
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priv->tx_buf_size = hdev->tx_buf_size;
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else
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priv->tx_buf_size = 0;
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@ -1441,7 +1470,6 @@ static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
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static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
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struct hclge_pkt_buf_alloc *buf_alloc)
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{
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#define HCLGE_BUF_SIZE_UNIT 128
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u32 rx_all = hdev->pkt_buf_size, aligned_mps;
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int no_pfc_priv_num, pfc_priv_num;
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struct hclge_priv_buf *priv;
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@ -1467,13 +1495,16 @@ static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
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priv->enable = 1;
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if (hdev->tm_info.hw_pfc_map & BIT(i)) {
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priv->wl.low = aligned_mps;
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priv->wl.high = priv->wl.low + aligned_mps;
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priv->wl.high =
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roundup(priv->wl.low + aligned_mps,
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HCLGE_BUF_SIZE_UNIT);
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priv->buf_size = priv->wl.high +
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HCLGE_DEFAULT_DV;
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hdev->dv_buf_size;
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} else {
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priv->wl.low = 0;
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priv->wl.high = 2 * aligned_mps;
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priv->buf_size = priv->wl.high;
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priv->buf_size = priv->wl.high +
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hdev->dv_buf_size;
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}
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} else {
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priv->enable = 0;
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@ -1503,13 +1534,13 @@ static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
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priv->enable = 1;
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if (hdev->tm_info.hw_pfc_map & BIT(i)) {
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priv->wl.low = 128;
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priv->wl.low = 256;
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priv->wl.high = priv->wl.low + aligned_mps;
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priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
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priv->buf_size = priv->wl.high + hdev->dv_buf_size;
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} else {
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priv->wl.low = 0;
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priv->wl.high = aligned_mps;
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priv->buf_size = priv->wl.high;
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priv->buf_size = priv->wl.high + hdev->dv_buf_size;
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}
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}
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@ -2810,7 +2841,6 @@ static void hclge_reset(struct hclge_dev *hdev)
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*/
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ae_dev->reset_type = hdev->reset_type;
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hdev->reset_count++;
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hdev->last_reset_time = jiffies;
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/* perform reset of the stack & ae device for a client */
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ret = hclge_notify_roce_client(hdev, HNAE3_DOWN_CLIENT);
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if (ret)
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@ -2873,6 +2903,10 @@ static void hclge_reset(struct hclge_dev *hdev)
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if (ret)
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goto err_reset;
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hdev->last_reset_time = jiffies;
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hdev->reset_fail_cnt = 0;
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ae_dev->reset_type = HNAE3_NONE_RESET;
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return;
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err_reset_lock:
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@ -7377,19 +7411,6 @@ static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
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return ret;
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}
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ret = hclge_get_cap(hdev);
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if (ret) {
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dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
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ret);
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return ret;
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}
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ret = hclge_configure(hdev);
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if (ret) {
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dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
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return ret;
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}
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ret = hclge_map_tqp(hdev);
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if (ret) {
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dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
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@ -736,6 +736,9 @@ struct hclge_dev {
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u32 flag;
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u32 pkt_buf_size; /* Total pf buf size for tx/rx */
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u32 tx_buf_size; /* Tx buffer size for each TC */
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u32 dv_buf_size; /* Dv buffer size for each TC */
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u32 mps; /* Max packet size */
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/* vport_lock protect resource shared by vports */
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struct mutex vport_lock;
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@ -12,7 +12,7 @@
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SUPPORTED_TP | \
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PHY_10BT_FEATURES | \
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PHY_100BT_FEATURES | \
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PHY_1000BT_FEATURES)
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SUPPORTED_1000baseT_Full)
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enum hclge_mdio_c22_op_seq {
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HCLGE_MDIO_C22_WRITE = 1,
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@ -179,6 +179,10 @@ static void hclge_mac_adjust_link(struct net_device *netdev)
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int duplex, speed;
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int ret;
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/* When phy link down, do nothing */
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if (netdev->phydev->link == 0)
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return;
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speed = netdev->phydev->speed;
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duplex = netdev->phydev->duplex;
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@ -1342,6 +1342,9 @@ static int hclgevf_reset(struct hclgevf_dev *hdev)
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rtnl_unlock();
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hdev->last_reset_time = jiffies;
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ae_dev->reset_type = HNAE3_NONE_RESET;
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return ret;
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err_reset_lock:
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rtnl_unlock();
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@ -2401,9 +2404,9 @@ static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev)
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if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
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hclgevf_misc_irq_uninit(hdev);
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hclgevf_uninit_msi(hdev);
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hclgevf_pci_uninit(hdev);
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}
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hclgevf_pci_uninit(hdev);
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hclgevf_cmd_uninit(hdev);
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}
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