[libata] sata_sx4, sata_via: minor documentation updates
sata_sx4: - describe overall driver theory of operation - add a few constants that will be used in the future sata_via: - remove mention of an old-EH function that is going away Signed-off-by: Jeff Garzik <jeff@garzik.org>
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@ -30,6 +30,54 @@
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*
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*
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*/
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*/
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/*
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Theory of operation
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-------------------
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The SX4 (PDC20621) chip features a single Host DMA (HDMA) copy
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engine, DIMM memory, and four ATA engines (one per SATA port).
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Data is copied to/from DIMM memory by the HDMA engine, before
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handing off to one (or more) of the ATA engines. The ATA
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engines operate solely on DIMM memory.
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The SX4 behaves like a PATA chip, with no SATA controls or
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knowledge whatsoever, leading to the presumption that
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PATA<->SATA bridges exist on SX4 boards, external to the
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PDC20621 chip itself.
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The chip is quite capable, supporting an XOR engine and linked
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hardware commands (permits a string to transactions to be
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submitted and waited-on as a single unit), and an optional
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microprocessor.
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The limiting factor is largely software. This Linux driver was
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written to multiplex the single HDMA engine to copy disk
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transactions into a fixed DIMM memory space, from where an ATA
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engine takes over. As a result, each WRITE looks like this:
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submit HDMA packet to hardware
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hardware copies data from system memory to DIMM
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hardware raises interrupt
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submit ATA packet to hardware
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hardware executes ATA WRITE command, w/ data in DIMM
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hardware raises interrupt
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and each READ looks like this:
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submit ATA packet to hardware
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hardware executes ATA READ command, w/ data in DIMM
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hardware raises interrupt
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submit HDMA packet to hardware
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hardware copies data from DIMM to system memory
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hardware raises interrupt
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This is a very slow, lock-step way of doing things that can
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certainly be improved by motivated kernel hackers.
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*/
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#include <linux/kernel.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/pci.h>
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@ -58,6 +106,8 @@ enum {
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PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
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PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
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PDC_HDMA_CTLSTAT = 0x12C, /* Host DMA control / status */
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PDC_HDMA_CTLSTAT = 0x12C, /* Host DMA control / status */
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PDC_CTLSTAT = 0x60, /* IDEn control / status */
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PDC_20621_SEQCTL = 0x400,
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PDC_20621_SEQCTL = 0x400,
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PDC_20621_SEQMASK = 0x480,
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PDC_20621_SEQMASK = 0x480,
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PDC_20621_GENERAL_CTL = 0x484,
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PDC_20621_GENERAL_CTL = 0x484,
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@ -89,6 +139,7 @@ enum {
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PDC_MASK_INT = (1 << 10), /* HDMA/ATA mask int */
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PDC_MASK_INT = (1 << 10), /* HDMA/ATA mask int */
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PDC_RESET = (1 << 11), /* HDMA/ATA reset */
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PDC_RESET = (1 << 11), /* HDMA/ATA reset */
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PDC_DMA_ENABLE = (1 << 7), /* DMA start/stop */
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PDC_MAX_HDMA = 32,
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PDC_MAX_HDMA = 32,
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PDC_HDMA_Q_MASK = (PDC_MAX_HDMA - 1),
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PDC_HDMA_Q_MASK = (PDC_MAX_HDMA - 1),
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@ -303,9 +303,7 @@ static int vt6420_prereset(struct ata_port *ap, unsigned long deadline)
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if (!(ap->pflags & ATA_PFLAG_LOADING))
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if (!(ap->pflags & ATA_PFLAG_LOADING))
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goto skip_scr;
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goto skip_scr;
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/* Resume phy. This is the old resume sequence from
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/* Resume phy. This is the old SATA resume sequence */
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* __sata_phy_reset().
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*/
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svia_scr_write(ap, SCR_CONTROL, 0x300);
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svia_scr_write(ap, SCR_CONTROL, 0x300);
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svia_scr_read(ap, SCR_CONTROL); /* flush */
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svia_scr_read(ap, SCR_CONTROL); /* flush */
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