drm/i915: split PCI IDs out into i915_drm.h v4
For use by userspace (at some point in the future) and other kernel code.
v2: move PCI IDs to uabi (Chris)
move PCI IDs to drm/ (Dave)
v3: fixup Quanta detection - needs to come first (Daniel)
v4: fix up PCI match structure init for easier use by userspace (Chris)
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Jesse Barnes
Daniel Vetter
parent
fac15c1082
commit
a0a1807544
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@ -157,25 +157,6 @@ MODULE_PARM_DESC(prefault_disable,
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static struct drm_driver driver;
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extern int intel_agp_enabled;
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#define INTEL_VGA_DEVICE(id, info) { \
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.class = PCI_BASE_CLASS_DISPLAY << 16, \
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.class_mask = 0xff0000, \
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.vendor = 0x8086, \
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.device = id, \
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.subvendor = PCI_ANY_ID, \
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.subdevice = PCI_ANY_ID, \
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.driver_data = (unsigned long) info }
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#define INTEL_QUANTA_VGA_DEVICE(info) { \
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.class = PCI_BASE_CLASS_DISPLAY << 16, \
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.class_mask = 0xff0000, \
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.vendor = 0x8086, \
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.device = 0x16a, \
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.subvendor = 0x152d, \
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.subdevice = 0x8990, \
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.driver_data = (unsigned long) info }
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static const struct intel_device_info intel_i830_info = {
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.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
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.has_overlay = 1, .overlay_needs_physical = 1,
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@ -350,118 +331,41 @@ static const struct intel_device_info intel_haswell_m_info = {
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.has_vebox_ring = 1,
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};
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/*
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* Make sure any device matches here are from most specific to most
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* general. For example, since the Quanta match is based on the subsystem
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* and subvendor IDs, we need it to come before the more general IVB
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* PCI ID matches, otherwise we'll use the wrong info struct above.
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*/
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#define INTEL_PCI_IDS \
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INTEL_I830_IDS(&intel_i830_info), \
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INTEL_I845G_IDS(&intel_845g_info), \
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INTEL_I85X_IDS(&intel_i85x_info), \
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INTEL_I865G_IDS(&intel_i865g_info), \
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INTEL_I915G_IDS(&intel_i915g_info), \
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INTEL_I915GM_IDS(&intel_i915gm_info), \
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INTEL_I945G_IDS(&intel_i945g_info), \
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INTEL_I945GM_IDS(&intel_i945gm_info), \
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INTEL_I965G_IDS(&intel_i965g_info), \
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INTEL_G33_IDS(&intel_g33_info), \
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INTEL_I965GM_IDS(&intel_i965gm_info), \
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INTEL_GM45_IDS(&intel_gm45_info), \
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INTEL_G45_IDS(&intel_g45_info), \
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INTEL_PINEVIEW_IDS(&intel_pineview_info), \
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INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \
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INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \
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INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \
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INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \
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INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
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INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \
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INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \
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INTEL_HSW_D_IDS(&intel_haswell_d_info), \
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INTEL_HSW_M_IDS(&intel_haswell_m_info), \
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INTEL_VLV_M_IDS(&intel_valleyview_m_info), \
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INTEL_VLV_D_IDS(&intel_valleyview_d_info)
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static const struct pci_device_id pciidlist[] = { /* aka */
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INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
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INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
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INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
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INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
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INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
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INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
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INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
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INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
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INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
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INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
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INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
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INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
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INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
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INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
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INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
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INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
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INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
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INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
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INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
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INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
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INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
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INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
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INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
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INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
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INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
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INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
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INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
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INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
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INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
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INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
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INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
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INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
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INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
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INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
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INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
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INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
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INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
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INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
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INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
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INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
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INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
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INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
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INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
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INTEL_QUANTA_VGA_DEVICE(&intel_ivybridge_q_info), /* Quanta transcode */
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INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
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INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
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INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
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INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT3 desktop */
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INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
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INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
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INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT3 server */
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INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
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INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
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INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
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INTEL_VGA_DEVICE(0x040B, &intel_haswell_d_info), /* GT1 reserved */
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INTEL_VGA_DEVICE(0x041B, &intel_haswell_d_info), /* GT2 reserved */
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INTEL_VGA_DEVICE(0x042B, &intel_haswell_d_info), /* GT3 reserved */
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INTEL_VGA_DEVICE(0x040E, &intel_haswell_d_info), /* GT1 reserved */
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INTEL_VGA_DEVICE(0x041E, &intel_haswell_d_info), /* GT2 reserved */
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INTEL_VGA_DEVICE(0x042E, &intel_haswell_d_info), /* GT3 reserved */
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INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
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INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
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INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT3 desktop */
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INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
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INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
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INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT3 server */
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INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
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INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
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INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT3 mobile */
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INTEL_VGA_DEVICE(0x0C0B, &intel_haswell_d_info), /* SDV GT1 reserved */
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INTEL_VGA_DEVICE(0x0C1B, &intel_haswell_d_info), /* SDV GT2 reserved */
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INTEL_VGA_DEVICE(0x0C2B, &intel_haswell_d_info), /* SDV GT3 reserved */
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INTEL_VGA_DEVICE(0x0C0E, &intel_haswell_d_info), /* SDV GT1 reserved */
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INTEL_VGA_DEVICE(0x0C1E, &intel_haswell_d_info), /* SDV GT2 reserved */
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INTEL_VGA_DEVICE(0x0C2E, &intel_haswell_d_info), /* SDV GT3 reserved */
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INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
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INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
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INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT3 desktop */
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INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
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INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
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INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT3 server */
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INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
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INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
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INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT3 mobile */
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INTEL_VGA_DEVICE(0x0A0B, &intel_haswell_d_info), /* ULT GT1 reserved */
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INTEL_VGA_DEVICE(0x0A1B, &intel_haswell_d_info), /* ULT GT2 reserved */
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INTEL_VGA_DEVICE(0x0A2B, &intel_haswell_d_info), /* ULT GT3 reserved */
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INTEL_VGA_DEVICE(0x0A0E, &intel_haswell_m_info), /* ULT GT1 reserved */
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INTEL_VGA_DEVICE(0x0A1E, &intel_haswell_m_info), /* ULT GT2 reserved */
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INTEL_VGA_DEVICE(0x0A2E, &intel_haswell_m_info), /* ULT GT3 reserved */
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INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
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INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
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INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT3 desktop */
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INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
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INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
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INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT3 server */
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INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
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INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
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INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT3 mobile */
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INTEL_VGA_DEVICE(0x0D0B, &intel_haswell_d_info), /* CRW GT1 reserved */
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INTEL_VGA_DEVICE(0x0D1B, &intel_haswell_d_info), /* CRW GT2 reserved */
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INTEL_VGA_DEVICE(0x0D2B, &intel_haswell_d_info), /* CRW GT3 reserved */
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INTEL_VGA_DEVICE(0x0D0E, &intel_haswell_d_info), /* CRW GT1 reserved */
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INTEL_VGA_DEVICE(0x0D1E, &intel_haswell_d_info), /* CRW GT2 reserved */
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INTEL_VGA_DEVICE(0x0D2E, &intel_haswell_d_info), /* CRW GT3 reserved */
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INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
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INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info),
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INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info),
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INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info),
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INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
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INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
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INTEL_PCI_IDS,
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{0, 0, 0}
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};
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@ -26,6 +26,7 @@
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#ifndef _I915_DRM_H_
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#define _I915_DRM_H_
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#include <drm/i915_pciids.h>
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#include <uapi/drm/i915_drm.h>
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/* For use by IPS driver */
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@ -34,4 +35,5 @@ extern bool i915_gpu_raise(void);
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extern bool i915_gpu_lower(void);
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extern bool i915_gpu_busy(void);
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extern bool i915_gpu_turbo_disable(void);
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#endif /* _I915_DRM_H_ */
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@ -0,0 +1,211 @@
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/*
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* Copyright 2013 Intel Corporation
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _I915_PCIIDS_H
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#define _I915_PCIIDS_H
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/*
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* A pci_device_id struct {
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* __u32 vendor, device;
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* __u32 subvendor, subdevice;
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* __u32 class, class_mask;
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* kernel_ulong_t driver_data;
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* };
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* Don't use C99 here because "class" is reserved and we want to
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* give userspace flexibility.
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*/
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#define INTEL_VGA_DEVICE(id, info) { \
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0x8086, id, \
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~0, ~0, \
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0x030000, 0xff0000, \
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(unsigned long) info }
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#define INTEL_QUANTA_VGA_DEVICE(info) { \
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0x8086, 0x16a, \
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0x152d, 0x8990, \
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0x030000, 0xff0000, \
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(unsigned long) info }
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#define INTEL_I830_IDS(info) \
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INTEL_VGA_DEVICE(0x3577, info)
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#define INTEL_I845G_IDS(info) \
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INTEL_VGA_DEVICE(0x2562, info)
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#define INTEL_I85X_IDS(info) \
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INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \
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INTEL_VGA_DEVICE(0x358e, info)
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#define INTEL_I865G_IDS(info) \
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INTEL_VGA_DEVICE(0x2572, info) /* I865_G */
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#define INTEL_I915G_IDS(info) \
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INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \
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INTEL_VGA_DEVICE(0x258a, info) /* E7221_G */
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#define INTEL_I915GM_IDS(info) \
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INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */
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#define INTEL_I945G_IDS(info) \
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INTEL_VGA_DEVICE(0x2772, info) /* I945_G */
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#define INTEL_I945GM_IDS(info) \
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INTEL_VGA_DEVICE(0x27a2, info), /* I945_GM */ \
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INTEL_VGA_DEVICE(0x27ae, info) /* I945_GME */
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#define INTEL_I965G_IDS(info) \
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INTEL_VGA_DEVICE(0x2972, info), /* I946_GZ */ \
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INTEL_VGA_DEVICE(0x2982, info), /* G35_G */ \
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INTEL_VGA_DEVICE(0x2992, info), /* I965_Q */ \
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INTEL_VGA_DEVICE(0x29a2, info) /* I965_G */
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#define INTEL_G33_IDS(info) \
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INTEL_VGA_DEVICE(0x29b2, info), /* Q35_G */ \
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INTEL_VGA_DEVICE(0x29c2, info), /* G33_G */ \
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INTEL_VGA_DEVICE(0x29d2, info) /* Q33_G */
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#define INTEL_I965GM_IDS(info) \
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INTEL_VGA_DEVICE(0x2a02, info), /* I965_GM */ \
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INTEL_VGA_DEVICE(0x2a12, info) /* I965_GME */
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#define INTEL_GM45_IDS(info) \
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INTEL_VGA_DEVICE(0x2a42, info) /* GM45_G */
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#define INTEL_G45_IDS(info) \
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INTEL_VGA_DEVICE(0x2e02, info), /* IGD_E_G */ \
|
||||
INTEL_VGA_DEVICE(0x2e12, info), /* Q45_G */ \
|
||||
INTEL_VGA_DEVICE(0x2e22, info), /* G45_G */ \
|
||||
INTEL_VGA_DEVICE(0x2e32, info), /* G41_G */ \
|
||||
INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \
|
||||
INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */
|
||||
|
||||
#define INTEL_PINEVIEW_IDS(info) \
|
||||
INTEL_VGA_DEVICE(0xa001, info), \
|
||||
INTEL_VGA_DEVICE(0xa011, info)
|
||||
|
||||
#define INTEL_IRONLAKE_D_IDS(info) \
|
||||
INTEL_VGA_DEVICE(0x0042, info)
|
||||
|
||||
#define INTEL_IRONLAKE_M_IDS(info) \
|
||||
INTEL_VGA_DEVICE(0x0046, info)
|
||||
|
||||
#define INTEL_SNB_D_IDS(info) \
|
||||
INTEL_VGA_DEVICE(0x0102, info), \
|
||||
INTEL_VGA_DEVICE(0x0112, info), \
|
||||
INTEL_VGA_DEVICE(0x0122, info), \
|
||||
INTEL_VGA_DEVICE(0x010A, info)
|
||||
|
||||
#define INTEL_SNB_M_IDS(info) \
|
||||
INTEL_VGA_DEVICE(0x0106, info), \
|
||||
INTEL_VGA_DEVICE(0x0116, info), \
|
||||
INTEL_VGA_DEVICE(0x0126, info)
|
||||
|
||||
#define INTEL_IVB_M_IDS(info) \
|
||||
INTEL_VGA_DEVICE(0x0156, info), /* GT1 mobile */ \
|
||||
INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */
|
||||
|
||||
#define INTEL_IVB_D_IDS(info) \
|
||||
INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \
|
||||
INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \
|
||||
INTEL_VGA_DEVICE(0x015a, info), /* GT1 server */ \
|
||||
INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */
|
||||
|
||||
#define INTEL_IVB_Q_IDS(info) \
|
||||
INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
|
||||
|
||||
#define INTEL_HSW_D_IDS(info) \
|
||||
INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
|
||||
INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
|
||||
INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
|
||||
INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \
|
||||
INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
|
||||
INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
|
||||
INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
|
||||
INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
|
||||
INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
|
||||
INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
|
||||
INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
|
||||
INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
|
||||
INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
|
||||
INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
|
||||
INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
|
||||
INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
|
||||
INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
|
||||
INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
|
||||
INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
|
||||
INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
|
||||
INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
|
||||
INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
|
||||
INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
|
||||
INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
|
||||
INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
|
||||
INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
|
||||
INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
|
||||
INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
|
||||
INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
|
||||
INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
|
||||
INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
|
||||
INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
|
||||
INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
|
||||
INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
|
||||
INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
|
||||
INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
|
||||
INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
|
||||
INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
|
||||
INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
|
||||
INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
|
||||
INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
|
||||
INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
|
||||
INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
|
||||
INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
|
||||
INTEL_VGA_DEVICE(0x0D2E, info) /* CRW GT3 reserved */ \
|
||||
|
||||
#define INTEL_HSW_M_IDS(info) \
|
||||
INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
|
||||
INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
|
||||
INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
|
||||
INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
|
||||
INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
|
||||
INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
|
||||
INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
|
||||
INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
|
||||
INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
|
||||
INTEL_VGA_DEVICE(0x0A0E, info), /* ULT GT1 reserved */ \
|
||||
INTEL_VGA_DEVICE(0x0A1E, info), /* ULT GT2 reserved */ \
|
||||
INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
|
||||
INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
|
||||
INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
|
||||
INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */
|
||||
|
||||
#define INTEL_VLV_M_IDS(info) \
|
||||
INTEL_VGA_DEVICE(0x0f30, info), \
|
||||
INTEL_VGA_DEVICE(0x0f31, info), \
|
||||
INTEL_VGA_DEVICE(0x0f32, info), \
|
||||
INTEL_VGA_DEVICE(0x0f33, info), \
|
||||
INTEL_VGA_DEVICE(0x0157, info)
|
||||
|
||||
#define INTEL_VLV_D_IDS(info) \
|
||||
INTEL_VGA_DEVICE(0x0155, info)
|
||||
|
||||
#endif /* _I915_PCIIDS_H */
|
||||
Loading…
Reference in New Issue