From a0b381fafffaf07c939524c7708a270023d1ad95 Mon Sep 17 00:00:00 2001 From: Ryo Kodama Date: Thu, 20 Apr 2017 02:46:38 +0900 Subject: [PATCH] clk: renesas: r8a7796: Add PWM clock This patch adds PWM clock for PWM. Signed-off-by: Ryo Kodama Signed-off-by: Takeshi Kihara Signed-off-by: Yoshihiro Kaneko [geert: Correct parent clock] Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r8a7796-cpg-mssr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index 5c95e636a8d6..ab8ad5e6f537 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -156,6 +156,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { DEF_MOD("hscif1", 519, R8A7796_CLK_S3D1), DEF_MOD("hscif0", 520, R8A7796_CLK_S3D1), DEF_MOD("thermal", 522, R8A7796_CLK_CP), + DEF_MOD("pwm", 523, R8A7796_CLK_S0D12), DEF_MOD("fcpvd2", 601, R8A7796_CLK_S0D2), DEF_MOD("fcpvd1", 602, R8A7796_CLK_S0D2), DEF_MOD("fcpvd0", 603, R8A7796_CLK_S0D2),