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ARM64: dts: Add PSCI cpuidle support for MSM8916 

Add device bindings for CPUs to suspend using PSCI as the enable-method.

Cc: <devicetree@vger.kernel.org>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Tested-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This commit is contained in:
Lina Iyer 2016-03-01 14:15:30 -07:00 committed by Andy Gross
parent 3f452fe71f
commit a0df399fee
1 changed files with 24 additions and 0 deletions
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24
arch/arm64/boot/dts/qcom/msm8916.dtsi
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@ -62,6 +62,8 @@
compatible = "arm,cortex-a53", "arm,armv8"; compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0>; reg = <0x0>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SPC>;
}; };
CPU1: cpu@1 { CPU1: cpu@1 {
@ -69,6 +71,8 @@
compatible = "arm,cortex-a53", "arm,armv8"; compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x1>; reg = <0x1>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SPC>;
}; };
CPU2: cpu@2 { CPU2: cpu@2 {
@ -76,6 +80,8 @@
compatible = "arm,cortex-a53", "arm,armv8"; compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x2>; reg = <0x2>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SPC>;
}; };
CPU3: cpu@3 { CPU3: cpu@3 {
@ -83,12 +89,30 @@
compatible = "arm,cortex-a53", "arm,armv8"; compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x3>; reg = <0x3>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SPC>;
}; };
L2_0: l2-cache { L2_0: l2-cache {
compatible = "cache"; compatible = "cache";
cache-level = <2>; cache-level = <2>;
}; };
idle-states {
CPU_SPC: spc {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x40000002>;
entry-latency-us = <130>;
exit-latency-us = <150>;
min-residency-us = <2000>;
local-timer-stop;
};
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
}; };
timer { timer {