[SCSI] be2iscsi: Fix Template HDR support for Dual Chute mode
Template HDR is created for each chute which has iSCSI Protocol loaded. For BE-X family iSCSI protocol is loaded only on single chute. Signed-off-by: John Soni Jose <sony.john-n@emulex.com> Signed-off-by: Jayamohan Kallickal <jayamohan.kallickal@emulex.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
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@ -2539,8 +2539,6 @@ static void beiscsi_find_mem_req(struct beiscsi_hba *phba)
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phba->params.icds_per_ctrl;
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phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) *
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phba->params.num_sge_per_io * phba->params.icds_per_ctrl;
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phba->mem_req[HWI_MEM_TEMPLATE_HDR] = phba->params.cxns_per_ctrl *
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BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE;
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for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
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if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
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@ -2564,6 +2562,12 @@ static void beiscsi_find_mem_req(struct beiscsi_hba *phba)
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phba, ulp_num) *
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sizeof(struct phys_addr));
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mem_descr_index = (HWI_MEM_TEMPLATE_HDR_ULP0 +
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(ulp_num * MEM_DESCR_OFFSET));
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phba->mem_req[mem_descr_index] =
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BEISCSI_GET_CID_COUNT(phba, ulp_num) *
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BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE;
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mem_descr_index = (HWI_MEM_ASYNC_HEADER_BUF_ULP0 +
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(ulp_num * MEM_DESCR_OFFSET));
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phba->mem_req[mem_descr_index] =
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@ -3405,26 +3409,31 @@ beiscsi_post_template_hdr(struct beiscsi_hba *phba)
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struct be_mem_descriptor *mem_descr;
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struct mem_array *pm_arr;
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struct be_dma_mem sgl;
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int status, i;
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int status, ulp_num;
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mem_descr = phba->init_mem;
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mem_descr += HWI_MEM_TEMPLATE_HDR;
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pm_arr = mem_descr->mem_array;
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for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
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if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
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mem_descr = (struct be_mem_descriptor *)phba->init_mem;
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mem_descr += HWI_MEM_TEMPLATE_HDR_ULP0 +
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(ulp_num * MEM_DESCR_OFFSET);
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pm_arr = mem_descr->mem_array;
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for (i = 0; i < mem_descr->num_elements; i++) {
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hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
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status = be_cmd_iscsi_post_template_hdr(&phba->ctrl, &sgl);
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hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
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status = be_cmd_iscsi_post_template_hdr(
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&phba->ctrl, &sgl);
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if (status != 0) {
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beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
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"BM_%d : Post Template HDR Failed\n");
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return status;
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if (status != 0) {
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beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
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"BM_%d : Post Template HDR Failed for"
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"ULP_%d\n", ulp_num);
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return status;
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}
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beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
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"BM_%d : Template HDR Pages Posted for"
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"ULP_%d\n", ulp_num);
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}
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}
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beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
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"BM_%d : Template HDR Pages Posted\n");
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return 0;
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}
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@ -161,7 +161,7 @@
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#define BEISCSI_MSI_NAME 20 /* size of msi_name string */
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#define MEM_DESCR_OFFSET 7
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#define MEM_DESCR_OFFSET 8
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#define BEISCSI_DEFQ_HDR 1
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#define BEISCSI_DEFQ_DATA 0
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enum be_mem_enum {
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@ -170,20 +170,21 @@ enum be_mem_enum {
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HWI_MEM_WRBH,
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HWI_MEM_SGLH,
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HWI_MEM_SGE,
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HWI_MEM_TEMPLATE_HDR,
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HWI_MEM_ASYNC_HEADER_BUF_ULP0,
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HWI_MEM_TEMPLATE_HDR_ULP0,
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HWI_MEM_ASYNC_HEADER_BUF_ULP0, /* 6 */
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HWI_MEM_ASYNC_DATA_BUF_ULP0,
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HWI_MEM_ASYNC_HEADER_RING_ULP0,
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HWI_MEM_ASYNC_DATA_RING_ULP0,
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HWI_MEM_ASYNC_HEADER_HANDLE_ULP0,
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HWI_MEM_ASYNC_DATA_HANDLE_ULP0,
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HWI_MEM_ASYNC_DATA_HANDLE_ULP0, /* 11 */
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HWI_MEM_ASYNC_PDU_CONTEXT_ULP0,
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HWI_MEM_ASYNC_HEADER_BUF_ULP1,
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HWI_MEM_TEMPLATE_HDR_ULP1,
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HWI_MEM_ASYNC_HEADER_BUF_ULP1, /* 14 */
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HWI_MEM_ASYNC_DATA_BUF_ULP1,
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HWI_MEM_ASYNC_HEADER_RING_ULP1,
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HWI_MEM_ASYNC_DATA_RING_ULP1,
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HWI_MEM_ASYNC_HEADER_HANDLE_ULP1,
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HWI_MEM_ASYNC_DATA_HANDLE_ULP1,
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HWI_MEM_ASYNC_DATA_HANDLE_ULP1, /* 19 */
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HWI_MEM_ASYNC_PDU_CONTEXT_ULP1,
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ISCSI_MEM_GLOBAL_HEADER,
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SE_MEM_MAX
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