scsi: ipr: Use pci_irq_allocate_vectors
Switch the ipr driver to use pci_alloc_irq_vectors. We need to two calls to pci_alloc_irq_vectors as ipr only supports multiple MSI-X vectors, but not multiple MSI vectors. Otherwise this cleans up a lot of cruft and allows to use a common request_irq loop for irq types, which happens to only iterate over a single line in the non MSI-X case. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Brian King <brking@linux.vnet.ibm.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
parent
68130c9948
commit
a299ee62cf
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@ -186,16 +186,16 @@ static const struct ipr_chip_cfg_t ipr_chip_cfg[] = {
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};
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static const struct ipr_chip_t ipr_chip[] = {
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{ PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
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{ PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
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{ PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
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{ PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
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{ PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E, IPR_USE_MSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
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{ PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_SNIPE, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[1] },
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{ PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[1] },
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{ PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2, IPR_USE_MSI, IPR_SIS64, IPR_MMIO, &ipr_chip_cfg[2] },
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{ PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE, IPR_USE_MSI, IPR_SIS64, IPR_MMIO, &ipr_chip_cfg[2] },
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{ PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_RATTLESNAKE, IPR_USE_MSI, IPR_SIS64, IPR_MMIO, &ipr_chip_cfg[2] }
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{ PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE, false, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
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{ PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, false, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
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{ PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN, false, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
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{ PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN, false, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
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{ PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E, true, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
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{ PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_SNIPE, false, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[1] },
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{ PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP, false, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[1] },
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{ PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2, true, IPR_SIS64, IPR_MMIO, &ipr_chip_cfg[2] },
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{ PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE, true, IPR_SIS64, IPR_MMIO, &ipr_chip_cfg[2] },
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{ PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_RATTLESNAKE, true, IPR_SIS64, IPR_MMIO, &ipr_chip_cfg[2] }
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};
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static int ipr_max_bus_speeds[] = {
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@ -9439,23 +9439,11 @@ static void ipr_free_mem(struct ipr_ioa_cfg *ioa_cfg)
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static void ipr_free_irqs(struct ipr_ioa_cfg *ioa_cfg)
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{
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struct pci_dev *pdev = ioa_cfg->pdev;
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int i;
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if (ioa_cfg->intr_flag == IPR_USE_MSI ||
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ioa_cfg->intr_flag == IPR_USE_MSIX) {
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int i;
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for (i = 0; i < ioa_cfg->nvectors; i++)
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free_irq(ioa_cfg->vectors_info[i].vec,
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&ioa_cfg->hrrq[i]);
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} else
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free_irq(pdev->irq, &ioa_cfg->hrrq[0]);
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if (ioa_cfg->intr_flag == IPR_USE_MSI) {
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pci_disable_msi(pdev);
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ioa_cfg->intr_flag &= ~IPR_USE_MSI;
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} else if (ioa_cfg->intr_flag == IPR_USE_MSIX) {
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pci_disable_msix(pdev);
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ioa_cfg->intr_flag &= ~IPR_USE_MSIX;
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}
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for (i = 0; i < ioa_cfg->nvectors; i++)
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free_irq(pci_irq_vector(pdev, i), &ioa_cfg->hrrq[i]);
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pci_free_irq_vectors(pdev);
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}
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/**
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@ -9883,45 +9871,6 @@ static void ipr_wait_for_pci_err_recovery(struct ipr_ioa_cfg *ioa_cfg)
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}
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}
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static int ipr_enable_msix(struct ipr_ioa_cfg *ioa_cfg)
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{
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struct msix_entry entries[IPR_MAX_MSIX_VECTORS];
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int i, vectors;
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for (i = 0; i < ARRAY_SIZE(entries); ++i)
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entries[i].entry = i;
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vectors = pci_enable_msix_range(ioa_cfg->pdev,
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entries, 1, ipr_number_of_msix);
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if (vectors < 0) {
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ipr_wait_for_pci_err_recovery(ioa_cfg);
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return vectors;
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}
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for (i = 0; i < vectors; i++)
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ioa_cfg->vectors_info[i].vec = entries[i].vector;
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ioa_cfg->nvectors = vectors;
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return 0;
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}
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static int ipr_enable_msi(struct ipr_ioa_cfg *ioa_cfg)
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{
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int i, vectors;
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vectors = pci_enable_msi_range(ioa_cfg->pdev, 1, ipr_number_of_msix);
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if (vectors < 0) {
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ipr_wait_for_pci_err_recovery(ioa_cfg);
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return vectors;
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}
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for (i = 0; i < vectors; i++)
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ioa_cfg->vectors_info[i].vec = ioa_cfg->pdev->irq + i;
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ioa_cfg->nvectors = vectors;
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return 0;
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}
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static void name_msi_vectors(struct ipr_ioa_cfg *ioa_cfg)
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{
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int vec_idx, n = sizeof(ioa_cfg->vectors_info[0].desc) - 1;
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@ -9934,19 +9883,20 @@ static void name_msi_vectors(struct ipr_ioa_cfg *ioa_cfg)
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}
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}
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static int ipr_request_other_msi_irqs(struct ipr_ioa_cfg *ioa_cfg)
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static int ipr_request_other_msi_irqs(struct ipr_ioa_cfg *ioa_cfg,
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struct pci_dev *pdev)
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{
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int i, rc;
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for (i = 1; i < ioa_cfg->nvectors; i++) {
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rc = request_irq(ioa_cfg->vectors_info[i].vec,
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rc = request_irq(pci_irq_vector(pdev, i),
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ipr_isr_mhrrq,
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0,
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ioa_cfg->vectors_info[i].desc,
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&ioa_cfg->hrrq[i]);
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if (rc) {
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while (--i >= 0)
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free_irq(ioa_cfg->vectors_info[i].vec,
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free_irq(pci_irq_vector(pdev, i),
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&ioa_cfg->hrrq[i]);
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return rc;
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}
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@ -9984,8 +9934,7 @@ static irqreturn_t ipr_test_intr(int irq, void *devp)
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* ipr_test_msi - Test for Message Signaled Interrupt (MSI) support.
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* @pdev: PCI device struct
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*
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* Description: The return value from pci_enable_msi_range() can not always be
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* trusted. This routine sets up and initiates a test interrupt to determine
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* Description: This routine sets up and initiates a test interrupt to determine
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* if the interrupt is received via the ipr_test_intr() service routine.
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* If the tests fails, the driver will fall back to LSI.
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*
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@ -9997,6 +9946,7 @@ static int ipr_test_msi(struct ipr_ioa_cfg *ioa_cfg, struct pci_dev *pdev)
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int rc;
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volatile u32 int_reg;
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unsigned long lock_flags = 0;
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int irq = pci_irq_vector(pdev, 0);
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ENTER;
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@ -10008,15 +9958,12 @@ static int ipr_test_msi(struct ipr_ioa_cfg *ioa_cfg, struct pci_dev *pdev)
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int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
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spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
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if (ioa_cfg->intr_flag == IPR_USE_MSIX)
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rc = request_irq(ioa_cfg->vectors_info[0].vec, ipr_test_intr, 0, IPR_NAME, ioa_cfg);
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else
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rc = request_irq(pdev->irq, ipr_test_intr, 0, IPR_NAME, ioa_cfg);
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rc = request_irq(irq, ipr_test_intr, 0, IPR_NAME, ioa_cfg);
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if (rc) {
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dev_err(&pdev->dev, "Can not assign irq %d\n", pdev->irq);
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dev_err(&pdev->dev, "Can not assign irq %d\n", irq);
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return rc;
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} else if (ipr_debug)
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dev_info(&pdev->dev, "IRQ assigned: %d\n", pdev->irq);
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dev_info(&pdev->dev, "IRQ assigned: %d\n", irq);
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writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE, ioa_cfg->regs.sense_interrupt_reg32);
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int_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
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@ -10033,10 +9980,7 @@ static int ipr_test_msi(struct ipr_ioa_cfg *ioa_cfg, struct pci_dev *pdev)
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spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
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if (ioa_cfg->intr_flag == IPR_USE_MSIX)
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free_irq(ioa_cfg->vectors_info[0].vec, ioa_cfg);
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else
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free_irq(pdev->irq, ioa_cfg);
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free_irq(irq, ioa_cfg);
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LEAVE;
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@ -10060,6 +10004,7 @@ static int ipr_probe_ioa(struct pci_dev *pdev,
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int rc = PCIBIOS_SUCCESSFUL;
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volatile u32 mask, uproc, interrupts;
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unsigned long lock_flags, driver_lock_flags;
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unsigned int irq_flag;
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ENTER;
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@ -10175,18 +10120,18 @@ static int ipr_probe_ioa(struct pci_dev *pdev,
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ipr_number_of_msix = IPR_MAX_MSIX_VECTORS;
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}
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if (ioa_cfg->ipr_chip->intr_type == IPR_USE_MSI &&
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ipr_enable_msix(ioa_cfg) == 0)
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ioa_cfg->intr_flag = IPR_USE_MSIX;
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else if (ioa_cfg->ipr_chip->intr_type == IPR_USE_MSI &&
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ipr_enable_msi(ioa_cfg) == 0)
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ioa_cfg->intr_flag = IPR_USE_MSI;
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else {
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ioa_cfg->intr_flag = IPR_USE_LSI;
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ioa_cfg->clear_isr = 1;
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ioa_cfg->nvectors = 1;
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dev_info(&pdev->dev, "Cannot enable MSI.\n");
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irq_flag = PCI_IRQ_LEGACY;
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if (ioa_cfg->ipr_chip->has_msi)
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irq_flag |= PCI_IRQ_MSI | PCI_IRQ_MSIX;
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rc = pci_alloc_irq_vectors(pdev, 1, ipr_number_of_msix, irq_flag);
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if (rc < 0) {
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ipr_wait_for_pci_err_recovery(ioa_cfg);
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goto cleanup_nomem;
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}
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ioa_cfg->nvectors = rc;
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if (!pdev->msi_enabled && !pdev->msix_enabled)
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ioa_cfg->clear_isr = 1;
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pci_set_master(pdev);
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@ -10199,33 +10144,22 @@ static int ipr_probe_ioa(struct pci_dev *pdev,
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}
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}
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if (ioa_cfg->intr_flag == IPR_USE_MSI ||
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ioa_cfg->intr_flag == IPR_USE_MSIX) {
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if (pdev->msi_enabled || pdev->msix_enabled) {
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rc = ipr_test_msi(ioa_cfg, pdev);
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if (rc == -EOPNOTSUPP) {
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switch (rc) {
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case 0:
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dev_info(&pdev->dev,
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"Request for %d MSI%ss succeeded.", ioa_cfg->nvectors,
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pdev->msix_enabled ? "-X" : "");
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break;
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case -EOPNOTSUPP:
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ipr_wait_for_pci_err_recovery(ioa_cfg);
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if (ioa_cfg->intr_flag == IPR_USE_MSI) {
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ioa_cfg->intr_flag &= ~IPR_USE_MSI;
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pci_disable_msi(pdev);
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} else if (ioa_cfg->intr_flag == IPR_USE_MSIX) {
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ioa_cfg->intr_flag &= ~IPR_USE_MSIX;
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pci_disable_msix(pdev);
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}
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pci_free_irq_vectors(pdev);
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ioa_cfg->intr_flag = IPR_USE_LSI;
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ioa_cfg->nvectors = 1;
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}
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else if (rc)
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break;
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default:
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goto out_msi_disable;
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else {
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if (ioa_cfg->intr_flag == IPR_USE_MSI)
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dev_info(&pdev->dev,
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"Request for %d MSIs succeeded with starting IRQ: %d\n",
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ioa_cfg->nvectors, pdev->irq);
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else if (ioa_cfg->intr_flag == IPR_USE_MSIX)
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dev_info(&pdev->dev,
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"Request for %d MSIXs succeeded.",
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ioa_cfg->nvectors);
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}
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}
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ipr_mask_and_clear_interrupts(ioa_cfg, ~IPR_PCII_IOA_TRANS_TO_OPER);
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spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
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if (ioa_cfg->intr_flag == IPR_USE_MSI
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|| ioa_cfg->intr_flag == IPR_USE_MSIX) {
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if (pdev->msi_enabled || pdev->msix_enabled) {
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name_msi_vectors(ioa_cfg);
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rc = request_irq(ioa_cfg->vectors_info[0].vec, ipr_isr,
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0,
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rc = request_irq(pci_irq_vector(pdev, 0), ipr_isr, 0,
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ioa_cfg->vectors_info[0].desc,
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&ioa_cfg->hrrq[0]);
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if (!rc)
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rc = ipr_request_other_msi_irqs(ioa_cfg);
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rc = ipr_request_other_msi_irqs(ioa_cfg, pdev);
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} else {
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rc = request_irq(pdev->irq, ipr_isr,
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IRQF_SHARED,
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ipr_free_mem(ioa_cfg);
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out_msi_disable:
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ipr_wait_for_pci_err_recovery(ioa_cfg);
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if (ioa_cfg->intr_flag == IPR_USE_MSI)
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pci_disable_msi(pdev);
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else if (ioa_cfg->intr_flag == IPR_USE_MSIX)
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pci_disable_msix(pdev);
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pci_free_irq_vectors(pdev);
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cleanup_nomem:
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iounmap(ipr_regs);
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out_disable:
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@ -1413,10 +1413,7 @@ struct ipr_chip_cfg_t {
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struct ipr_chip_t {
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u16 vendor;
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u16 device;
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u16 intr_type;
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#define IPR_USE_LSI 0x00
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#define IPR_USE_MSI 0x01
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#define IPR_USE_MSIX 0x02
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bool has_msi;
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u16 sis_type;
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#define IPR_SIS32 0x00
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#define IPR_SIS64 0x01
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@ -1593,11 +1590,9 @@ struct ipr_ioa_cfg {
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struct ipr_cmnd **ipr_cmnd_list;
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dma_addr_t *ipr_cmnd_list_dma;
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u16 intr_flag;
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unsigned int nvectors;
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struct {
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unsigned short vec;
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char desc[22];
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} vectors_info[IPR_MAX_MSIX_VECTORS];
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