From a2b31dd93000136d82f675952e322ec18973a348 Mon Sep 17 00:00:00 2001 From: Vivek Mahajan Date: Tue, 8 Dec 2009 13:01:15 +0530 Subject: [PATCH] powerpc/fsl: 85xx: document cache sram bindings Adds binding documentation for cache sram for the PQ3 and some QorIQ based platforms. Signed-off-by: Vivek Mahajan Signed-off-by: Kumar Gala --- .../bindings/powerpc/fsl/cache_sram.txt | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/cache_sram.txt diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cache_sram.txt b/Documentation/devicetree/bindings/powerpc/fsl/cache_sram.txt new file mode 100644 index 000000000000..781955f5217d --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/cache_sram.txt @@ -0,0 +1,20 @@ +* Freescale PQ3 and QorIQ based Cache SRAM + +Freescale's mpc85xx and some QorIQ platforms provide an +option of configuring a part of (or full) cache memory +as SRAM. This cache SRAM representation in the device +tree should be done as under:- + +Required properties: + +- compatible : should be "fsl,p2020-cache-sram" +- fsl,cache-sram-ctlr-handle : points to the L2 controller +- reg : offset and length of the cache-sram. + +Example: + +cache-sram@fff00000 { + fsl,cache-sram-ctlr-handle = <&L2>; + reg = <0 0xfff00000 0 0x10000>; + compatible = "fsl,p2020-cache-sram"; +};