Merge remote-tracking branches 'asoc/topic/atmel', 'asoc/topic/bcm2835' and 'asoc/topic/cs42xx8' into asoc-next
This commit is contained in:
Mark Brown
commit
a391dbe09a
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@ -34,6 +34,7 @@ struct ssc_device *ssc_request(unsigned int ssc_num)
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if (ssc->pdev->dev.of_node) {
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if (of_alias_get_id(ssc->pdev->dev.of_node, "ssc")
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== ssc_num) {
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ssc->pdev->id = ssc_num;
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ssc_valid = 1;
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break;
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}
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@ -285,7 +285,8 @@ static int atmel_ssc_hw_rule_rate(struct snd_pcm_hw_params *params,
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static int atmel_ssc_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
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struct platform_device *pdev = to_platform_device(dai->dev);
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struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id];
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struct atmel_pcm_dma_params *dma_params;
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int dir, dir_mask;
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int ret;
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@ -346,7 +347,8 @@ static int atmel_ssc_startup(struct snd_pcm_substream *substream,
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static void atmel_ssc_shutdown(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
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struct platform_device *pdev = to_platform_device(dai->dev);
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struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id];
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struct atmel_pcm_dma_params *dma_params;
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int dir, dir_mask;
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@ -392,7 +394,8 @@ static void atmel_ssc_shutdown(struct snd_pcm_substream *substream,
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static int atmel_ssc_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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unsigned int fmt)
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{
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struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
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struct platform_device *pdev = to_platform_device(cpu_dai->dev);
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struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id];
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ssc_p->daifmt = fmt;
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return 0;
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@ -404,7 +407,8 @@ static int atmel_ssc_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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static int atmel_ssc_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
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int div_id, int div)
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{
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struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
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struct platform_device *pdev = to_platform_device(cpu_dai->dev);
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struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id];
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switch (div_id) {
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case ATMEL_SSC_CMR_DIV:
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@ -445,7 +449,8 @@ static int atmel_ssc_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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int id = dai->id;
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struct platform_device *pdev = to_platform_device(dai->dev);
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int id = pdev->id;
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struct atmel_ssc_info *ssc_p = &ssc_info[id];
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struct ssc_device *ssc = ssc_p->ssc;
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struct atmel_pcm_dma_params *dma_params;
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@ -772,7 +777,8 @@ static int atmel_ssc_hw_params(struct snd_pcm_substream *substream,
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static int atmel_ssc_prepare(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
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struct platform_device *pdev = to_platform_device(dai->dev);
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struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id];
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struct atmel_pcm_dma_params *dma_params;
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int dir;
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@ -795,7 +801,8 @@ static int atmel_ssc_prepare(struct snd_pcm_substream *substream,
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static int atmel_ssc_trigger(struct snd_pcm_substream *substream,
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int cmd, struct snd_soc_dai *dai)
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{
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struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
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struct platform_device *pdev = to_platform_device(dai->dev);
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struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id];
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struct atmel_pcm_dma_params *dma_params;
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int dir;
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@ -824,11 +831,12 @@ static int atmel_ssc_trigger(struct snd_pcm_substream *substream,
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static int atmel_ssc_suspend(struct snd_soc_dai *cpu_dai)
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{
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struct atmel_ssc_info *ssc_p;
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struct platform_device *pdev = to_platform_device(cpu_dai->dev);
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if (!cpu_dai->active)
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return 0;
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ssc_p = &ssc_info[cpu_dai->id];
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ssc_p = &ssc_info[pdev->id];
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/* Save the status register before disabling transmit and receive */
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ssc_p->ssc_state.ssc_sr = ssc_readl(ssc_p->ssc->regs, SR);
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@ -852,12 +860,13 @@ static int atmel_ssc_suspend(struct snd_soc_dai *cpu_dai)
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static int atmel_ssc_resume(struct snd_soc_dai *cpu_dai)
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{
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struct atmel_ssc_info *ssc_p;
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struct platform_device *pdev = to_platform_device(cpu_dai->dev);
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u32 cr;
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if (!cpu_dai->active)
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return 0;
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ssc_p = &ssc_info[cpu_dai->id];
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ssc_p = &ssc_info[pdev->id];
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/* restore SSC register settings */
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ssc_writel(ssc_p->ssc->regs, TFMR, ssc_p->ssc_state.ssc_tfmr);
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@ -37,6 +37,7 @@
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <sound/core.h>
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@ -46,55 +47,6 @@
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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/* Clock registers */
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#define BCM2835_CLK_PCMCTL_REG 0x00
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#define BCM2835_CLK_PCMDIV_REG 0x04
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/* Clock register settings */
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#define BCM2835_CLK_PASSWD (0x5a000000)
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#define BCM2835_CLK_PASSWD_MASK (0xff000000)
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#define BCM2835_CLK_MASH(v) ((v) << 9)
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#define BCM2835_CLK_FLIP BIT(8)
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#define BCM2835_CLK_BUSY BIT(7)
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#define BCM2835_CLK_KILL BIT(5)
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#define BCM2835_CLK_ENAB BIT(4)
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#define BCM2835_CLK_SRC(v) (v)
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#define BCM2835_CLK_SHIFT (12)
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#define BCM2835_CLK_DIVI(v) ((v) << BCM2835_CLK_SHIFT)
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#define BCM2835_CLK_DIVF(v) (v)
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#define BCM2835_CLK_DIVF_MASK (0xFFF)
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enum {
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BCM2835_CLK_MASH_0 = 0,
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BCM2835_CLK_MASH_1,
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BCM2835_CLK_MASH_2,
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BCM2835_CLK_MASH_3,
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};
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enum {
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BCM2835_CLK_SRC_GND = 0,
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BCM2835_CLK_SRC_OSC,
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BCM2835_CLK_SRC_DBG0,
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BCM2835_CLK_SRC_DBG1,
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BCM2835_CLK_SRC_PLLA,
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BCM2835_CLK_SRC_PLLC,
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BCM2835_CLK_SRC_PLLD,
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BCM2835_CLK_SRC_HDMI,
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};
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/* Most clocks are not useable (freq = 0) */
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static const unsigned int bcm2835_clk_freq[BCM2835_CLK_SRC_HDMI+1] = {
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[BCM2835_CLK_SRC_GND] = 0,
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[BCM2835_CLK_SRC_OSC] = 19200000,
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[BCM2835_CLK_SRC_DBG0] = 0,
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[BCM2835_CLK_SRC_DBG1] = 0,
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[BCM2835_CLK_SRC_PLLA] = 0,
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[BCM2835_CLK_SRC_PLLC] = 0,
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[BCM2835_CLK_SRC_PLLD] = 500000000,
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[BCM2835_CLK_SRC_HDMI] = 0,
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};
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/* I2S registers */
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#define BCM2835_I2S_CS_A_REG 0x00
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#define BCM2835_I2S_FIFO_A_REG 0x04
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@ -158,10 +110,6 @@ static const unsigned int bcm2835_clk_freq[BCM2835_CLK_SRC_HDMI+1] = {
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#define BCM2835_I2S_INT_RXR BIT(1)
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#define BCM2835_I2S_INT_TXW BIT(0)
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/* I2S DMA interface */
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/* FIXME: Needs IOMMU support */
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#define BCM2835_VCMMU_SHIFT (0x7E000000 - 0x20000000)
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/* General device struct */
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struct bcm2835_i2s_dev {
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struct device *dev;
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@ -169,21 +117,23 @@ struct bcm2835_i2s_dev {
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unsigned int fmt;
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unsigned int bclk_ratio;
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struct regmap *i2s_regmap;
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struct regmap *clk_regmap;
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struct regmap *i2s_regmap;
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struct clk *clk;
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bool clk_prepared;
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};
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static void bcm2835_i2s_start_clock(struct bcm2835_i2s_dev *dev)
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{
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/* Start the clock if in master mode */
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unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
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if (dev->clk_prepared)
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return;
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switch (master) {
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case SND_SOC_DAIFMT_CBS_CFS:
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case SND_SOC_DAIFMT_CBS_CFM:
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regmap_update_bits(dev->clk_regmap, BCM2835_CLK_PCMCTL_REG,
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BCM2835_CLK_PASSWD_MASK | BCM2835_CLK_ENAB,
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BCM2835_CLK_PASSWD | BCM2835_CLK_ENAB);
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clk_prepare_enable(dev->clk);
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dev->clk_prepared = true;
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break;
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default:
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break;
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@ -192,28 +142,9 @@ static void bcm2835_i2s_start_clock(struct bcm2835_i2s_dev *dev)
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static void bcm2835_i2s_stop_clock(struct bcm2835_i2s_dev *dev)
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{
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uint32_t clkreg;
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int timeout = 1000;
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/* Stop clock */
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regmap_update_bits(dev->clk_regmap, BCM2835_CLK_PCMCTL_REG,
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BCM2835_CLK_PASSWD_MASK | BCM2835_CLK_ENAB,
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BCM2835_CLK_PASSWD);
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/* Wait for the BUSY flag going down */
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while (--timeout) {
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regmap_read(dev->clk_regmap, BCM2835_CLK_PCMCTL_REG, &clkreg);
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if (!(clkreg & BCM2835_CLK_BUSY))
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break;
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}
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if (!timeout) {
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/* KILL the clock */
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dev_err(dev->dev, "I2S clock didn't stop. Kill the clock!\n");
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regmap_update_bits(dev->clk_regmap, BCM2835_CLK_PCMCTL_REG,
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BCM2835_CLK_KILL | BCM2835_CLK_PASSWD_MASK,
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BCM2835_CLK_KILL | BCM2835_CLK_PASSWD);
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}
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if (dev->clk_prepared)
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clk_disable_unprepare(dev->clk);
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dev->clk_prepared = false;
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}
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static void bcm2835_i2s_clear_fifos(struct bcm2835_i2s_dev *dev,
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@ -223,8 +154,7 @@ static void bcm2835_i2s_clear_fifos(struct bcm2835_i2s_dev *dev,
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uint32_t syncval;
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uint32_t csreg;
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uint32_t i2s_active_state;
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uint32_t clkreg;
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uint32_t clk_active_state;
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bool clk_was_prepared;
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uint32_t off;
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uint32_t clr;
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@ -238,15 +168,10 @@ static void bcm2835_i2s_clear_fifos(struct bcm2835_i2s_dev *dev,
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regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &csreg);
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i2s_active_state = csreg & (BCM2835_I2S_RXON | BCM2835_I2S_TXON);
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regmap_read(dev->clk_regmap, BCM2835_CLK_PCMCTL_REG, &clkreg);
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clk_active_state = clkreg & BCM2835_CLK_ENAB;
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/* Start clock if not running */
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if (!clk_active_state) {
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regmap_update_bits(dev->clk_regmap, BCM2835_CLK_PCMCTL_REG,
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BCM2835_CLK_PASSWD_MASK | BCM2835_CLK_ENAB,
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BCM2835_CLK_PASSWD | BCM2835_CLK_ENAB);
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}
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clk_was_prepared = dev->clk_prepared;
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if (!clk_was_prepared)
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bcm2835_i2s_start_clock(dev);
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/* Stop I2S module */
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regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, off, 0);
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|
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@ -280,7 +205,7 @@ static void bcm2835_i2s_clear_fifos(struct bcm2835_i2s_dev *dev,
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dev_err(dev->dev, "I2S SYNC error!\n");
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/* Stop clock if it was not running before */
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if (!clk_active_state)
|
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if (!clk_was_prepared)
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bcm2835_i2s_stop_clock(dev);
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|
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/* Restore I2S state */
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|
|
@ -309,19 +234,9 @@ static int bcm2835_i2s_hw_params(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
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|
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unsigned int sampling_rate = params_rate(params);
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unsigned int data_length, data_delay, bclk_ratio;
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unsigned int ch1pos, ch2pos, mode, format;
|
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unsigned int mash = BCM2835_CLK_MASH_1;
|
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unsigned int divi, divf, target_frequency;
|
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int clk_src = -1;
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unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
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bool bit_master = (master == SND_SOC_DAIFMT_CBS_CFS
|
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|| master == SND_SOC_DAIFMT_CBS_CFM);
|
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|
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bool frame_master = (master == SND_SOC_DAIFMT_CBS_CFS
|
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|| master == SND_SOC_DAIFMT_CBM_CFS);
|
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uint32_t csreg;
|
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|
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/*
|
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|
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@ -343,11 +258,9 @@ static int bcm2835_i2s_hw_params(struct snd_pcm_substream *substream,
|
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
|
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data_length = 16;
|
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bclk_ratio = 40;
|
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break;
|
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case SNDRV_PCM_FORMAT_S32_LE:
|
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data_length = 32;
|
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bclk_ratio = 80;
|
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break;
|
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default:
|
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return -EINVAL;
|
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|
|
@ -356,69 +269,12 @@ static int bcm2835_i2s_hw_params(struct snd_pcm_substream *substream,
|
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/* If bclk_ratio already set, use that one. */
|
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if (dev->bclk_ratio)
|
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bclk_ratio = dev->bclk_ratio;
|
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else
|
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/* otherwise calculate a fitting block ratio */
|
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bclk_ratio = 2 * data_length;
|
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|
||||
/*
|
||||
* Clock Settings
|
||||
*
|
||||
* The target frequency of the bit clock is
|
||||
* sampling rate * frame length
|
||||
*
|
||||
* Integer mode:
|
||||
* Sampling rates that are multiples of 8000 kHz
|
||||
* can be driven by the oscillator of 19.2 MHz
|
||||
* with an integer divider as long as the frame length
|
||||
* is an integer divider of 19200000/8000=2400 as set up above.
|
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* This is no longer possible if the sampling rate
|
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* is too high (e.g. 192 kHz), because the oscillator is too slow.
|
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*
|
||||
* MASH mode:
|
||||
* For all other sampling rates, it is not possible to
|
||||
* have an integer divider. Approximate the clock
|
||||
* with the MASH module that induces a slight frequency
|
||||
* variance. To minimize that it is best to have the fastest
|
||||
* clock here. That is PLLD with 500 MHz.
|
||||
*/
|
||||
target_frequency = sampling_rate * bclk_ratio;
|
||||
clk_src = BCM2835_CLK_SRC_OSC;
|
||||
mash = BCM2835_CLK_MASH_0;
|
||||
|
||||
if (bcm2835_clk_freq[clk_src] % target_frequency == 0
|
||||
&& bit_master && frame_master) {
|
||||
divi = bcm2835_clk_freq[clk_src] / target_frequency;
|
||||
divf = 0;
|
||||
} else {
|
||||
uint64_t dividend;
|
||||
|
||||
if (!dev->bclk_ratio) {
|
||||
/*
|
||||
* Overwrite bclk_ratio, because the
|
||||
* above trick is not needed or can
|
||||
* not be used.
|
||||
*/
|
||||
bclk_ratio = 2 * data_length;
|
||||
}
|
||||
|
||||
target_frequency = sampling_rate * bclk_ratio;
|
||||
|
||||
clk_src = BCM2835_CLK_SRC_PLLD;
|
||||
mash = BCM2835_CLK_MASH_1;
|
||||
|
||||
dividend = bcm2835_clk_freq[clk_src];
|
||||
dividend <<= BCM2835_CLK_SHIFT;
|
||||
do_div(dividend, target_frequency);
|
||||
divi = dividend >> BCM2835_CLK_SHIFT;
|
||||
divf = dividend & BCM2835_CLK_DIVF_MASK;
|
||||
}
|
||||
|
||||
/* Set clock divider */
|
||||
regmap_write(dev->clk_regmap, BCM2835_CLK_PCMDIV_REG, BCM2835_CLK_PASSWD
|
||||
| BCM2835_CLK_DIVI(divi)
|
||||
| BCM2835_CLK_DIVF(divf));
|
||||
|
||||
/* Setup clock, but don't start it yet */
|
||||
regmap_write(dev->clk_regmap, BCM2835_CLK_PCMCTL_REG, BCM2835_CLK_PASSWD
|
||||
| BCM2835_CLK_MASH(mash)
|
||||
| BCM2835_CLK_SRC(clk_src));
|
||||
/* set target clock rate*/
|
||||
clk_set_rate(dev->clk, sampling_rate * bclk_ratio);
|
||||
|
||||
/* Setup the frame format */
|
||||
format = BCM2835_I2S_CHEN;
|
||||
|
|
@ -692,7 +548,7 @@ static const struct snd_soc_dai_ops bcm2835_i2s_dai_ops = {
|
|||
.trigger = bcm2835_i2s_trigger,
|
||||
.hw_params = bcm2835_i2s_hw_params,
|
||||
.set_fmt = bcm2835_i2s_set_dai_fmt,
|
||||
.set_bclk_ratio = bcm2835_i2s_set_dai_bclk_ratio
|
||||
.set_bclk_ratio = bcm2835_i2s_set_dai_bclk_ratio,
|
||||
};
|
||||
|
||||
static int bcm2835_i2s_dai_probe(struct snd_soc_dai *dai)
|
||||
|
|
@ -750,34 +606,14 @@ static bool bcm2835_i2s_precious_reg(struct device *dev, unsigned int reg)
|
|||
};
|
||||
}
|
||||
|
||||
static bool bcm2835_clk_volatile_reg(struct device *dev, unsigned int reg)
|
||||
{
|
||||
switch (reg) {
|
||||
case BCM2835_CLK_PCMCTL_REG:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
};
|
||||
}
|
||||
|
||||
static const struct regmap_config bcm2835_regmap_config[] = {
|
||||
{
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = BCM2835_I2S_GRAY_REG,
|
||||
.precious_reg = bcm2835_i2s_precious_reg,
|
||||
.volatile_reg = bcm2835_i2s_volatile_reg,
|
||||
.cache_type = REGCACHE_RBTREE,
|
||||
},
|
||||
{
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = BCM2835_CLK_PCMDIV_REG,
|
||||
.volatile_reg = bcm2835_clk_volatile_reg,
|
||||
.cache_type = REGCACHE_RBTREE,
|
||||
},
|
||||
static const struct regmap_config bcm2835_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = BCM2835_I2S_GRAY_REG,
|
||||
.precious_reg = bcm2835_i2s_precious_reg,
|
||||
.volatile_reg = bcm2835_i2s_volatile_reg,
|
||||
.cache_type = REGCACHE_RBTREE,
|
||||
};
|
||||
|
||||
static const struct snd_soc_component_driver bcm2835_i2s_component = {
|
||||
|
|
@ -787,42 +623,50 @@ static const struct snd_soc_component_driver bcm2835_i2s_component = {
|
|||
static int bcm2835_i2s_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct bcm2835_i2s_dev *dev;
|
||||
int i;
|
||||
int ret;
|
||||
struct regmap *regmap[2];
|
||||
struct resource *mem[2];
|
||||
|
||||
/* Request both ioareas */
|
||||
for (i = 0; i <= 1; i++) {
|
||||
void __iomem *base;
|
||||
|
||||
mem[i] = platform_get_resource(pdev, IORESOURCE_MEM, i);
|
||||
base = devm_ioremap_resource(&pdev->dev, mem[i]);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
regmap[i] = devm_regmap_init_mmio(&pdev->dev, base,
|
||||
&bcm2835_regmap_config[i]);
|
||||
if (IS_ERR(regmap[i]))
|
||||
return PTR_ERR(regmap[i]);
|
||||
}
|
||||
struct resource *mem;
|
||||
void __iomem *base;
|
||||
const __be32 *addr;
|
||||
dma_addr_t dma_base;
|
||||
|
||||
dev = devm_kzalloc(&pdev->dev, sizeof(*dev),
|
||||
GFP_KERNEL);
|
||||
if (!dev)
|
||||
return -ENOMEM;
|
||||
|
||||
dev->i2s_regmap = regmap[0];
|
||||
dev->clk_regmap = regmap[1];
|
||||
/* get the clock */
|
||||
dev->clk_prepared = false;
|
||||
dev->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(dev->clk)) {
|
||||
dev_err(&pdev->dev, "could not get clk: %ld\n",
|
||||
PTR_ERR(dev->clk));
|
||||
return PTR_ERR(dev->clk);
|
||||
}
|
||||
|
||||
/* Request ioarea */
|
||||
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
base = devm_ioremap_resource(&pdev->dev, mem);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
dev->i2s_regmap = devm_regmap_init_mmio(&pdev->dev, base,
|
||||
&bcm2835_regmap_config);
|
||||
if (IS_ERR(dev->i2s_regmap))
|
||||
return PTR_ERR(dev->i2s_regmap);
|
||||
|
||||
/* Set the DMA address - we have to parse DT ourselves */
|
||||
addr = of_get_address(pdev->dev.of_node, 0, NULL, NULL);
|
||||
if (!addr) {
|
||||
dev_err(&pdev->dev, "could not get DMA-register address\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
dma_base = be32_to_cpup(addr);
|
||||
|
||||
/* Set the DMA address */
|
||||
dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr =
|
||||
(dma_addr_t)mem[0]->start + BCM2835_I2S_FIFO_A_REG
|
||||
+ BCM2835_VCMMU_SHIFT;
|
||||
dma_base + BCM2835_I2S_FIFO_A_REG;
|
||||
|
||||
dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr =
|
||||
(dma_addr_t)mem[0]->start + BCM2835_I2S_FIFO_A_REG
|
||||
+ BCM2835_VCMMU_SHIFT;
|
||||
dma_base + BCM2835_I2S_FIFO_A_REG;
|
||||
|
||||
/* Set the bus width */
|
||||
dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr_width =
|
||||
|
|
|
|||
|
|
@ -44,6 +44,7 @@ struct cs42xx8_priv {
|
|||
|
||||
bool slave_mode;
|
||||
unsigned long sysclk;
|
||||
u32 tx_channels;
|
||||
};
|
||||
|
||||
/* -127.5dB to 0dB with step of 0.5dB */
|
||||
|
|
@ -257,6 +258,9 @@ static int cs42xx8_hw_params(struct snd_pcm_substream *substream,
|
|||
u32 ratio = cs42xx8->sysclk / params_rate(params);
|
||||
u32 i, fm, val, mask;
|
||||
|
||||
if (tx)
|
||||
cs42xx8->tx_channels = params_channels(params);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(cs42xx8_ratios); i++) {
|
||||
if (cs42xx8_ratios[i].ratio == ratio)
|
||||
break;
|
||||
|
|
@ -283,9 +287,11 @@ static int cs42xx8_digital_mute(struct snd_soc_dai *dai, int mute)
|
|||
{
|
||||
struct snd_soc_codec *codec = dai->codec;
|
||||
struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec);
|
||||
u8 dac_unmute = cs42xx8->tx_channels ?
|
||||
~((0x1 << cs42xx8->tx_channels) - 1) : 0;
|
||||
|
||||
regmap_update_bits(cs42xx8->regmap, CS42XX8_DACMUTE,
|
||||
CS42XX8_DACMUTE_ALL, mute ? CS42XX8_DACMUTE_ALL : 0);
|
||||
regmap_write(cs42xx8->regmap, CS42XX8_DACMUTE,
|
||||
mute ? CS42XX8_DACMUTE_ALL : dac_unmute);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue