MIPS: Netlogic: Reduce size of reset code
Update thread wakeup function to use scratch registers for saving SP and RA. Move the register restore code needed for thread 0 to the calling function. This reduces the size of code copied to the reset vector. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6910/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -197,6 +197,9 @@ FEXPORT(nlm_reset_entry)
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EXPORT(nlm_boot_siblings)
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EXPORT(nlm_boot_siblings)
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/* core L1D flush before enable threads */
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/* core L1D flush before enable threads */
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xlp_flush_l1_dcache
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xlp_flush_l1_dcache
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/* save ra and sp, will be used later (only for boot cpu) */
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dmtc0 ra, $22, 6
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dmtc0 sp, $22, 7
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/* Enable hw threads by writing to MAP_THREADMODE of the core */
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/* Enable hw threads by writing to MAP_THREADMODE of the core */
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li t0, CKSEG1ADDR(RESET_DATA_PHYS)
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li t0, CKSEG1ADDR(RESET_DATA_PHYS)
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lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */
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lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */
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@ -238,14 +241,12 @@ EXPORT(nlm_boot_siblings)
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nop
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nop
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/*
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/*
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* For the boot CPU, we have to restore registers and
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* For the boot CPU, we have to restore ra and sp and return, rest
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* return
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* of the registers will be restored by the caller
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*/
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*/
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4: dmfc0 t0, $4, 2 /* restore SP from UserLocal */
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4:
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li t1, 0xfadebeef
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dmfc0 ra, $22, 6
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dmtc0 t1, $4, 2 /* restore SP from UserLocal */
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dmfc0 sp, $22, 7
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PTR_SUBU sp, t0, PT_SIZE
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RESTORE_ALL
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jr ra
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jr ra
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nop
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nop
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EXPORT(nlm_reset_entry_end)
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EXPORT(nlm_reset_entry_end)
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@ -54,8 +54,9 @@
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.set noat
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.set noat
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.set arch=xlr /* for mfcr/mtcr, XLR is sufficient */
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.set arch=xlr /* for mfcr/mtcr, XLR is sufficient */
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FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */
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/* Called by the boot cpu to wake up its sibling threads */
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dmtc0 sp, $4, 2 /* SP saved in UserLocal */
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NESTED(xlp_boot_core0_siblings, PT_SIZE, sp)
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/* CPU register contents lost when enabling threads, save them first */
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SAVE_ALL
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SAVE_ALL
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sync
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sync
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/* find the location to which nlm_boot_siblings was relocated */
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/* find the location to which nlm_boot_siblings was relocated */
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@ -65,9 +66,12 @@ FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */
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dsubu t2, t1
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dsubu t2, t1
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daddu t2, t0
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daddu t2, t0
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/* call it */
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/* call it */
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jr t2
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jalr t2
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nop
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nop
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/* not reached */
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RESTORE_ALL
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jr ra
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nop
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END(xlp_boot_core0_siblings)
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NESTED(nlm_boot_secondary_cpus, 16, sp)
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NESTED(nlm_boot_secondary_cpus, 16, sp)
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/* Initialize CP0 Status */
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/* Initialize CP0 Status */
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