SoCFPGA DTS updates for v5.2
- Add base support for Agilex platform - Add 'cap-mmc-highspeed' Stratix10 and 32-bit SoCFPGA platform - Increase Stratix10 QSPI support to 100 MHz -----BEGIN PGP SIGNATURE----- iQJIBAABCgAyFiEEoHhMeiyk5VmwVMwNGZQEC4GjKPQFAly1Mv8UHGRpbmd1eWVu QGtlcm5lbC5vcmcACgkQGZQEC4GjKPS7mg//d56np59wWQ1k4wP7FFo3ewnNcqdu Zr3e2T586KCRFpCAH2zsY32jzPLPgzgX0ssiXg4FDr8Q0tptDfYFtkzUfM+9J8LH 91VhGCUoq3YfKudnovl4vOo9QLTXyXxm9qSv4MN+8z+np/uLOc05qWFrPS6Ylh0O cYcC/1hif8svnxziH9d7QwF3Eely8aYAETY4waQVG5SDkzVMG9JuecC8rfxfOyCv uMy4jBTeOY7xDAJwl0yILPcI3qLZX97AoBUD64b7TmgGkrraSm9xijDmQKRFgFlz r42Ze4o1kjY+iKYefyXJiE+k4TQUoark8V0tBLst8KujiveH6gPQ8T8s75d0djFj r9koVafOege64KsY3Gdrkkv7e9vI8oCqcy/dvoApb9RBA3X+4V/gXJCZxv5KPOcn t3/swEsHKYnmJ1GumkmCnO+2aGKkDcJewJkQrnU4DNC8AVyGOyehPu9kqYfrMC3g eODzoHWC+4ZKltglfxP0mihqXHXcdYrSHfxAKtWAZyTect20w5w3dCsvvvpoxaA2 gYr008kqrGVIxumpCZlbaEVnr/0PnHdiMstIWMVsIOsvs8EuvQrbmJJS2TSqhhI0 gUFyADgnh4RCV/cD3EeYC9dokM6Ms2SDB/r7QdnQG1aELkVi51hSJf201w6fYemI Uq1EBLmMGaF8zow= =PxBZ -----END PGP SIGNATURE----- Merge tag 'socfpga_dts_updates_for_v5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt SoCFPGA DTS updates for v5.2 - Add base support for Agilex platform - Add 'cap-mmc-highspeed' Stratix10 and 32-bit SoCFPGA platform - Increase Stratix10 QSPI support to 100 MHz * tag 'socfpga_dts_updates_for_v5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: arm64: dts: agilex: Add initial support for Intel's Agilex SoCFPGA arm64: dts: stratix10: increase QSPI max frequency to 100MHz arm64: dts: stratix10: enable MMC highspeed support ARM: dts: socfpga: enable MMC highspeed support Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
a41332dd5e
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@ -9,6 +9,7 @@
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&mmc {
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status = "okay";
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cap-sd-highspeed;
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cap-mmc-highspeed;
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broken-cd;
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bus-width = <4>;
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};
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@ -7,6 +7,11 @@ config ARCH_ACTIONS
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help
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This enables support for the Actions Semiconductor S900 SoC family.
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config ARCH_AGILEX
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bool "Intel's Agilex SoCFPGA Family"
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help
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This enables support for Intel's Agilex SoCFPGA Family.
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config ARCH_SUNXI
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bool "Allwinner sunxi 64-bit SoC Family"
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select ARCH_HAS_RESET_CONTROLLER
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@ -13,6 +13,7 @@ subdir-y += cavium
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subdir-y += exynos
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subdir-y += freescale
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subdir-y += hisilicon
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subdir-y += intel
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subdir-y += lg
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subdir-y += marvell
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subdir-y += mediatek
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@ -107,6 +107,7 @@
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&mmc {
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status = "okay";
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cap-sd-highspeed;
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cap-mmc-highspeed;
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broken-cd;
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bus-width = <4>;
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};
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@ -159,7 +160,7 @@
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#size-cells = <1>;
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compatible = "n25q00a";
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reg = <0>;
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spi-max-frequency = <50000000>;
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spi-max-frequency = <100000000>;
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m25p,fast-read;
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cdns,page-size = <256>;
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@ -0,0 +1 @@
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dtb-$(CONFIG_ARCH_AGILEX) += socfpga_agilex_socdk.dtb
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@ -0,0 +1,444 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019, Intel Corporation
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*/
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/dts-v1/;
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#include <dt-bindings/reset/altr,rst-mgr-s10.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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compatible = "intel,socfpga-agilex";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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enable-method = "psci";
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reg = <0x0>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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enable-method = "psci";
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reg = <0x1>;
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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enable-method = "psci";
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reg = <0x2>;
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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enable-method = "psci";
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reg = <0x3>;
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};
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <0 120 8>,
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<0 121 8>,
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<0 122 8>,
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<0 123 8>;
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interrupt-affinity = <&cpu0>,
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<&cpu1>,
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<&cpu2>,
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<&cpu3>;
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interrupt-parent = <&intc>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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intc: intc@fffc1000 {
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compatible = "arm,gic-400", "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0xfffc1000 0x0 0x1000>,
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<0x0 0xfffc2000 0x0 0x2000>,
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<0x0 0xfffc4000 0x0 0x2000>,
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<0x0 0xfffc6000 0x0 0x2000>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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device_type = "soc";
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interrupt-parent = <&intc>;
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ranges = <0 0 0 0xffffffff>;
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gmac0: ethernet@ff800000 {
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
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reg = <0xff800000 0x2000>;
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interrupts = <0 90 4>;
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interrupt-names = "macirq";
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mac-address = [00 00 00 00 00 00];
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resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
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reset-names = "stmmaceth", "stmmaceth-ocp";
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tx-fifo-depth = <16384>;
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rx-fifo-depth = <16384>;
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snps,multicast-filter-bins = <256>;
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iommus = <&smmu 1>;
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status = "disabled";
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};
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gmac1: ethernet@ff802000 {
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
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reg = <0xff802000 0x2000>;
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interrupts = <0 91 4>;
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interrupt-names = "macirq";
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mac-address = [00 00 00 00 00 00];
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resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
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reset-names = "stmmaceth", "stmmaceth-ocp";
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tx-fifo-depth = <16384>;
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rx-fifo-depth = <16384>;
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snps,multicast-filter-bins = <256>;
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iommus = <&smmu 2>;
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status = "disabled";
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};
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gmac2: ethernet@ff804000 {
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
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reg = <0xff804000 0x2000>;
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interrupts = <0 92 4>;
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interrupt-names = "macirq";
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mac-address = [00 00 00 00 00 00];
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resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
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reset-names = "stmmaceth", "stmmaceth-ocp";
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tx-fifo-depth = <16384>;
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rx-fifo-depth = <16384>;
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snps,multicast-filter-bins = <256>;
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iommus = <&smmu 3>;
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status = "disabled";
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};
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gpio0: gpio@ffc03200 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dw-apb-gpio";
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reg = <0xffc03200 0x100>;
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resets = <&rst GPIO0_RESET>;
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status = "disabled";
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porta: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <24>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 110 4>;
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};
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};
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gpio1: gpio@ffc03300 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dw-apb-gpio";
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reg = <0xffc03300 0x100>;
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resets = <&rst GPIO1_RESET>;
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status = "disabled";
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portb: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <24>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 111 4>;
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};
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};
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i2c0: i2c@ffc02800 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xffc02800 0x100>;
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interrupts = <0 103 4>;
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resets = <&rst I2C0_RESET>;
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status = "disabled";
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};
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i2c1: i2c@ffc02900 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xffc02900 0x100>;
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interrupts = <0 104 4>;
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resets = <&rst I2C1_RESET>;
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status = "disabled";
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};
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i2c2: i2c@ffc02a00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xffc02a00 0x100>;
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interrupts = <0 105 4>;
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resets = <&rst I2C2_RESET>;
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status = "disabled";
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};
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i2c3: i2c@ffc02b00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xffc02b00 0x100>;
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interrupts = <0 106 4>;
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resets = <&rst I2C3_RESET>;
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status = "disabled";
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};
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i2c4: i2c@ffc02c00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xffc02c00 0x100>;
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interrupts = <0 107 4>;
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resets = <&rst I2C4_RESET>;
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status = "disabled";
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};
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mmc: dwmmc0@ff808000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "altr,socfpga-dw-mshc";
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reg = <0xff808000 0x1000>;
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interrupts = <0 96 4>;
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fifo-depth = <0x400>;
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resets = <&rst SDMMC_RESET>;
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reset-names = "reset";
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iommus = <&smmu 5>;
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status = "disabled";
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};
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ocram: sram@ffe00000 {
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compatible = "mmio-sram";
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reg = <0xffe00000 0x40000>;
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};
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pdma: pdma@ffda0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0xffda0000 0x1000>;
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interrupts = <0 81 4>,
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<0 82 4>,
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<0 83 4>,
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<0 84 4>,
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<0 85 4>,
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<0 86 4>,
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<0 87 4>,
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<0 88 4>,
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<0 89 4>;
|
||||
#dma-cells = <1>;
|
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#dma-channels = <8>;
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||||
#dma-requests = <32>;
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||||
};
|
||||
|
||||
rst: rstmgr@ffd11000 {
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||||
#reset-cells = <1>;
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||||
compatible = "altr,stratix10-rst-mgr";
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||||
reg = <0xffd11000 0x100>;
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||||
};
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||||
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||||
smmu: iommu@fa000000 {
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||||
compatible = "arm,mmu-500", "arm,smmu-v2";
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reg = <0xfa000000 0x40000>;
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||||
#global-interrupts = <2>;
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#iommu-cells = <1>;
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||||
interrupt-parent = <&intc>;
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||||
interrupts = <0 128 4>, /* Global Secure Fault */
|
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<0 129 4>, /* Global Non-secure Fault */
|
||||
/* Non-secure Context Interrupts (32) */
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||||
<0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
|
||||
<0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
|
||||
<0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
|
||||
<0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
|
||||
<0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
|
||||
<0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
|
||||
<0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
|
||||
<0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
|
||||
stream-match-mask = <0x7ff0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi@ffda4000 {
|
||||
compatible = "snps,dw-apb-ssi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xffda4000 0x1000>;
|
||||
interrupts = <0 99 4>;
|
||||
resets = <&rst SPIM0_RESET>;
|
||||
reg-io-width = <4>;
|
||||
num-cs = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@ffda5000 {
|
||||
compatible = "snps,dw-apb-ssi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xffda5000 0x1000>;
|
||||
interrupts = <0 100 4>;
|
||||
resets = <&rst SPIM1_RESET>;
|
||||
reg-io-width = <4>;
|
||||
num-cs = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sysmgr: sysmgr@ffd12000 {
|
||||
compatible = "altr,sys-mgr", "syscon";
|
||||
reg = <0xffd12000 0x500>;
|
||||
};
|
||||
|
||||
/* Local timer */
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <1 13 0xf08>,
|
||||
<1 14 0xf08>,
|
||||
<1 11 0xf08>,
|
||||
<1 10 0xf08>;
|
||||
};
|
||||
|
||||
timer0: timer0@ffc03000 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
interrupts = <0 113 4>;
|
||||
reg = <0xffc03000 0x100>;
|
||||
};
|
||||
|
||||
timer1: timer1@ffc03100 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
interrupts = <0 114 4>;
|
||||
reg = <0xffc03100 0x100>;
|
||||
};
|
||||
|
||||
timer2: timer2@ffd00000 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
interrupts = <0 115 4>;
|
||||
reg = <0xffd00000 0x100>;
|
||||
};
|
||||
|
||||
timer3: timer3@ffd00100 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
interrupts = <0 116 4>;
|
||||
reg = <0xffd00100 0x100>;
|
||||
};
|
||||
|
||||
uart0: serial0@ffc02000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0xffc02000 0x100>;
|
||||
interrupts = <0 108 4>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
resets = <&rst UART0_RESET>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial1@ffc02100 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0xffc02100 0x100>;
|
||||
interrupts = <0 109 4>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
resets = <&rst UART1_RESET>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbphy0: usbphy@0 {
|
||||
#phy-cells = <0>;
|
||||
compatible = "usb-nop-xceiv";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb0: usb@ffb00000 {
|
||||
compatible = "snps,dwc2";
|
||||
reg = <0xffb00000 0x40000>;
|
||||
interrupts = <0 93 4>;
|
||||
phys = <&usbphy0>;
|
||||
phy-names = "usb2-phy";
|
||||
resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
|
||||
reset-names = "dwc2", "dwc2-ecc";
|
||||
iommus = <&smmu 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb1: usb@ffb40000 {
|
||||
compatible = "snps,dwc2";
|
||||
reg = <0xffb40000 0x40000>;
|
||||
interrupts = <0 94 4>;
|
||||
phys = <&usbphy0>;
|
||||
phy-names = "usb2-phy";
|
||||
resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
|
||||
reset-names = "dwc2", "dwc2-ecc";
|
||||
iommus = <&smmu 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog0: watchdog@ffd00200 {
|
||||
compatible = "snps,dw-wdt";
|
||||
reg = <0xffd00200 0x100>;
|
||||
interrupts = <0 117 4>;
|
||||
resets = <&rst WATCHDOG0_RESET>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog1: watchdog@ffd00300 {
|
||||
compatible = "snps,dw-wdt";
|
||||
reg = <0xffd00300 0x100>;
|
||||
interrupts = <0 118 4>;
|
||||
resets = <&rst WATCHDOG1_RESET>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog2: watchdog@ffd00400 {
|
||||
compatible = "snps,dw-wdt";
|
||||
reg = <0xffd00400 0x100>;
|
||||
interrupts = <0 125 4>;
|
||||
resets = <&rst WATCHDOG2_RESET>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog3: watchdog@ffd00500 {
|
||||
compatible = "snps,dw-wdt";
|
||||
reg = <0xffd00500 0x100>;
|
||||
interrupts = <0 126 4>;
|
||||
resets = <&rst WATCHDOG3_RESET>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdr: sdr@f8011100 {
|
||||
compatible = "altr,sdr-ctl", "syscon";
|
||||
reg = <0xf8011100 0xc0>;
|
||||
};
|
||||
|
||||
qspi: spi@ff8d2000 {
|
||||
compatible = "cdns,qspi-nor";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xff8d2000 0x100>,
|
||||
<0xff900000 0x100000>;
|
||||
interrupts = <0 3 4>;
|
||||
cdns,fifo-depth = <128>;
|
||||
cdns,fifo-width = <4>;
|
||||
cdns,trigger-address = <0x00000000>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2019, Intel Corporation
|
||||
*/
|
||||
#include "socfpga_agilex.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SoCFPGA Agilex SoCDK";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
ethernet0 = &gmac0;
|
||||
ethernet1 = &gmac1;
|
||||
ethernet2 = &gmac2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
/* We expect the bootloader to fill in the reg */
|
||||
reg = <0 0 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy0>;
|
||||
|
||||
max-frame-size = <9000>;
|
||||
|
||||
mdio0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dwmac-mdio";
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <4>;
|
||||
|
||||
txd0-skew-ps = <0>; /* -420ps */
|
||||
txd1-skew-ps = <0>; /* -420ps */
|
||||
txd2-skew-ps = <0>; /* -420ps */
|
||||
txd3-skew-ps = <0>; /* -420ps */
|
||||
rxd0-skew-ps = <420>; /* 0ps */
|
||||
rxd1-skew-ps = <420>; /* 0ps */
|
||||
rxd2-skew-ps = <420>; /* 0ps */
|
||||
rxd3-skew-ps = <420>; /* 0ps */
|
||||
txen-skew-ps = <0>; /* -420ps */
|
||||
txc-skew-ps = <900>; /* 0ps */
|
||||
rxdv-skew-ps = <420>; /* 0ps */
|
||||
rxc-skew-ps = <1680>; /* 780ps */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mmc {
|
||||
status = "okay";
|
||||
cap-sd-highspeed;
|
||||
broken-cd;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
status = "okay";
|
||||
};
|
||||
Loading…
Reference in New Issue