SB1 cache exception handling.
Expand SB1 cache error handling by adding SB1_CEX_ALWAYS_FATAL and SB1_CEX_STALL, allowing configurable behavior on cache errors. Signed-Off-By: Andy Isaacson <adi@broadcom.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -19,13 +19,19 @@
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#include <linux/sched.h>
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#include <asm/mipsregs.h>
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#include <asm/sibyte/sb1250.h>
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#ifndef CONFIG_SIBYTE_BUS_WATCHER
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#include <asm/io.h>
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#include <asm/sibyte/sb1250_regs.h>
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#if !defined(CONFIG_SIBYTE_BUS_WATCHER) || defined(CONFIG_SIBYTE_BW_TRACE)
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#include <asm/io.h>
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#include <asm/sibyte/sb1250_scd.h>
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#endif
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/*
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* We'd like to dump the L2_ECC_TAG register on errors, but errata make
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* that unsafe... So for now we don't. (BCM1250/BCM112x erratum SOC-48.)
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*/
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#undef DUMP_L2_ECC_TAG_ON_ERROR
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/* SB1 definitions */
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/* XXX should come from config1 XXX */
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@ -139,12 +145,18 @@ static inline void breakout_cerrd(unsigned int val)
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static void check_bus_watcher(void)
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{
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uint32_t status, l2_err, memio_err;
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#ifdef DUMP_L2_ECC_TAG_ON_ERROR
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uint64_t l2_tag;
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#endif
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/* Destructive read, clears register and interrupt */
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status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS));
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/* Bit 31 is always on, but there's no #define for that */
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if (status & ~(1UL << 31)) {
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l2_err = csr_in32(IOADDR(A_BUS_L2_ERRORS));
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#ifdef DUMP_L2_ECC_TAG_ON_ERROR
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l2_tag = in64(IO_SPACE_BASE | A_L2_ECC_TAG);
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#endif
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memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS));
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prom_printf("Bus watcher error counters: %08x %08x\n", l2_err, memio_err);
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prom_printf("\nLast recorded signature:\n");
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@ -153,6 +165,9 @@ static void check_bus_watcher(void)
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(int)(G_SCD_BERR_TID(status) >> 6),
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(int)G_SCD_BERR_RID(status),
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(int)G_SCD_BERR_DCODE(status));
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#ifdef DUMP_L2_ECC_TAG_ON_ERROR
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prom_printf("Last L2 tag w/ bad ECC: %016llx\n", l2_tag);
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#endif
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} else {
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prom_printf("Bus watcher indicates no error\n");
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}
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@ -166,6 +181,16 @@ asmlinkage void sb1_cache_error(void)
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uint64_t cerr_dpa;
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uint32_t errctl, cerr_i, cerr_d, dpalo, dpahi, eepc, res;
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#ifdef CONFIG_SIBYTE_BW_TRACE
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/* Freeze the trace buffer now */
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#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
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csr_out32(M_BCM1480_SCD_TRACE_CFG_FREEZE, IO_SPACE_BASE | A_SCD_TRACE_CFG);
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#else
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csr_out32(M_SCD_TRACE_CFG_FREEZE, IO_SPACE_BASE | A_SCD_TRACE_CFG);
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#endif
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prom_printf("Trace buffer frozen\n");
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#endif
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prom_printf("Cache error exception on CPU %x:\n",
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(read_c0_prid() >> 25) & 0x7);
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@ -229,11 +254,19 @@ asmlinkage void sb1_cache_error(void)
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check_bus_watcher();
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while (1);
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/*
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* This tends to make things get really ugly; let's just stall instead.
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* panic("Can't handle the cache error!");
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* Calling panic() when a fatal cache error occurs scrambles the
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* state of the system (and the cache), making it difficult to
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* investigate after the fact. However, if you just stall the CPU,
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* the other CPU may keep on running, which is typically very
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* undesirable.
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*/
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#ifdef CONFIG_SB1_CERR_STALL
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while (1)
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;
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#else
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panic("unhandled cache error");
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#endif
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}
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@ -434,7 +467,8 @@ static struct dc_state dc_states[] = {
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};
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#define DC_TAG_VALID(state) \
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(((state) == 0xf) || ((state) == 0x13) || ((state) == 0x19) || ((state == 0x16)) || ((state) == 0x1c))
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(((state) == 0x0) || ((state) == 0xf) || ((state) == 0x13) || \
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((state) == 0x19) || ((state) == 0x16) || ((state) == 0x1c))
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static char *dc_state_str(unsigned char state)
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{
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@ -505,6 +539,7 @@ static uint32_t extract_dc(unsigned short addr, int data)
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uint64_t datalo;
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uint32_t datalohi, datalolo, datahi;
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int offset;
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char bad_ecc = 0;
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for (offset = 0; offset < 4; offset++) {
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/* Index-load-data-D */
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@ -525,8 +560,7 @@ static uint32_t extract_dc(unsigned short addr, int data)
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ecc = dc_ecc(datalo);
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if (ecc != datahi) {
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int bits = 0;
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prom_printf(" ** bad ECC (%02x %02x) ->",
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datahi, ecc);
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bad_ecc |= 1 << (3-offset);
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ecc ^= datahi;
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while (ecc) {
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if (ecc & 1) bits++;
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@ -537,6 +571,10 @@ static uint32_t extract_dc(unsigned short addr, int data)
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prom_printf(" %02X-%016llX", datahi, datalo);
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}
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prom_printf("\n");
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if (bad_ecc)
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prom_printf(" dwords w/ bad ECC: %d %d %d %d\n",
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!!(bad_ecc & 8), !!(bad_ecc & 4),
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!!(bad_ecc & 2), !!(bad_ecc & 1));
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}
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}
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return res;
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@ -64,6 +64,10 @@ LEAF(except_vec2_sb1)
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sd k0,0x170($0)
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sd k1,0x178($0)
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#if CONFIG_SB1_CEX_ALWAYS_FATAL
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j handle_vec2_sb1
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nop
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#else
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/*
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* M_ERRCTL_RECOVERABLE is bit 31, which makes it easy to tell
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* if we can fast-path out of here for a h/w-recovered error.
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@ -134,6 +138,7 @@ unrecoverable:
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/* Unrecoverable Icache or Dcache error; log it and/or fail */
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j handle_vec2_sb1
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nop
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#endif
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END(except_vec2_sb1)
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@ -102,6 +102,14 @@ config SIMULATION
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Build a kernel suitable for running under the GDB simulator.
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Primarily adjusts the kernel's notion of time.
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config CONFIG_SB1_CEX_ALWAYS_FATAL
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bool "All cache exceptions considered fatal (no recovery attempted)"
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depends on SIBYTE_SB1xxx_SOC
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config CONFIG_SB1_CERR_STALL
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bool "Stall (rather than panic) on fatal cache error"
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depends on SIBYTE_SB1xxx_SOC
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config SIBYTE_CFE
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bool "Booting from CFE"
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depends on SIBYTE_SB1xxx_SOC
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