ARM: tegra: powergate driver changes
This branch includes all the changes to Tegra's powergate driver for 3.14. These are separate out, since the Tegra DRM changes for 3.14 rely on the new APIs introduced here. A few cleanups and fixes are included, plus additions of Tegra124 SoC support, and a new API for manipulating Tegra's IO rail deep power down states. This branch is based on tag tegra-for-3.14-dmas-resets-rework, in order to avoid conflicts with the addition of common reset controller support to the powergate driver. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJSr3G5AAoJEMzrak5tbycxHaEP/2YP1KIUTINzF9JlTaFWLd38 dlqCOdDjcIow6QvaI0H2xdD7OhWqbiK2gAKz10PH0TYVr5AJZKyC7uxAw1gvV5bI 2hgP9ZBVQY8qfveZuyQhL9jCwAg52TfG2LBO4Iw3wng9tO00uo8knjoHURmiewuY fLY8CQxYydwK8MmqabPI/L0gQhSlswyDByaeB0ixHJncSVT8KHmbSX8kx7FnYsI6 /r/D7IQtMyx52XJRbInN83UIdONKP9vkPAXmptKBU2SGwdXOzqPqfxFuNRKN85Gq a4wlJUQAfBAndiemaZIH5O7gmmUht1lB0L9JWDFw9nBr6EHDVOpgRgi/OgVFaFE+ Qer3LdrpEvyXsRe3AjeQgta8716KaRMW3IbaqkdS0F+HwyFGL9/nGRttu9JLHSCR oo7FVscaE7tC2d/LGNqI0y4pprgbrjROT70hWoNDF8oS5qDsI3rxEjB0FXyzE2by Bd702Sc9heh60Hnov/vZy9WFcWETEKVEF5hgIL3lrjA6pMKdH7fEylOD+bxVAmE2 t5wePXc7OSdciaLN/D1GhtCD+R58u+idHadKnU9uRYB1wmeIAeJMi9D/ZnpKftX4 M5Ts7t8k1jxZlRXXgiara3SwJ6tIOlc5vEvhQWEeInzL0yishFDy2mmq1lMaV0mJ cFgQUdhufycI0Yprfwjt =jJOV -----END PGP SIGNATURE----- Merge tag 'tegra-for-3.14-powergate' into drm/for-next ARM: tegra: powergate driver changes This branch includes all the changes to Tegra's powergate driver for 3.14. These are separate out, since the Tegra DRM changes for 3.14 rely on the new APIs introduced here. A few cleanups and fixes are included, plus additions of Tegra124 SoC support, and a new API for manipulating Tegra's IO rail deep power down states. This branch is based on tag tegra-for-3.14-dmas-resets-rework, in order to avoid conflicts with the addition of common reset controller support to the powergate driver.
This commit is contained in:
Thierry Reding
commit
a4d86e5e42
|
|
@ -34,6 +34,10 @@
|
|||
#include "fuse.h"
|
||||
#include "iomap.h"
|
||||
|
||||
#define DPD_SAMPLE 0x020
|
||||
#define DPD_SAMPLE_ENABLE (1 << 0)
|
||||
#define DPD_SAMPLE_DISABLE (0 << 0)
|
||||
|
||||
#define PWRGATE_TOGGLE 0x30
|
||||
#define PWRGATE_TOGGLE_START (1 << 8)
|
||||
|
||||
|
|
@ -41,6 +45,19 @@
|
|||
|
||||
#define PWRGATE_STATUS 0x38
|
||||
|
||||
#define IO_DPD_REQ 0x1b8
|
||||
#define IO_DPD_REQ_CODE_IDLE (0 << 30)
|
||||
#define IO_DPD_REQ_CODE_OFF (1 << 30)
|
||||
#define IO_DPD_REQ_CODE_ON (2 << 30)
|
||||
#define IO_DPD_REQ_CODE_MASK (3 << 30)
|
||||
|
||||
#define IO_DPD_STATUS 0x1bc
|
||||
#define IO_DPD2_REQ 0x1c0
|
||||
#define IO_DPD2_STATUS 0x1c4
|
||||
#define SEL_DPD_TIM 0x1c8
|
||||
|
||||
#define GPU_RG_CNTRL 0x2d4
|
||||
|
||||
static int tegra_num_powerdomains;
|
||||
static int tegra_num_cpu_domains;
|
||||
static const u8 *tegra_cpu_domains;
|
||||
|
|
@ -59,6 +76,13 @@ static const u8 tegra114_cpu_domains[] = {
|
|||
TEGRA_POWERGATE_CPU3,
|
||||
};
|
||||
|
||||
static const u8 tegra124_cpu_domains[] = {
|
||||
TEGRA_POWERGATE_CPU0,
|
||||
TEGRA_POWERGATE_CPU1,
|
||||
TEGRA_POWERGATE_CPU2,
|
||||
TEGRA_POWERGATE_CPU3,
|
||||
};
|
||||
|
||||
static DEFINE_SPINLOCK(tegra_powergate_lock);
|
||||
|
||||
static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
|
||||
|
|
@ -109,6 +133,7 @@ int tegra_powergate_power_off(int id)
|
|||
|
||||
return tegra_powergate_set(id, false);
|
||||
}
|
||||
EXPORT_SYMBOL(tegra_powergate_power_off);
|
||||
|
||||
int tegra_powergate_is_powered(int id)
|
||||
{
|
||||
|
|
@ -128,13 +153,24 @@ int tegra_powergate_remove_clamping(int id)
|
|||
if (id < 0 || id >= tegra_num_powerdomains)
|
||||
return -EINVAL;
|
||||
|
||||
/*
|
||||
* The Tegra124 GPU has a separate register (with different semantics)
|
||||
* to remove clamps.
|
||||
*/
|
||||
if (tegra_chip_id == TEGRA124) {
|
||||
if (id == TEGRA_POWERGATE_3D) {
|
||||
pmc_write(0, GPU_RG_CNTRL);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Tegra 2 has a bug where PCIE and VDE clamping masks are
|
||||
* swapped relatively to the partition ids
|
||||
*/
|
||||
if (id == TEGRA_POWERGATE_VDEC)
|
||||
if (id == TEGRA_POWERGATE_VDEC)
|
||||
mask = (1 << TEGRA_POWERGATE_PCIE);
|
||||
else if (id == TEGRA_POWERGATE_PCIE)
|
||||
else if (id == TEGRA_POWERGATE_PCIE)
|
||||
mask = (1 << TEGRA_POWERGATE_VDEC);
|
||||
else
|
||||
mask = (1 << id);
|
||||
|
|
@ -143,6 +179,7 @@ int tegra_powergate_remove_clamping(int id)
|
|||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(tegra_powergate_remove_clamping);
|
||||
|
||||
/* Must be called with clk disabled, and returns with clk enabled */
|
||||
int tegra_powergate_sequence_power_up(int id, struct clk *clk,
|
||||
|
|
@ -204,6 +241,11 @@ int __init tegra_powergate_init(void)
|
|||
tegra_num_cpu_domains = 4;
|
||||
tegra_cpu_domains = tegra114_cpu_domains;
|
||||
break;
|
||||
case TEGRA124:
|
||||
tegra_num_powerdomains = 25;
|
||||
tegra_num_cpu_domains = 4;
|
||||
tegra_cpu_domains = tegra124_cpu_domains;
|
||||
break;
|
||||
default:
|
||||
/* Unknown Tegra variant. Disable powergating */
|
||||
tegra_num_powerdomains = 0;
|
||||
|
|
@ -245,7 +287,7 @@ static const char * const powergate_name_t30[] = {
|
|||
};
|
||||
|
||||
static const char * const powergate_name_t114[] = {
|
||||
[TEGRA_POWERGATE_CPU] = "cpu0",
|
||||
[TEGRA_POWERGATE_CPU] = "crail",
|
||||
[TEGRA_POWERGATE_3D] = "3d",
|
||||
[TEGRA_POWERGATE_VENC] = "venc",
|
||||
[TEGRA_POWERGATE_VDEC] = "vdec",
|
||||
|
|
@ -265,6 +307,33 @@ static const char * const powergate_name_t114[] = {
|
|||
[TEGRA_POWERGATE_XUSBC] = "xusbc",
|
||||
};
|
||||
|
||||
static const char * const powergate_name_t124[] = {
|
||||
[TEGRA_POWERGATE_CPU] = "crail",
|
||||
[TEGRA_POWERGATE_3D] = "3d",
|
||||
[TEGRA_POWERGATE_VENC] = "venc",
|
||||
[TEGRA_POWERGATE_PCIE] = "pcie",
|
||||
[TEGRA_POWERGATE_VDEC] = "vdec",
|
||||
[TEGRA_POWERGATE_L2] = "l2",
|
||||
[TEGRA_POWERGATE_MPE] = "mpe",
|
||||
[TEGRA_POWERGATE_HEG] = "heg",
|
||||
[TEGRA_POWERGATE_SATA] = "sata",
|
||||
[TEGRA_POWERGATE_CPU1] = "cpu1",
|
||||
[TEGRA_POWERGATE_CPU2] = "cpu2",
|
||||
[TEGRA_POWERGATE_CPU3] = "cpu3",
|
||||
[TEGRA_POWERGATE_CELP] = "celp",
|
||||
[TEGRA_POWERGATE_CPU0] = "cpu0",
|
||||
[TEGRA_POWERGATE_C0NC] = "c0nc",
|
||||
[TEGRA_POWERGATE_C1NC] = "c1nc",
|
||||
[TEGRA_POWERGATE_SOR] = "sor",
|
||||
[TEGRA_POWERGATE_DIS] = "dis",
|
||||
[TEGRA_POWERGATE_DISB] = "disb",
|
||||
[TEGRA_POWERGATE_XUSBA] = "xusba",
|
||||
[TEGRA_POWERGATE_XUSBB] = "xusbb",
|
||||
[TEGRA_POWERGATE_XUSBC] = "xusbc",
|
||||
[TEGRA_POWERGATE_VIC] = "vic",
|
||||
[TEGRA_POWERGATE_IRAM] = "iram",
|
||||
};
|
||||
|
||||
static int powergate_show(struct seq_file *s, void *data)
|
||||
{
|
||||
int i;
|
||||
|
|
@ -309,6 +378,9 @@ int __init tegra_powergate_debugfs_init(void)
|
|||
case TEGRA114:
|
||||
powergate_name = powergate_name_t114;
|
||||
break;
|
||||
case TEGRA124:
|
||||
powergate_name = powergate_name_t124;
|
||||
break;
|
||||
}
|
||||
|
||||
if (powergate_name) {
|
||||
|
|
@ -322,3 +394,120 @@ int __init tegra_powergate_debugfs_init(void)
|
|||
}
|
||||
|
||||
#endif
|
||||
|
||||
static int tegra_io_rail_prepare(int id, unsigned long *request,
|
||||
unsigned long *status, unsigned int *bit)
|
||||
{
|
||||
unsigned long rate, value;
|
||||
struct clk *clk;
|
||||
|
||||
*bit = id % 32;
|
||||
|
||||
/*
|
||||
* There are two sets of 30 bits to select IO rails, but bits 30 and
|
||||
* 31 are control bits rather than IO rail selection bits.
|
||||
*/
|
||||
if (id > 63 || *bit == 30 || *bit == 31)
|
||||
return -EINVAL;
|
||||
|
||||
if (id < 32) {
|
||||
*status = IO_DPD_STATUS;
|
||||
*request = IO_DPD_REQ;
|
||||
} else {
|
||||
*status = IO_DPD2_STATUS;
|
||||
*request = IO_DPD2_REQ;
|
||||
}
|
||||
|
||||
clk = clk_get_sys(NULL, "pclk");
|
||||
if (IS_ERR(clk))
|
||||
return PTR_ERR(clk);
|
||||
|
||||
rate = clk_get_rate(clk);
|
||||
clk_put(clk);
|
||||
|
||||
pmc_write(DPD_SAMPLE_ENABLE, DPD_SAMPLE);
|
||||
|
||||
/* must be at least 200 ns, in APB (PCLK) clock cycles */
|
||||
value = DIV_ROUND_UP(1000000000, rate);
|
||||
value = DIV_ROUND_UP(200, value);
|
||||
pmc_write(value, SEL_DPD_TIM);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_io_rail_poll(unsigned long offset, unsigned long mask,
|
||||
unsigned long val, unsigned long timeout)
|
||||
{
|
||||
unsigned long value;
|
||||
|
||||
timeout = jiffies + msecs_to_jiffies(timeout);
|
||||
|
||||
while (time_after(timeout, jiffies)) {
|
||||
value = pmc_read(offset);
|
||||
if ((value & mask) == val)
|
||||
return 0;
|
||||
|
||||
usleep_range(250, 1000);
|
||||
}
|
||||
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
static void tegra_io_rail_unprepare(void)
|
||||
{
|
||||
pmc_write(DPD_SAMPLE_DISABLE, DPD_SAMPLE);
|
||||
}
|
||||
|
||||
int tegra_io_rail_power_on(int id)
|
||||
{
|
||||
unsigned long request, status, value;
|
||||
unsigned int bit, mask;
|
||||
int err;
|
||||
|
||||
err = tegra_io_rail_prepare(id, &request, &status, &bit);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
mask = 1 << bit;
|
||||
|
||||
value = pmc_read(request);
|
||||
value |= mask;
|
||||
value &= ~IO_DPD_REQ_CODE_MASK;
|
||||
value |= IO_DPD_REQ_CODE_OFF;
|
||||
pmc_write(value, request);
|
||||
|
||||
err = tegra_io_rail_poll(status, mask, 0, 250);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
tegra_io_rail_unprepare();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int tegra_io_rail_power_off(int id)
|
||||
{
|
||||
unsigned long request, status, value;
|
||||
unsigned int bit, mask;
|
||||
int err;
|
||||
|
||||
err = tegra_io_rail_prepare(id, &request, &status, &bit);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
mask = 1 << bit;
|
||||
|
||||
value = pmc_read(request);
|
||||
value |= mask;
|
||||
value &= ~IO_DPD_REQ_CODE_MASK;
|
||||
value |= IO_DPD_REQ_CODE_ON;
|
||||
pmc_write(value, request);
|
||||
|
||||
err = tegra_io_rail_poll(status, mask, mask, 250);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
tegra_io_rail_unprepare();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -38,14 +38,49 @@ struct reset_control;
|
|||
#define TEGRA_POWERGATE_CPU0 14
|
||||
#define TEGRA_POWERGATE_C0NC 15
|
||||
#define TEGRA_POWERGATE_C1NC 16
|
||||
#define TEGRA_POWERGATE_SOR 17
|
||||
#define TEGRA_POWERGATE_DIS 18
|
||||
#define TEGRA_POWERGATE_DISB 19
|
||||
#define TEGRA_POWERGATE_XUSBA 20
|
||||
#define TEGRA_POWERGATE_XUSBB 21
|
||||
#define TEGRA_POWERGATE_XUSBC 22
|
||||
#define TEGRA_POWERGATE_VIC 23
|
||||
#define TEGRA_POWERGATE_IRAM 24
|
||||
|
||||
#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D
|
||||
|
||||
#define TEGRA_IO_RAIL_CSIA 0
|
||||
#define TEGRA_IO_RAIL_CSIB 1
|
||||
#define TEGRA_IO_RAIL_DSI 2
|
||||
#define TEGRA_IO_RAIL_MIPI_BIAS 3
|
||||
#define TEGRA_IO_RAIL_PEX_BIAS 4
|
||||
#define TEGRA_IO_RAIL_PEX_CLK1 5
|
||||
#define TEGRA_IO_RAIL_PEX_CLK2 6
|
||||
#define TEGRA_IO_RAIL_USB0 9
|
||||
#define TEGRA_IO_RAIL_USB1 10
|
||||
#define TEGRA_IO_RAIL_USB2 11
|
||||
#define TEGRA_IO_RAIL_USB_BIAS 12
|
||||
#define TEGRA_IO_RAIL_NAND 13
|
||||
#define TEGRA_IO_RAIL_UART 14
|
||||
#define TEGRA_IO_RAIL_BB 15
|
||||
#define TEGRA_IO_RAIL_AUDIO 17
|
||||
#define TEGRA_IO_RAIL_HSIC 19
|
||||
#define TEGRA_IO_RAIL_COMP 22
|
||||
#define TEGRA_IO_RAIL_HDMI 28
|
||||
#define TEGRA_IO_RAIL_PEX_CNTRL 32
|
||||
#define TEGRA_IO_RAIL_SDMMC1 33
|
||||
#define TEGRA_IO_RAIL_SDMMC3 34
|
||||
#define TEGRA_IO_RAIL_SDMMC4 35
|
||||
#define TEGRA_IO_RAIL_CAM 36
|
||||
#define TEGRA_IO_RAIL_RES 37
|
||||
#define TEGRA_IO_RAIL_HV 38
|
||||
#define TEGRA_IO_RAIL_DSIB 39
|
||||
#define TEGRA_IO_RAIL_DSIC 40
|
||||
#define TEGRA_IO_RAIL_DSID 41
|
||||
#define TEGRA_IO_RAIL_CSIE 44
|
||||
#define TEGRA_IO_RAIL_LVDS 57
|
||||
#define TEGRA_IO_RAIL_SYS_DDC 58
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA
|
||||
int tegra_powergate_is_powered(int id);
|
||||
int tegra_powergate_power_on(int id);
|
||||
|
|
@ -55,6 +90,9 @@ int tegra_powergate_remove_clamping(int id);
|
|||
/* Must be called with clk disabled, and returns with clk enabled */
|
||||
int tegra_powergate_sequence_power_up(int id, struct clk *clk,
|
||||
struct reset_control *rst);
|
||||
|
||||
int tegra_io_rail_power_on(int id);
|
||||
int tegra_io_rail_power_off(int id);
|
||||
#else
|
||||
static inline int tegra_powergate_is_powered(int id)
|
||||
{
|
||||
|
|
@ -81,6 +119,16 @@ static inline int tegra_powergate_sequence_power_up(int id, struct clk *clk,
|
|||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline int tegra_io_rail_power_on(int id)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline int tegra_io_rail_power_off(int id)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _MACH_TEGRA_POWERGATE_H_ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue