Merge branch 'asoc-5.2' into asoc-5.3

This commit is contained in:
Mark Brown 2019-06-03 18:38:15 +01:00
commit a529819d88
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GPG Key ID: 24D68B725D5487D0
12 changed files with 115 additions and 38 deletions

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@ -48,6 +48,7 @@
#define SOF_IPC_FW_READY SOF_GLB_TYPE(0x7U)
#define SOF_IPC_GLB_DAI_MSG SOF_GLB_TYPE(0x8U)
#define SOF_IPC_GLB_TRACE_MSG SOF_GLB_TYPE(0x9U)
#define SOF_IPC_GLB_GDB_DEBUG SOF_GLB_TYPE(0xAU)
/*
* DSP Command Message Types
@ -78,6 +79,7 @@
#define SOF_IPC_COMP_GET_VALUE SOF_CMD_TYPE(0x002)
#define SOF_IPC_COMP_SET_DATA SOF_CMD_TYPE(0x003)
#define SOF_IPC_COMP_GET_DATA SOF_CMD_TYPE(0x004)
#define SOF_IPC_COMP_NOTIFICATION SOF_CMD_TYPE(0x005)
/* DAI messages */
#define SOF_IPC_DAI_CONFIG SOF_CMD_TYPE(0x001)
@ -153,6 +155,27 @@ struct sof_ipc_compound_hdr {
uint32_t count; /**< count of 0 means end of compound sequence */
} __packed;
/**
* OOPS header architecture specific data.
*/
struct sof_ipc_dsp_oops_arch_hdr {
uint32_t arch; /* Identifier of architecture */
uint32_t totalsize; /* Total size of oops message */
} __packed;
/**
* OOPS header platform specific data.
*/
struct sof_ipc_dsp_oops_plat_hdr {
uint32_t configidhi; /* ConfigID hi 32bits */
uint32_t configidlo; /* ConfigID lo 32bits */
uint32_t numaregs; /* Special regs num */
uint32_t stackoffset; /* Offset to stack pointer from beginning of
* oops message
*/
uint32_t stackptr; /* Stack ptr */
} __packed;
/** @}*/
#endif

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@ -18,6 +18,14 @@
#define SOF_IPC_MAX_ELEMS 16
/*
* Firmware boot info flag bits (64-bit)
*/
#define SOF_IPC_INFO_BUILD BIT(0)
#define SOF_IPC_INFO_LOCKS BIT(1)
#define SOF_IPC_INFO_LOCKSV BIT(2)
#define SOF_IPC_INFO_GDB BIT(3)
/* extended data types that can be appended onto end of sof_ipc_fw_ready */
enum sof_ipc_ext_data {
SOF_IPC_EXT_DMA_BUFFER = 0,
@ -49,16 +57,8 @@ struct sof_ipc_fw_ready {
uint32_t hostbox_size;
struct sof_ipc_fw_version version;
/* Miscellaneous debug flags showing build/debug features enabled */
union {
uint64_t reserved;
struct {
uint64_t build:1;
uint64_t locks:1;
uint64_t locks_verbose:1;
uint64_t gdb:1;
} bits;
} debug;
/* Miscellaneous flags */
uint64_t flags;
/* reserved for future use */
uint32_t reserved[4];

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@ -17,7 +17,8 @@
/* Xtensa Firmware Oops data */
struct sof_ipc_dsp_oops_xtensa {
struct sof_ipc_hdr hdr;
struct sof_ipc_dsp_oops_arch_hdr arch_hdr;
struct sof_ipc_dsp_oops_plat_hdr plat_hdr;
uint32_t exccause;
uint32_t excvaddr;
uint32_t ps;
@ -38,7 +39,11 @@ struct sof_ipc_dsp_oops_xtensa {
uint32_t intenable;
uint32_t interrupt;
uint32_t sar;
uint32_t stack;
uint32_t debugcause;
uint32_t windowbase;
uint32_t windowstart;
uint32_t excsave1;
uint32_t ar[];
} __packed;
#endif

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@ -26,7 +26,7 @@
/* SOF ABI version major, minor and patch numbers */
#define SOF_ABI_MAJOR 3
#define SOF_ABI_MINOR 5
#define SOF_ABI_MINOR 6
#define SOF_ABI_PATCH 0
/* SOF ABI version number. Format within 32bit word is MMmmmppp */

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@ -840,7 +840,14 @@ static int snd_hda_codec_dev_free(struct snd_device *device)
if (codec->core.type == HDA_DEV_LEGACY)
snd_hdac_device_unregister(&codec->core);
codec_display_power(codec, false);
put_device(hda_codec_dev(codec));
/*
* In the case of ASoC HD-audio bus, the device refcount is released in
* snd_hdac_ext_bus_device_remove() explicitly.
*/
if (codec->core.type == HDA_DEV_LEGACY)
put_device(hda_codec_dev(codec));
return 0;
}

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@ -2882,6 +2882,18 @@ static const struct dmi_system_id dmi_platform_intel_quirks[] = {
RT5670_DEV_GPIO |
RT5670_JD_MODE3),
},
{
.callback = rt5670_quirk_cb,
.ident = "Aegex 10 tablet (RU2)",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "AEGEX"),
DMI_MATCH(DMI_PRODUCT_VERSION, "RU2"),
},
.driver_data = (unsigned long *)(RT5670_DMIC_EN |
RT5670_DMIC2_INR |
RT5670_DEV_GPIO |
RT5670_JD_MODE3),
},
{}
};

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@ -22,6 +22,7 @@ static unsigned long byt_machine_id;
#define BYT_THINKPAD_10 1
#define BYT_POV_P1006W 2
#define BYT_AEGEX_10 3
static int byt_thinkpad10_quirk_cb(const struct dmi_system_id *id)
{
@ -35,6 +36,12 @@ static int byt_pov_p1006w_quirk_cb(const struct dmi_system_id *id)
return 1;
}
static int byt_aegex10_quirk_cb(const struct dmi_system_id *id)
{
byt_machine_id = BYT_AEGEX_10;
return 1;
}
static const struct dmi_system_id byt_table[] = {
{
.callback = byt_thinkpad10_quirk_cb,
@ -75,9 +82,18 @@ static const struct dmi_system_id byt_table[] = {
DMI_EXACT_MATCH(DMI_BOARD_NAME, "0E57"),
},
},
{
/* Aegex 10 tablet (RU2) */
.callback = byt_aegex10_quirk_cb,
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "AEGEX"),
DMI_MATCH(DMI_PRODUCT_VERSION, "RU2"),
},
},
{ }
};
/* The Thinkapd 10 and Aegex 10 tablets have the same ID problem */
static struct snd_soc_acpi_mach byt_thinkpad_10 = {
.id = "10EC5640",
.drv_name = "cht-bsw-rt5672",
@ -104,6 +120,7 @@ static struct snd_soc_acpi_mach *byt_quirk(void *arg)
switch (byt_machine_id) {
case BYT_THINKPAD_10:
case BYT_AEGEX_10:
return &byt_thinkpad_10;
case BYT_POV_P1006W:
return &byt_pov_p1006w;

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@ -220,17 +220,20 @@ static void bdw_get_registers(struct snd_sof_dev *sdev,
struct sof_ipc_panic_info *panic_info,
u32 *stack, size_t stack_words)
{
/* first read regsisters */
sof_mailbox_read(sdev, sdev->dsp_oops_offset, xoops, sizeof(*xoops));
u32 offset = sdev->dsp_oops_offset;
/* first read registers */
sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops));
/* note: variable AR register array is not read */
/* then get panic info */
sof_mailbox_read(sdev, sdev->dsp_oops_offset + sizeof(*xoops),
panic_info, sizeof(*panic_info));
offset += xoops->arch_hdr.totalsize;
sof_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info));
/* then get the stack */
sof_mailbox_read(sdev, sdev->dsp_oops_offset + sizeof(*xoops) +
sizeof(*panic_info), stack,
stack_words * sizeof(u32));
offset += sizeof(*panic_info);
sof_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32));
}
static void bdw_dump(struct snd_sof_dev *sdev, u32 flags)

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@ -265,17 +265,20 @@ static void byt_get_registers(struct snd_sof_dev *sdev,
struct sof_ipc_panic_info *panic_info,
u32 *stack, size_t stack_words)
{
u32 offset = sdev->dsp_oops_offset;
/* first read regsisters */
sof_mailbox_read(sdev, sdev->dsp_oops_offset, xoops, sizeof(*xoops));
sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops));
/* note: variable AR register array is not read */
/* then get panic info */
sof_mailbox_read(sdev, sdev->dsp_oops_offset + sizeof(*xoops),
panic_info, sizeof(*panic_info));
offset += xoops->arch_hdr.totalsize;
sof_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info));
/* then get the stack */
sof_mailbox_read(sdev, sdev->dsp_oops_offset + sizeof(*xoops) +
sizeof(*panic_info), stack,
stack_words * sizeof(u32));
offset += sizeof(*panic_info);
sof_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32));
}
static void byt_dump(struct snd_sof_dev *sdev, u32 flags)

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@ -108,17 +108,21 @@ static void hda_dsp_get_registers(struct snd_sof_dev *sdev,
struct sof_ipc_panic_info *panic_info,
u32 *stack, size_t stack_words)
{
u32 offset = sdev->dsp_oops_offset;
/* first read registers */
sof_block_read(sdev, sdev->mmio_bar, sdev->dsp_oops_offset, xoops,
sizeof(*xoops));
sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops));
/* note: variable AR register array is not read */
/* then get panic info */
sof_block_read(sdev, sdev->mmio_bar, sdev->dsp_oops_offset +
sizeof(*xoops), panic_info, sizeof(*panic_info));
offset += xoops->arch_hdr.totalsize;
sof_block_read(sdev, sdev->mmio_bar, offset,
panic_info, sizeof(*panic_info));
/* then get the stack */
sof_block_read(sdev, sdev->mmio_bar, sdev->dsp_oops_offset +
sizeof(*xoops) + sizeof(*panic_info), stack,
offset += sizeof(*panic_info);
sof_block_read(sdev, sdev->mmio_bar, offset, stack,
stack_words * sizeof(u32));
}

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@ -763,16 +763,19 @@ int snd_sof_ipc_valid(struct snd_sof_dev *sdev)
}
}
if (ready->debug.bits.build) {
if (ready->flags & SOF_IPC_INFO_BUILD) {
dev_info(sdev->dev,
"Firmware debug build %d on %s-%s - options:\n"
" GDB: %s\n"
" lock debug: %s\n"
" lock vdebug: %s\n",
v->build, v->date, v->time,
ready->debug.bits.gdb ? "enabled" : "disabled",
ready->debug.bits.locks ? "enabled" : "disabled",
ready->debug.bits.locks_verbose ? "enabled" : "disabled");
ready->flags & SOF_IPC_INFO_GDB ?
"enabled" : "disabled",
ready->flags & SOF_IPC_INFO_LOCKS ?
"enabled" : "disabled",
ready->flags & SOF_IPC_INFO_LOCKSV ?
"enabled" : "disabled");
}
/* copy the fw_version into debugfs at first boot */

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@ -110,7 +110,7 @@ static void xtensa_stack(struct snd_sof_dev *sdev, void *oops, u32 *stack,
u32 stack_words)
{
struct sof_ipc_dsp_oops_xtensa *xoops = oops;
u32 stack_ptr = xoops->stack;
u32 stack_ptr = xoops->plat_hdr.stackptr;
/* 4 * 8chars + 3 ws + 1 terminating NUL */
unsigned char buf[4 * 8 + 3 + 1];
int i;