xtensa: enforce slab alignment to maximum register width
XCHAL_DATA_WIDTH is the maximum register width, slab caches should be aligned to this. Theoretical fix as all variants have had an XCHAL_DATA_WIDTH of 4 (wordsize) for now. But the S6000 variant will raise this to 16. Signed-off-by: Oskar Schirmer <os@emlix.com> Signed-off-by: Johannes Weiner <jw@emlix.com> Signed-off-by: Chris Zankel <chris@zankel.net>
This commit is contained in:
parent
c947a585ab
commit
a81cbd2da4
|
@ -25,6 +25,8 @@
|
||||||
# error Linux requires the Xtensa Windowed Registers Option.
|
# error Linux requires the Xtensa Windowed Registers Option.
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#define ARCH_SLAB_MINALIGN XCHAL_DATA_WIDTH
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* User space process size: 1 GB.
|
* User space process size: 1 GB.
|
||||||
* Windowed call ABI requires caller and callee to be located within the same
|
* Windowed call ABI requires caller and callee to be located within the same
|
||||||
|
|
Loading…
Reference in New Issue