tty: xuartps: Remove '_OFFSET' suffix from #defines
Remove the _OFFSET suffix from all register defines which makes code a little easier to read and avoids a few line breaks. Suggested-by: Peter Hurley <peter@hurleysoftware.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Soren Brinkmann
Greg Kroah-Hartman
parent
74ea66d4ca
commit
a8df6a5160
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@ -50,24 +50,24 @@ module_param(rx_timeout, uint, S_IRUGO);
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MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
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/* Register offsets for the UART. */
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#define CDNS_UART_CR_OFFSET 0x00 /* Control Register */
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#define CDNS_UART_MR_OFFSET 0x04 /* Mode Register */
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#define CDNS_UART_IER_OFFSET 0x08 /* Interrupt Enable */
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#define CDNS_UART_IDR_OFFSET 0x0C /* Interrupt Disable */
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#define CDNS_UART_IMR_OFFSET 0x10 /* Interrupt Mask */
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#define CDNS_UART_ISR_OFFSET 0x14 /* Interrupt Status */
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#define CDNS_UART_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator */
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#define CDNS_UART_RXTOUT_OFFSET 0x1C /* RX Timeout */
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#define CDNS_UART_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level */
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#define CDNS_UART_MODEMCR_OFFSET 0x24 /* Modem Control */
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#define CDNS_UART_MODEMSR_OFFSET 0x28 /* Modem Status */
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#define CDNS_UART_SR_OFFSET 0x2C /* Channel Status */
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#define CDNS_UART_FIFO_OFFSET 0x30 /* FIFO */
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#define CDNS_UART_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider */
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#define CDNS_UART_FLOWDEL_OFFSET 0x38 /* Flow Delay */
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#define CDNS_UART_IRRX_PWIDTH_OFFSET 0x3C /* IR Min Received Pulse Width */
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#define CDNS_UART_IRTX_PWIDTH_OFFSET 0x40 /* IR Transmitted pulse Width */
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#define CDNS_UART_TXWM_OFFSET 0x44 /* TX FIFO Trigger Level */
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#define CDNS_UART_CR 0x00 /* Control Register */
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#define CDNS_UART_MR 0x04 /* Mode Register */
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#define CDNS_UART_IER 0x08 /* Interrupt Enable */
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#define CDNS_UART_IDR 0x0C /* Interrupt Disable */
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#define CDNS_UART_IMR 0x10 /* Interrupt Mask */
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#define CDNS_UART_ISR 0x14 /* Interrupt Status */
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#define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */
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#define CDNS_UART_RXTOUT 0x1C /* RX Timeout */
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#define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */
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#define CDNS_UART_MODEMCR 0x24 /* Modem Control */
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#define CDNS_UART_MODEMSR 0x28 /* Modem Status */
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#define CDNS_UART_SR 0x2C /* Channel Status */
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#define CDNS_UART_FIFO 0x30 /* FIFO */
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#define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */
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#define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */
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#define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */
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#define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */
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#define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */
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/* Control Register Bit Definitions */
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#define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */
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@ -184,15 +184,14 @@ static void cdns_uart_handle_rx(struct uart_port *port, unsigned int isrstatus)
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* there's another non-zero byte at the end of the sequence.
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*/
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if (isrstatus & CDNS_UART_IXR_FRAMING) {
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while (!(readl(port->membase + CDNS_UART_SR_OFFSET) &
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while (!(readl(port->membase + CDNS_UART_SR) &
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CDNS_UART_SR_RXEMPTY)) {
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if (!readl(port->membase + CDNS_UART_FIFO_OFFSET)) {
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if (!readl(port->membase + CDNS_UART_FIFO)) {
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port->read_status_mask |= CDNS_UART_IXR_BRK;
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isrstatus &= ~CDNS_UART_IXR_FRAMING;
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}
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}
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writel(CDNS_UART_IXR_FRAMING,
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port->membase + CDNS_UART_ISR_OFFSET);
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writel(CDNS_UART_IXR_FRAMING, port->membase + CDNS_UART_ISR);
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}
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/* drop byte with parity error if IGNPAR specified */
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@ -205,12 +204,11 @@ static void cdns_uart_handle_rx(struct uart_port *port, unsigned int isrstatus)
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if (!(isrstatus & (CDNS_UART_IXR_TOUT | CDNS_UART_IXR_RXTRIG)))
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return;
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while (!(readl(port->membase + CDNS_UART_SR_OFFSET) &
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CDNS_UART_SR_RXEMPTY)) {
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while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)) {
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u32 data;
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char status = TTY_NORMAL;
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data = readl(port->membase + CDNS_UART_FIFO_OFFSET);
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data = readl(port->membase + CDNS_UART_FIFO);
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/* Non-NULL byte after BREAK is garbage (99%) */
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if (data && (port->read_status_mask & CDNS_UART_IXR_BRK)) {
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@ -259,7 +257,7 @@ static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
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/* Read the interrupt status register to determine which
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* interrupt(s) is/are active.
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*/
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isrstatus = readl(port->membase + CDNS_UART_ISR_OFFSET);
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isrstatus = readl(port->membase + CDNS_UART_ISR);
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if (isrstatus & CDNS_UART_RX_IRQS)
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cdns_uart_handle_rx(port, isrstatus);
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@ -268,7 +266,7 @@ static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
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if ((isrstatus & CDNS_UART_IXR_TXEMPTY) == CDNS_UART_IXR_TXEMPTY) {
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if (uart_circ_empty(&port->state->xmit)) {
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writel(CDNS_UART_IXR_TXEMPTY,
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port->membase + CDNS_UART_IDR_OFFSET);
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port->membase + CDNS_UART_IDR);
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} else {
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numbytes = port->fifosize;
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/* Break if no more data available in the UART buffer */
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@ -281,7 +279,7 @@ static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
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*/
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writel(port->state->xmit.buf[
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port->state->xmit.tail],
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port->membase + CDNS_UART_FIFO_OFFSET);
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port->membase + CDNS_UART_FIFO);
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port->icount.tx++;
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@ -299,7 +297,7 @@ static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
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}
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}
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writel(isrstatus, port->membase + CDNS_UART_ISR_OFFSET);
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writel(isrstatus, port->membase + CDNS_UART_ISR);
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/* be sure to release the lock and tty before leaving */
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spin_unlock_irqrestore(&port->lock, flags);
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@ -389,14 +387,14 @@ static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
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&div8);
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/* Write new divisors to hardware */
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mreg = readl(port->membase + CDNS_UART_MR_OFFSET);
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mreg = readl(port->membase + CDNS_UART_MR);
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if (div8)
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mreg |= CDNS_UART_MR_CLKSEL;
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else
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mreg &= ~CDNS_UART_MR_CLKSEL;
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writel(mreg, port->membase + CDNS_UART_MR_OFFSET);
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writel(cd, port->membase + CDNS_UART_BAUDGEN_OFFSET);
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writel(bdiv, port->membase + CDNS_UART_BAUDDIV_OFFSET);
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writel(mreg, port->membase + CDNS_UART_MR);
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writel(cd, port->membase + CDNS_UART_BAUDGEN);
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writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
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cdns_uart->baud = baud;
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return calc_baud;
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@ -443,9 +441,9 @@ static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
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spin_lock_irqsave(&cdns_uart->port->lock, flags);
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/* Disable the TX and RX to set baud rate */
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ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET);
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ctrl_reg = readl(port->membase + CDNS_UART_CR);
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ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
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writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET);
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writel(ctrl_reg, port->membase + CDNS_UART_CR);
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spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
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@ -470,11 +468,11 @@ static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
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spin_lock_irqsave(&cdns_uart->port->lock, flags);
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/* Set TX/RX Reset */
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ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET);
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ctrl_reg = readl(port->membase + CDNS_UART_CR);
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ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
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writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET);
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writel(ctrl_reg, port->membase + CDNS_UART_CR);
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while (readl(port->membase + CDNS_UART_CR_OFFSET) &
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while (readl(port->membase + CDNS_UART_CR) &
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(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
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cpu_relax();
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@ -483,11 +481,11 @@ static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
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* enable bit and RX enable bit to enable the transmitter and
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* receiver.
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*/
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writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET);
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ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET);
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writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
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ctrl_reg = readl(port->membase + CDNS_UART_CR);
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ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
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ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
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writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET);
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writel(ctrl_reg, port->membase + CDNS_UART_CR);
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spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
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@ -513,15 +511,15 @@ static void cdns_uart_start_tx(struct uart_port *port)
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* Set the TX enable bit and clear the TX disable bit to enable the
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* transmitter.
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*/
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status = readl(port->membase + CDNS_UART_CR_OFFSET);
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status = readl(port->membase + CDNS_UART_CR);
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status &= ~CDNS_UART_CR_TX_DIS;
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status |= CDNS_UART_CR_TX_EN;
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writel(status, port->membase + CDNS_UART_CR_OFFSET);
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writel(status, port->membase + CDNS_UART_CR);
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if (uart_circ_empty(&port->state->xmit))
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return;
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while (numbytes-- && ((readl(port->membase + CDNS_UART_SR_OFFSET) &
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while (numbytes-- && ((readl(port->membase + CDNS_UART_SR) &
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CDNS_UART_SR_TXFULL)) != CDNS_UART_SR_TXFULL) {
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/* Break if no more data available in the UART buffer */
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if (uart_circ_empty(&port->state->xmit))
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@ -531,7 +529,7 @@ static void cdns_uart_start_tx(struct uart_port *port)
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* write it to the cdns_uart's TX_FIFO register.
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*/
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writel(port->state->xmit.buf[port->state->xmit.tail],
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port->membase + CDNS_UART_FIFO_OFFSET);
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port->membase + CDNS_UART_FIFO);
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port->icount.tx++;
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/* Adjust the tail of the UART buffer and wrap
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@ -540,9 +538,9 @@ static void cdns_uart_start_tx(struct uart_port *port)
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port->state->xmit.tail = (port->state->xmit.tail + 1) &
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(UART_XMIT_SIZE - 1);
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}
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writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR_OFFSET);
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writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
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/* Enable the TX Empty interrupt */
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writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER_OFFSET);
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writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
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if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS)
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uart_write_wakeup(port);
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@ -556,10 +554,10 @@ static void cdns_uart_stop_tx(struct uart_port *port)
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{
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unsigned int regval;
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regval = readl(port->membase + CDNS_UART_CR_OFFSET);
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regval = readl(port->membase + CDNS_UART_CR);
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regval |= CDNS_UART_CR_TX_DIS;
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/* Disable the transmitter */
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writel(regval, port->membase + CDNS_UART_CR_OFFSET);
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writel(regval, port->membase + CDNS_UART_CR);
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}
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/**
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@ -571,12 +569,12 @@ static void cdns_uart_stop_rx(struct uart_port *port)
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unsigned int regval;
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/* Disable RX IRQs */
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writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR_OFFSET);
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writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
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/* Disable the receiver */
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regval = readl(port->membase + CDNS_UART_CR_OFFSET);
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regval = readl(port->membase + CDNS_UART_CR);
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regval |= CDNS_UART_CR_RX_DIS;
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writel(regval, port->membase + CDNS_UART_CR_OFFSET);
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writel(regval, port->membase + CDNS_UART_CR);
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}
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/**
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@ -589,7 +587,7 @@ static unsigned int cdns_uart_tx_empty(struct uart_port *port)
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{
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unsigned int status;
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status = readl(port->membase + CDNS_UART_SR_OFFSET) &
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status = readl(port->membase + CDNS_UART_SR) &
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CDNS_UART_SR_TXEMPTY;
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return status ? TIOCSER_TEMT : 0;
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}
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@ -607,15 +605,15 @@ static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
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spin_lock_irqsave(&port->lock, flags);
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status = readl(port->membase + CDNS_UART_CR_OFFSET);
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status = readl(port->membase + CDNS_UART_CR);
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if (ctl == -1)
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writel(CDNS_UART_CR_STARTBRK | status,
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port->membase + CDNS_UART_CR_OFFSET);
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port->membase + CDNS_UART_CR);
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else {
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if ((status & CDNS_UART_CR_STOPBRK) == 0)
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writel(CDNS_UART_CR_STOPBRK | status,
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port->membase + CDNS_UART_CR_OFFSET);
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port->membase + CDNS_UART_CR);
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}
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spin_unlock_irqrestore(&port->lock, flags);
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}
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@ -638,18 +636,18 @@ static void cdns_uart_set_termios(struct uart_port *port,
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spin_lock_irqsave(&port->lock, flags);
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/* Wait for the transmit FIFO to empty before making changes */
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if (!(readl(port->membase + CDNS_UART_CR_OFFSET) &
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if (!(readl(port->membase + CDNS_UART_CR) &
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CDNS_UART_CR_TX_DIS)) {
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while (!(readl(port->membase + CDNS_UART_SR_OFFSET) &
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while (!(readl(port->membase + CDNS_UART_SR) &
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CDNS_UART_SR_TXEMPTY)) {
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cpu_relax();
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}
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}
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/* Disable the TX and RX to set baud rate */
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ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET);
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ctrl_reg = readl(port->membase + CDNS_UART_CR);
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ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
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writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET);
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writel(ctrl_reg, port->membase + CDNS_UART_CR);
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/*
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* Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
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@ -668,20 +666,20 @@ static void cdns_uart_set_termios(struct uart_port *port,
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uart_update_timeout(port, termios->c_cflag, baud);
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/* Set TX/RX Reset */
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ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET);
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ctrl_reg = readl(port->membase + CDNS_UART_CR);
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ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
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writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET);
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writel(ctrl_reg, port->membase + CDNS_UART_CR);
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/*
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* Clear the RX disable and TX disable bits and then set the TX enable
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* bit and RX enable bit to enable the transmitter and receiver.
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*/
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ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET);
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ctrl_reg = readl(port->membase + CDNS_UART_CR);
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ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
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ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
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writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET);
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writel(ctrl_reg, port->membase + CDNS_UART_CR);
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writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET);
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writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
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port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
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CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
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@ -701,7 +699,7 @@ static void cdns_uart_set_termios(struct uart_port *port,
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CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
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CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
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mode_reg = readl(port->membase + CDNS_UART_MR_OFFSET);
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mode_reg = readl(port->membase + CDNS_UART_MR);
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/* Handling Data Size */
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switch (termios->c_cflag & CSIZE) {
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@ -742,7 +740,7 @@ static void cdns_uart_set_termios(struct uart_port *port,
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cval |= CDNS_UART_MR_PARITY_NONE;
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}
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cval |= mode_reg & 1;
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writel(cval, port->membase + CDNS_UART_MR_OFFSET);
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writel(cval, port->membase + CDNS_UART_MR);
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spin_unlock_irqrestore(&port->lock, flags);
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}
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@ -763,45 +761,45 @@ static int cdns_uart_startup(struct uart_port *port)
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/* Disable the TX and RX */
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writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
|
||||
port->membase + CDNS_UART_CR_OFFSET);
|
||||
port->membase + CDNS_UART_CR);
|
||||
|
||||
/* Set the Control Register with TX/RX Enable, TX/RX Reset,
|
||||
* no break chars.
|
||||
*/
|
||||
writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
|
||||
port->membase + CDNS_UART_CR_OFFSET);
|
||||
port->membase + CDNS_UART_CR);
|
||||
|
||||
/*
|
||||
* Clear the RX disable bit and then set the RX enable bit to enable
|
||||
* the receiver.
|
||||
*/
|
||||
status = readl(port->membase + CDNS_UART_CR_OFFSET);
|
||||
status = readl(port->membase + CDNS_UART_CR);
|
||||
status &= CDNS_UART_CR_RX_DIS;
|
||||
status |= CDNS_UART_CR_RX_EN;
|
||||
writel(status, port->membase + CDNS_UART_CR_OFFSET);
|
||||
writel(status, port->membase + CDNS_UART_CR);
|
||||
|
||||
/* Set the Mode Register with normal mode,8 data bits,1 stop bit,
|
||||
* no parity.
|
||||
*/
|
||||
writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
|
||||
| CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
|
||||
port->membase + CDNS_UART_MR_OFFSET);
|
||||
port->membase + CDNS_UART_MR);
|
||||
|
||||
/*
|
||||
* Set the RX FIFO Trigger level to use most of the FIFO, but it
|
||||
* can be tuned with a module parameter
|
||||
*/
|
||||
writel(rx_trigger_level, port->membase + CDNS_UART_RXWM_OFFSET);
|
||||
writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
|
||||
|
||||
/*
|
||||
* Receive Timeout register is enabled but it
|
||||
* can be tuned with a module parameter
|
||||
*/
|
||||
writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET);
|
||||
writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
|
||||
|
||||
/* Clear out any pending interrupts before enabling them */
|
||||
writel(readl(port->membase + CDNS_UART_ISR_OFFSET),
|
||||
port->membase + CDNS_UART_ISR_OFFSET);
|
||||
writel(readl(port->membase + CDNS_UART_ISR),
|
||||
port->membase + CDNS_UART_ISR);
|
||||
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
|
||||
|
|
@ -813,7 +811,7 @@ static int cdns_uart_startup(struct uart_port *port)
|
|||
}
|
||||
|
||||
/* Set the Interrupt Registers with desired interrupts */
|
||||
writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER_OFFSET);
|
||||
writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -830,13 +828,13 @@ static void cdns_uart_shutdown(struct uart_port *port)
|
|||
spin_lock_irqsave(&port->lock, flags);
|
||||
|
||||
/* Disable interrupts */
|
||||
status = readl(port->membase + CDNS_UART_IMR_OFFSET);
|
||||
writel(status, port->membase + CDNS_UART_IDR_OFFSET);
|
||||
writel(0xffffffff, port->membase + CDNS_UART_ISR_OFFSET);
|
||||
status = readl(port->membase + CDNS_UART_IMR);
|
||||
writel(status, port->membase + CDNS_UART_IDR);
|
||||
writel(0xffffffff, port->membase + CDNS_UART_ISR);
|
||||
|
||||
/* Disable the TX and RX */
|
||||
writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
|
||||
port->membase + CDNS_UART_CR_OFFSET);
|
||||
port->membase + CDNS_UART_CR);
|
||||
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
|
||||
|
|
@ -941,7 +939,7 @@ static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
|
|||
{
|
||||
u32 val;
|
||||
|
||||
val = readl(port->membase + CDNS_UART_MODEMCR_OFFSET);
|
||||
val = readl(port->membase + CDNS_UART_MODEMCR);
|
||||
|
||||
val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR);
|
||||
|
||||
|
|
@ -950,7 +948,7 @@ static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
|
|||
if (mctrl & TIOCM_DTR)
|
||||
val |= CDNS_UART_MODEMCR_DTR;
|
||||
|
||||
writel(val, port->membase + CDNS_UART_MODEMCR_OFFSET);
|
||||
writel(val, port->membase + CDNS_UART_MODEMCR);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CONSOLE_POLL
|
||||
|
|
@ -962,11 +960,10 @@ static int cdns_uart_poll_get_char(struct uart_port *port)
|
|||
spin_lock_irqsave(&port->lock, flags);
|
||||
|
||||
/* Check if FIFO is empty */
|
||||
if (readl(port->membase + CDNS_UART_SR_OFFSET) & CDNS_UART_SR_RXEMPTY)
|
||||
if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
|
||||
c = NO_POLL_CHAR;
|
||||
else /* Read a character */
|
||||
c = (unsigned char) readl(
|
||||
port->membase + CDNS_UART_FIFO_OFFSET);
|
||||
c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
|
||||
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
|
||||
|
|
@ -980,16 +977,14 @@ static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
|
|||
spin_lock_irqsave(&port->lock, flags);
|
||||
|
||||
/* Wait until FIFO is empty */
|
||||
while (!(readl(port->membase + CDNS_UART_SR_OFFSET) &
|
||||
CDNS_UART_SR_TXEMPTY))
|
||||
while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
|
||||
cpu_relax();
|
||||
|
||||
/* Write a character */
|
||||
writel(c, port->membase + CDNS_UART_FIFO_OFFSET);
|
||||
writel(c, port->membase + CDNS_UART_FIFO);
|
||||
|
||||
/* Wait until FIFO is empty */
|
||||
while (!(readl(port->membase + CDNS_UART_SR_OFFSET) &
|
||||
CDNS_UART_SR_TXEMPTY))
|
||||
while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
|
||||
cpu_relax();
|
||||
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
|
|
@ -1066,8 +1061,7 @@ static struct uart_port *cdns_uart_get_port(int id)
|
|||
*/
|
||||
static void cdns_uart_console_wait_tx(struct uart_port *port)
|
||||
{
|
||||
while (!(readl(port->membase + CDNS_UART_SR_OFFSET) &
|
||||
CDNS_UART_SR_TXEMPTY))
|
||||
while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
|
||||
barrier();
|
||||
}
|
||||
|
||||
|
|
@ -1079,7 +1073,7 @@ static void cdns_uart_console_wait_tx(struct uart_port *port)
|
|||
static void cdns_uart_console_putchar(struct uart_port *port, int ch)
|
||||
{
|
||||
cdns_uart_console_wait_tx(port);
|
||||
writel(ch, port->membase + CDNS_UART_FIFO_OFFSET);
|
||||
writel(ch, port->membase + CDNS_UART_FIFO);
|
||||
}
|
||||
|
||||
static void __init cdns_early_write(struct console *con, const char *s,
|
||||
|
|
@ -1124,25 +1118,25 @@ static void cdns_uart_console_write(struct console *co, const char *s,
|
|||
spin_lock_irqsave(&port->lock, flags);
|
||||
|
||||
/* save and disable interrupt */
|
||||
imr = readl(port->membase + CDNS_UART_IMR_OFFSET);
|
||||
writel(imr, port->membase + CDNS_UART_IDR_OFFSET);
|
||||
imr = readl(port->membase + CDNS_UART_IMR);
|
||||
writel(imr, port->membase + CDNS_UART_IDR);
|
||||
|
||||
/*
|
||||
* Make sure that the tx part is enabled. Set the TX enable bit and
|
||||
* clear the TX disable bit to enable the transmitter.
|
||||
*/
|
||||
ctrl = readl(port->membase + CDNS_UART_CR_OFFSET);
|
||||
ctrl = readl(port->membase + CDNS_UART_CR);
|
||||
ctrl &= ~CDNS_UART_CR_TX_DIS;
|
||||
ctrl |= CDNS_UART_CR_TX_EN;
|
||||
writel(ctrl, port->membase + CDNS_UART_CR_OFFSET);
|
||||
writel(ctrl, port->membase + CDNS_UART_CR);
|
||||
|
||||
uart_console_write(port, s, count, cdns_uart_console_putchar);
|
||||
cdns_uart_console_wait_tx(port);
|
||||
|
||||
writel(ctrl, port->membase + CDNS_UART_CR_OFFSET);
|
||||
writel(ctrl, port->membase + CDNS_UART_CR);
|
||||
|
||||
/* restore interrupt state */
|
||||
writel(imr, port->membase + CDNS_UART_IER_OFFSET);
|
||||
writel(imr, port->membase + CDNS_UART_IER);
|
||||
|
||||
if (locked)
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
|
|
@ -1254,14 +1248,13 @@ static int cdns_uart_suspend(struct device *device)
|
|||
|
||||
spin_lock_irqsave(&port->lock, flags);
|
||||
/* Empty the receive FIFO 1st before making changes */
|
||||
while (!(readl(port->membase + CDNS_UART_SR_OFFSET) &
|
||||
while (!(readl(port->membase + CDNS_UART_SR) &
|
||||
CDNS_UART_SR_RXEMPTY))
|
||||
readl(port->membase + CDNS_UART_FIFO_OFFSET);
|
||||
readl(port->membase + CDNS_UART_FIFO);
|
||||
/* set RX trigger level to 1 */
|
||||
writel(1, port->membase + CDNS_UART_RXWM_OFFSET);
|
||||
writel(1, port->membase + CDNS_UART_RXWM);
|
||||
/* disable RX timeout interrups */
|
||||
writel(CDNS_UART_IXR_TOUT,
|
||||
port->membase + CDNS_UART_IDR_OFFSET);
|
||||
writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
}
|
||||
|
||||
|
|
@ -1300,30 +1293,28 @@ static int cdns_uart_resume(struct device *device)
|
|||
spin_lock_irqsave(&port->lock, flags);
|
||||
|
||||
/* Set TX/RX Reset */
|
||||
ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET);
|
||||
ctrl_reg = readl(port->membase + CDNS_UART_CR);
|
||||
ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
|
||||
writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET);
|
||||
while (readl(port->membase + CDNS_UART_CR_OFFSET) &
|
||||
writel(ctrl_reg, port->membase + CDNS_UART_CR);
|
||||
while (readl(port->membase + CDNS_UART_CR) &
|
||||
(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
|
||||
cpu_relax();
|
||||
|
||||
/* restore rx timeout value */
|
||||
writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET);
|
||||
writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
|
||||
/* Enable Tx/Rx */
|
||||
ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET);
|
||||
ctrl_reg = readl(port->membase + CDNS_UART_CR);
|
||||
ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
|
||||
ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
|
||||
writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET);
|
||||
writel(ctrl_reg, port->membase + CDNS_UART_CR);
|
||||
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
} else {
|
||||
spin_lock_irqsave(&port->lock, flags);
|
||||
/* restore original rx trigger level */
|
||||
writel(rx_trigger_level,
|
||||
port->membase + CDNS_UART_RXWM_OFFSET);
|
||||
writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
|
||||
/* enable RX timeout interrupt */
|
||||
writel(CDNS_UART_IXR_TOUT,
|
||||
port->membase + CDNS_UART_IER_OFFSET);
|
||||
writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue