MIPS: Emulate the new MIPS R6 B{L,G}Ε{Z,}{AL,}C instructions
MIPS R6 added the following four instructions which share the BLEZ and BLEZL opcodes: BLEZALC: Compact branch-and-link if GPR rt is <= to zero BGEZALC: Compact branch-and-link if GPR rt is >= to zero BLEZC : Compact branch if GPR rt is <= to zero BGEZC : Compact branch if GPR rt is >= to zero BGEC : Compact branch if GPR rs is less than or equal to GPR rt BGEUC : Similar to BGEC but unsigned. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
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@ -399,6 +399,16 @@ int __MIPS16e_compute_return_epc(struct pt_regs *regs)
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* @returns: -EFAULT on error and forces SIGBUS, and on success
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* returns 0 or BRANCH_LIKELY_TAKEN as appropriate after
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* evaluating the branch.
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*
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* MIPS R6 Compact branches and forbidden slots:
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* Compact branches do not throw exceptions because they do
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* not have delay slots. The forbidden slot instruction ($PC+4)
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* is only executed if the branch was not taken. Otherwise the
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* forbidden slot is skipped entirely. This means that the
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* only possible reason to be here because of a MIPS R6 compact
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* branch instruction is that the forbidden slot has thrown one.
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* In that case the branch was not taken, so the EPC can be safely
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* set to EPC + 8.
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*/
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int __compute_return_epc_for_insn(struct pt_regs *regs,
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union mips_instruction insn)
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@ -590,6 +600,27 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
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if (NO_R6EMU)
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goto sigill_r6;
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case blez_op:
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/*
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* Compact branches for R6 for the
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* blez and blezl opcodes.
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* BLEZ | rs = 0 | rt != 0 == BLEZALC
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* BLEZ | rs = rt != 0 == BGEZALC
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* BLEZ | rs != 0 | rt != 0 == BGEUC
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* BLEZL | rs = 0 | rt != 0 == BLEZC
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* BLEZL | rs = rt != 0 == BGEZC
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* BLEZL | rs != 0 | rt != 0 == BGEC
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*
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* For real BLEZ{,L}, rt is always 0.
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*/
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if (cpu_has_mips_r6 && insn.i_format.rt) {
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if ((insn.i_format.opcode == blez_op) &&
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((!insn.i_format.rs && insn.i_format.rt) ||
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(insn.i_format.rs == insn.i_format.rt)))
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regs->regs[31] = epc + 4;
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regs->cp0_epc += 8;
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break;
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}
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/* rt field assumed to be zero */
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if ((long)regs->regs[insn.i_format.rs] <= 0) {
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epc = epc + 4 + (insn.i_format.simmediate << 2);
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@ -552,6 +552,30 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
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if (NO_R6EMU)
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break;
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case blez_op:
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/*
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* Compact branches for R6 for the
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* blez and blezl opcodes.
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* BLEZ | rs = 0 | rt != 0 == BLEZALC
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* BLEZ | rs = rt != 0 == BGEZALC
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* BLEZ | rs != 0 | rt != 0 == BGEUC
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* BLEZL | rs = 0 | rt != 0 == BLEZC
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* BLEZL | rs = rt != 0 == BGEZC
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* BLEZL | rs != 0 | rt != 0 == BGEC
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*
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* For real BLEZ{,L}, rt is always 0.
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*/
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if (cpu_has_mips_r6 && insn.i_format.rt) {
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if ((insn.i_format.opcode == blez_op) &&
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((!insn.i_format.rs && insn.i_format.rt) ||
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(insn.i_format.rs == insn.i_format.rt)))
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regs->regs[31] = regs->cp0_epc +
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dec_insn.pc_inc;
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*contpc = regs->cp0_epc + dec_insn.pc_inc +
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dec_insn.next_pc_inc;
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return 1;
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}
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if ((long)regs->regs[insn.i_format.rs] <= 0)
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*contpc = regs->cp0_epc +
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dec_insn.pc_inc +
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