xtensa: implement clear_user_highpage and copy_user_highpage
Existing clear_user_page and copy_user_page cannot be used with highmem because they calculate physical page address from its virtual address and do it incorrectly in case of high memory page mapped with kmap_atomic. Also kmap is not needed, as most likely userspace mapping color would be different from the kmapped color. Provide clear_user_highpage and copy_user_highpage functions that determine if temporary mapping is needed for the pages. Move most of the logic of the former clear_user_page and copy_user_page to xtensa/mm/cache.c only leaving temporary mapping setup, invalidation and clearing/copying in the xtensa/mm/misc.S. Rename these functions to clear_page_alias and copy_page_alias. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov
parent
7128039fe2
commit
a91902db29
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@ -37,6 +37,7 @@
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* specials for cache aliasing:
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*
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* __flush_invalidate_dcache_page_alias(vaddr,paddr)
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* __invalidate_dcache_page_alias(vaddr,paddr)
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* __invalidate_icache_page_alias(vaddr,paddr)
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*/
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@ -62,6 +63,7 @@ extern void __flush_invalidate_dcache_range(unsigned long, unsigned long);
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#if defined(CONFIG_MMU) && (DCACHE_WAY_SIZE > PAGE_SIZE)
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extern void __flush_invalidate_dcache_page_alias(unsigned long, unsigned long);
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extern void __invalidate_dcache_page_alias(unsigned long, unsigned long);
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#else
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static inline void __flush_invalidate_dcache_page_alias(unsigned long virt,
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unsigned long phys) { }
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@ -134,6 +134,7 @@ static inline __attribute_const__ int get_order(unsigned long size)
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#endif
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struct page;
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struct vm_area_struct;
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extern void clear_page(void *page);
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extern void copy_page(void *to, void *from);
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@ -143,8 +144,15 @@ extern void copy_page(void *to, void *from);
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*/
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#if DCACHE_WAY_SIZE > PAGE_SIZE
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extern void clear_user_page(void*, unsigned long, struct page*);
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extern void copy_user_page(void*, void*, unsigned long, struct page*);
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extern void clear_page_alias(void *vaddr, unsigned long paddr);
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extern void copy_page_alias(void *to, void *from,
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unsigned long to_paddr, unsigned long from_paddr);
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#define clear_user_highpage clear_user_highpage
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void clear_user_highpage(struct page *page, unsigned long vaddr);
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#define __HAVE_ARCH_COPY_USER_HIGHPAGE
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void copy_user_highpage(struct page *to, struct page *from,
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unsigned long vaddr, struct vm_area_struct *vma);
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#else
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# define clear_user_page(page, vaddr, pg) clear_page(page)
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# define copy_user_page(to, from, vaddr, pg) copy_page(to, from)
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@ -63,6 +63,69 @@
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#error "HIGHMEM is not supported on cores with aliasing cache."
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#endif
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#if (DCACHE_WAY_SIZE > PAGE_SIZE)
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static inline void kmap_invalidate_coherent(struct page *page,
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unsigned long vaddr)
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{
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if (!DCACHE_ALIAS_EQ(page_to_phys(page), vaddr)) {
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unsigned long kvaddr;
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if (!PageHighMem(page)) {
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kvaddr = (unsigned long)page_to_virt(page);
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__invalidate_dcache_page(kvaddr);
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} else {
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kvaddr = TLBTEMP_BASE_1 +
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(page_to_phys(page) & DCACHE_ALIAS_MASK);
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__invalidate_dcache_page_alias(kvaddr,
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page_to_phys(page));
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}
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}
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}
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static inline void *coherent_kvaddr(struct page *page, unsigned long base,
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unsigned long vaddr, unsigned long *paddr)
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{
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if (PageHighMem(page) || !DCACHE_ALIAS_EQ(page_to_phys(page), vaddr)) {
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*paddr = page_to_phys(page);
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return (void *)(base + (vaddr & DCACHE_ALIAS_MASK));
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} else {
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*paddr = 0;
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return page_to_virt(page);
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}
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}
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void clear_user_highpage(struct page *page, unsigned long vaddr)
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{
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unsigned long paddr;
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void *kvaddr = coherent_kvaddr(page, TLBTEMP_BASE_1, vaddr, &paddr);
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pagefault_disable();
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kmap_invalidate_coherent(page, vaddr);
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set_bit(PG_arch_1, &page->flags);
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clear_page_alias(kvaddr, paddr);
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pagefault_enable();
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}
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void copy_user_highpage(struct page *dst, struct page *src,
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unsigned long vaddr, struct vm_area_struct *vma)
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{
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unsigned long dst_paddr, src_paddr;
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void *dst_vaddr = coherent_kvaddr(dst, TLBTEMP_BASE_1, vaddr,
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&dst_paddr);
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void *src_vaddr = coherent_kvaddr(src, TLBTEMP_BASE_2, vaddr,
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&src_paddr);
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pagefault_disable();
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kmap_invalidate_coherent(dst, vaddr);
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set_bit(PG_arch_1, &dst->flags);
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copy_page_alias(dst_vaddr, src_vaddr, dst_paddr, src_paddr);
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pagefault_enable();
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}
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#endif /* DCACHE_WAY_SIZE > PAGE_SIZE */
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#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
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/*
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@ -110,41 +110,24 @@ ENTRY(__tlbtemp_mapping_start)
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#if (DCACHE_WAY_SIZE > PAGE_SIZE)
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/*
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* clear_user_page (void *addr, unsigned long vaddr, struct page *page)
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* a2 a3 a4
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* clear_page_alias(void *addr, unsigned long paddr)
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* a2 a3
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*/
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ENTRY(clear_user_page)
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ENTRY(clear_page_alias)
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entry a1, 32
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/* Mark page dirty and determine alias. */
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/* Skip setting up a temporary DTLB if not aliased low page. */
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movi a7, (1 << PG_ARCH_1)
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l32i a5, a4, PAGE_FLAGS
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xor a6, a2, a3
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extui a3, a3, PAGE_SHIFT, DCACHE_ALIAS_ORDER
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extui a6, a6, PAGE_SHIFT, DCACHE_ALIAS_ORDER
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or a5, a5, a7
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slli a3, a3, PAGE_SHIFT
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s32i a5, a4, PAGE_FLAGS
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movi a5, PAGE_OFFSET
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movi a6, 0
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beqz a3, 1f
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/* Skip setting up a temporary DTLB if not aliased. */
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beqz a6, 1f
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/* Invalidate kernel page. */
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mov a10, a2
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call8 __invalidate_dcache_page
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/* Setup a temporary DTLB with the color of the VPN */
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movi a4, ((PAGE_KERNEL | _PAGE_HW_WRITE) - PAGE_OFFSET) & 0xffffffff
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movi a5, TLBTEMP_BASE_1 # virt
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add a6, a2, a4 # ppn
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add a2, a5, a3 # add 'color'
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/* Setup a temporary DTLB for the addr. */
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addi a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE)
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mov a4, a2
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wdtlb a6, a2
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dsync
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@ -165,62 +148,43 @@ ENTRY(clear_user_page)
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/* We need to invalidate the temporary idtlb entry, if any. */
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1: addi a2, a2, -PAGE_SIZE
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idtlb a2
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1: idtlb a4
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dsync
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retw
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ENDPROC(clear_user_page)
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ENDPROC(clear_page_alias)
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/*
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* copy_page_user (void *to, void *from, unsigned long vaddr, struct page *page)
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* a2 a3 a4 a5
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* copy_page_alias(void *to, void *from,
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* a2 a3
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* unsigned long to_paddr, unsigned long from_paddr)
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* a4 a5
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*/
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ENTRY(copy_user_page)
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ENTRY(copy_page_alias)
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entry a1, 32
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/* Mark page dirty and determine alias for destination. */
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/* Skip setting up a temporary DTLB for destination if not aliased. */
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movi a8, (1 << PG_ARCH_1)
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l32i a9, a5, PAGE_FLAGS
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xor a6, a2, a4
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xor a7, a3, a4
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extui a4, a4, PAGE_SHIFT, DCACHE_ALIAS_ORDER
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extui a6, a6, PAGE_SHIFT, DCACHE_ALIAS_ORDER
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extui a7, a7, PAGE_SHIFT, DCACHE_ALIAS_ORDER
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or a9, a9, a8
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slli a4, a4, PAGE_SHIFT
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s32i a9, a5, PAGE_FLAGS
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movi a5, ((PAGE_KERNEL | _PAGE_HW_WRITE) - PAGE_OFFSET) & 0xffffffff
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movi a6, 0
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movi a7, 0
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beqz a4, 1f
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beqz a6, 1f
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/* Invalidate dcache */
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mov a10, a2
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call8 __invalidate_dcache_page
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/* Setup a temporary DTLB with a matching color. */
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movi a8, TLBTEMP_BASE_1 # base
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add a6, a2, a5 # ppn
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add a2, a8, a4 # add 'color'
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/* Setup a temporary DTLB for destination. */
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addi a6, a4, (PAGE_KERNEL | _PAGE_HW_WRITE)
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wdtlb a6, a2
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dsync
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/* Skip setting up a temporary DTLB for destination if not aliased. */
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/* Skip setting up a temporary DTLB for source if not aliased. */
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1: beqz a7, 1f
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1: beqz a5, 1f
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/* Setup a temporary DTLB with a matching color. */
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/* Setup a temporary DTLB for source. */
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movi a8, TLBTEMP_BASE_2 # base
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add a7, a3, a5 # ppn
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add a3, a8, a4
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addi a7, a5, PAGE_KERNEL
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addi a8, a3, 1 # way1
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wdtlb a7, a8
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@ -271,7 +235,7 @@ ENTRY(copy_user_page)
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retw
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ENDPROC(copy_user_page)
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ENDPROC(copy_page_alias)
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#endif
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@ -300,6 +264,30 @@ ENTRY(__flush_invalidate_dcache_page_alias)
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retw
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ENDPROC(__flush_invalidate_dcache_page_alias)
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/*
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* void __invalidate_dcache_page_alias (addr, phys)
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* a2 a3
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*/
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ENTRY(__invalidate_dcache_page_alias)
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entry sp, 16
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movi a7, 0 # required for exception handler
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addi a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE)
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mov a4, a2
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wdtlb a6, a2
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dsync
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___invalidate_dcache_page a2 a3
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idtlb a4
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dsync
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retw
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ENDPROC(__invalidate_dcache_page_alias)
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#endif
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ENTRY(__tlbtemp_mapping_itlb)
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