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PM / devfreq: exynos: Add the detailed correlation for Exynos5422 bus 

This patch adds the detailed corrleation between sub-blocks and power line
for Exynos5422.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com>
This commit is contained in:
Chanwoo Choi 2015-11-27 13:03:59 +09:00 committed by MyungJoo Ham
parent 19cf91d0f9
commit a9d1f4e0cb
1 changed files with 19 additions and 0 deletions
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19
Documentation/devicetree/bindings/devfreq/exynos-bus.txt
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@ -104,6 +104,25 @@ Detailed correlation between sub-blocks and power line according to Exynos SoC:
|--- LCD0
|--- ISP
- In case of Exynos5422, there are two power line as following:
VDD_MIF |--- DREX 0 (parent device, DRAM EXpress controller)
|--- DREX 1
VDD_INT |--- NoC_Core (parent device)
|--- G2D
|--- G3D
|--- DISP1
|--- NoC_WCORE
|--- GSCL
|--- MSCL
|--- ISP
|--- MFC
|--- GEN
|--- PERIS
|--- PERIC
|--- FSYS
|--- FSYS2
Example1:
Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
power line (regulator). The MIF (Memory Interface) AXI bus is used to