arm: davinci: Use generic irq chip
Simple conversion which simply uses the fact that the second irq chip base address has offset 0x04 to the first one. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-and-Tested-by: Kevin Hilman <khilman@ti.com> Tested-by: Sekhar Nori <nsekhar@ti.com>
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@ -29,8 +29,6 @@
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#include <mach/common.h>
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#include <asm/mach/irq.h>
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#define IRQ_BIT(irq) ((irq) & 0x1f)
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#define FIQ_REG0_OFFSET 0x0000
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#define FIQ_REG1_OFFSET 0x0004
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#define IRQ_REG0_OFFSET 0x0008
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@ -42,78 +40,33 @@
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#define IRQ_INTPRI0_REG_OFFSET 0x0030
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#define IRQ_INTPRI7_REG_OFFSET 0x004C
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static inline unsigned int davinci_irq_readl(int offset)
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{
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return __raw_readl(davinci_intc_base + offset);
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}
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static inline void davinci_irq_writel(unsigned long value, int offset)
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{
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__raw_writel(value, davinci_intc_base + offset);
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}
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/* Disable interrupt */
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static void davinci_mask_irq(struct irq_data *d)
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static __init void
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davinci_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
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{
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unsigned int mask;
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u32 l;
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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mask = 1 << IRQ_BIT(d->irq);
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gc = irq_alloc_generic_chip("AINTC", 1, irq_start, base, handle_edge_irq);
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ct = gc->chip_types;
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ct->chip.irq_ack = irq_gc_ack;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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if (d->irq > 31) {
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l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
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l &= ~mask;
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davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
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} else {
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l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
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l &= ~mask;
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davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
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}
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ct->regs.ack = IRQ_REG0_OFFSET;
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ct->regs.mask = IRQ_ENT_REG0_OFFSET;
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irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
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IRQ_NOREQUEST | IRQ_NOPROBE, 0);
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}
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/* Enable interrupt */
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static void davinci_unmask_irq(struct irq_data *d)
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{
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unsigned int mask;
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u32 l;
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mask = 1 << IRQ_BIT(d->irq);
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if (d->irq > 31) {
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l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
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l |= mask;
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davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
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} else {
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l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
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l |= mask;
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davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
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}
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}
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/* EOI interrupt */
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static void davinci_ack_irq(struct irq_data *d)
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{
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unsigned int mask;
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mask = 1 << IRQ_BIT(d->irq);
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if (d->irq > 31)
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davinci_irq_writel(mask, IRQ_REG1_OFFSET);
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else
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davinci_irq_writel(mask, IRQ_REG0_OFFSET);
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}
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static struct irq_chip davinci_irq_chip_0 = {
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.name = "AINTC",
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.irq_ack = davinci_ack_irq,
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.irq_mask = davinci_mask_irq,
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.irq_unmask = davinci_unmask_irq,
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};
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/* ARM Interrupt Controller Initialization */
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void __init davinci_irq_init(void)
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{
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unsigned i;
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unsigned i, j;
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const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios;
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davinci_intc_type = DAVINCI_INTC_TYPE_AINTC;
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@ -144,7 +97,6 @@ void __init davinci_irq_init(void)
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davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
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for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) {
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unsigned j;
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u32 pri;
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for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++)
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@ -152,13 +104,8 @@ void __init davinci_irq_init(void)
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davinci_irq_writel(pri, i);
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}
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/* set up genirq dispatch for ARM INTC */
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for (i = 0; i < davinci_soc_info.intc_irq_num; i++) {
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irq_set_chip(i, &davinci_irq_chip_0);
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set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
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if (i != IRQ_TINT1_TINT34)
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irq_set_handler(i, handle_edge_irq);
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else
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irq_set_handler(i, handle_level_irq);
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}
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for (i = 0, j = 0; i < davinci_soc_info.intc_irq_num; i += 32, j += 0x04)
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davinci_alloc_gc(davinci_intc_base + j, i, 32);
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irq_set_handler(IRQ_TINT1_TINT34, handle_level_irq);
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}
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