drm/radeon: some r420s have a CP race with the DMA engine.
This patch makes sure the CP doesn't DMA do VRAM while 2D is active by inserting a CP resync token. todo: port to kms. Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -616,6 +616,18 @@ static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
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dev_priv->cp_running = 1;
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/* on r420, any DMA from CP to system memory while 2D is active
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* can cause a hang. workaround is to queue a CP RESYNC token
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*/
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if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
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BEGIN_RING(3);
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OUT_RING(CP_PACKET0(R300_CP_RESYNC_ADDR, 1));
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OUT_RING(5); /* scratch reg 5 */
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OUT_RING(0xdeadbeef);
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ADVANCE_RING();
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COMMIT_RING();
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}
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BEGIN_RING(8);
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/* isync can only be written through cp on r5xx write it here */
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OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
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@ -653,8 +665,19 @@ static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
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*/
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static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
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{
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RING_LOCALS;
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DRM_DEBUG("\n");
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/* finish the pending CP_RESYNC token */
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if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
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BEGIN_RING(2);
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OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
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OUT_RING(R300_RB3D_DC_FINISH);
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ADVANCE_RING();
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COMMIT_RING();
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radeon_do_wait_for_idle(dev_priv);
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}
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RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
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dev_priv->cp_running = 0;
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@ -1099,6 +1099,9 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
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# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
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# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
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#define R300_CP_RESYNC_ADDR 0x0778
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#define R300_CP_RESYNC_DATA 0x077c
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#define RADEON_AIC_CNTL 0x01d0
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# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
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# define RS400_MSI_REARM (1 << 3)
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