tools build: Add Makefile.include

To ease up build framework code setup for users.

More shared code will be added in the following patches.

Signed-off-by: Jiri Olsa <jolsa@kernel.org>
Cc: David Ahern <dsahern@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1443004442-32660-2-git-send-email-jolsa@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Jiri Olsa 2015-09-23 12:33:56 +02:00 committed by Arnaldo Carvalho de Melo
parent dc240c5dc2
commit ab6201d09b
7 changed files with 39 additions and 18 deletions

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@ -11,8 +11,9 @@ Unlike the kernel we don't have a single build object 'obj-y' list that where
we setup source objects, but we support more. This allows one 'Build' file to
carry a sources list for multiple build objects.
a) Build framework makefiles
----------------------------
Build framework makefiles
-------------------------
The build framework consists of 2 Makefiles:
@ -23,7 +24,7 @@ While the 'Build.include' file contains just some generic definitions, the
'Makefile.build' file is the makefile used from the outside. It's
interface/usage is following:
$ make -f tools/build/Makefile srctree=$(KSRC) dir=$(DIR) obj=$(OBJECT)
$ make -f tools/build/Makefile.build srctree=$(KSRC) dir=$(DIR) obj=$(OBJECT)
where:
@ -38,8 +39,9 @@ called $(OBJECT)-in.o:
which includes all compiled sources described in 'Build' makefiles.
a) Build makefiles
------------------
Build makefiles
---------------
The user supplies 'Build' makefiles that contains a objects list, and connects
the build to nested directories.
@ -95,8 +97,24 @@ It's only a matter of 2 single commands to create the final binaries:
You can check the 'ex' example in 'tools/build/tests/ex' for more details.
b) Rules
--------
Makefile.include
----------------
The tools/build/Makefile.include makefile could be included
via user makefiles to get usefull definitions.
It defines following interface:
- build macro definition:
build := -f $(srctree)/tools/build/Makefile.build dir=. obj
to make it easier to invoke build like:
make $(build)=ex
Rules
-----
The build framework provides standard compilation rules to handle .S and .c
compilation.
@ -104,8 +122,9 @@ compilation.
It's possible to include special rule if needed (like we do for flex or bison
code generation).
c) CFLAGS
---------
CFLAGS
------
It's possible to alter the standard object C flags in the following way:
@ -115,8 +134,8 @@ It's possible to alter the standard object C flags in the following way:
This C flags changes has the scope of the Build makefile they are defined in.
d) Dependencies
---------------
Dependencies
------------
For each built object file 'a.o' the '.a.cmd' is created and holds:
@ -130,8 +149,8 @@ All existing '.cmd' files are included in the Build process to follow properly
the dependencies and trigger a rebuild when necessary.
e) Single rules
---------------
Single rules
------------
It's possible to build single object file by choice, like:

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@ -0,0 +1 @@
build := -f $(srctree)/tools/build/Makefile.build dir=. obj

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@ -3,7 +3,8 @@ export CC := gcc
export LD := ld
export AR := ar
build := -f $(srctree)/tools/build/Makefile.build dir=. obj
include $(srctree)/tools/build/Makefile.include
ex: ex-in.o libex-in.o
gcc -o $@ $^

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@ -21,10 +21,10 @@ CFLAGS += -D_LARGEFILE64_SOURCE -D_FILE_OFFSET_BITS=64
RM = rm -f
build := -f $(srctree)/tools/build/Makefile.build dir=. obj
API_IN := $(OUTPUT)libapi-in.o
export srctree OUTPUT CC LD CFLAGS V
include $(srctree)/tools/build/Makefile.include
all: $(LIBFILE)

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@ -124,7 +124,7 @@ endif
MAKEOVERRIDES=
export srctree OUTPUT CC LD CFLAGS V
build := -f $(srctree)/tools/build/Makefile.build dir=. obj
include $(srctree)/tools/build/Makefile.include
BPF_IN := $(OUTPUT)libbpf-in.o
LIB_FILE := $(addprefix $(OUTPUT),$(LIB_FILE))

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@ -94,7 +94,7 @@ else
endif
export srctree OUTPUT CC LD CFLAGS V
build := -f $(srctree)/tools/build/Makefile.build dir=. obj
include $(srctree)/tools/build/Makefile.include
do_compile_shared_library = \
($(print_shared_lib_compile) \

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@ -297,7 +297,7 @@ strip: $(PROGRAMS) $(OUTPUT)perf
PERF_IN := $(OUTPUT)perf-in.o
export srctree OUTPUT RM CC LD AR CFLAGS V BISON FLEX AWK
build := -f $(srctree)/tools/build/Makefile.build dir=. obj
include $(srctree)/tools/build/Makefile.include
$(PERF_IN): $(OUTPUT)PERF-VERSION-FILE $(OUTPUT)common-cmds.h FORCE
$(Q)$(MAKE) $(build)=perf