clk: stm32f4: fix timeout management for pll and ready gate
Use a classic polling to test bit ready.
And the shift of the bit ready of LSE & LSI were wrongs.
Fixes: 861adc44d2
("clk: stm32f4: Add LSI & LSE clocks")
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
This commit is contained in:
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@ -531,19 +531,26 @@ static int stm32f4_pll_is_enabled(struct clk_hw *hw)
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return clk_gate_ops.is_enabled(hw);
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return clk_gate_ops.is_enabled(hw);
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}
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}
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#define PLL_TIMEOUT 10000
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static int stm32f4_pll_enable(struct clk_hw *hw)
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static int stm32f4_pll_enable(struct clk_hw *hw)
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{
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{
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struct clk_gate *gate = to_clk_gate(hw);
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struct clk_gate *gate = to_clk_gate(hw);
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struct stm32f4_pll *pll = to_stm32f4_pll(gate);
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struct stm32f4_pll *pll = to_stm32f4_pll(gate);
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int ret = 0;
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int bit_status;
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unsigned long reg;
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unsigned int timeout = PLL_TIMEOUT;
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ret = clk_gate_ops.enable(hw);
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if (clk_gate_ops.is_enabled(hw))
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return 0;
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ret = readl_relaxed_poll_timeout_atomic(base + STM32F4_RCC_CR, reg,
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clk_gate_ops.enable(hw);
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reg & (1 << pll->bit_rdy_idx), 0, 10000);
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return ret;
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do {
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bit_status = !(readl(gate->reg) & BIT(pll->bit_rdy_idx));
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} while (bit_status && --timeout);
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return bit_status;
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}
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}
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static void stm32f4_pll_disable(struct clk_hw *hw)
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static void stm32f4_pll_disable(struct clk_hw *hw)
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@ -834,24 +841,32 @@ struct stm32_rgate {
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u8 bit_rdy_idx;
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u8 bit_rdy_idx;
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};
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};
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#define RTC_TIMEOUT 1000000
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#define RGATE_TIMEOUT 50000
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static int rgclk_enable(struct clk_hw *hw)
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static int rgclk_enable(struct clk_hw *hw)
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{
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{
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struct clk_gate *gate = to_clk_gate(hw);
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struct clk_gate *gate = to_clk_gate(hw);
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struct stm32_rgate *rgate = to_rgclk(gate);
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struct stm32_rgate *rgate = to_rgclk(gate);
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u32 reg;
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int bit_status;
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int ret;
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unsigned int timeout = RGATE_TIMEOUT;
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if (clk_gate_ops.is_enabled(hw))
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return 0;
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disable_power_domain_write_protection();
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disable_power_domain_write_protection();
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clk_gate_ops.enable(hw);
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clk_gate_ops.enable(hw);
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ret = readl_relaxed_poll_timeout_atomic(gate->reg, reg,
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do {
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reg & rgate->bit_rdy_idx, 1000, RTC_TIMEOUT);
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bit_status = !(readl(gate->reg) & BIT(rgate->bit_rdy_idx));
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if (bit_status)
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udelay(100);
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} while (bit_status && --timeout);
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enable_power_domain_write_protection();
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enable_power_domain_write_protection();
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return ret;
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return bit_status;
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}
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}
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static void rgclk_disable(struct clk_hw *hw)
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static void rgclk_disable(struct clk_hw *hw)
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@ -1533,7 +1548,7 @@ static void __init stm32f4_rcc_init(struct device_node *np)
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}
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}
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clks[CLK_LSI] = clk_register_rgate(NULL, "lsi", "clk-lsi", 0,
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clks[CLK_LSI] = clk_register_rgate(NULL, "lsi", "clk-lsi", 0,
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base + STM32F4_RCC_CSR, 0, 2, 0, &stm32f4_clk_lock);
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base + STM32F4_RCC_CSR, 0, 1, 0, &stm32f4_clk_lock);
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if (IS_ERR(clks[CLK_LSI])) {
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if (IS_ERR(clks[CLK_LSI])) {
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pr_err("Unable to register lsi clock\n");
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pr_err("Unable to register lsi clock\n");
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@ -1541,7 +1556,7 @@ static void __init stm32f4_rcc_init(struct device_node *np)
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}
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}
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clks[CLK_LSE] = clk_register_rgate(NULL, "lse", "clk-lse", 0,
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clks[CLK_LSE] = clk_register_rgate(NULL, "lse", "clk-lse", 0,
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base + STM32F4_RCC_BDCR, 0, 2, 0, &stm32f4_clk_lock);
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base + STM32F4_RCC_BDCR, 0, 1, 0, &stm32f4_clk_lock);
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if (IS_ERR(clks[CLK_LSE])) {
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if (IS_ERR(clks[CLK_LSE])) {
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pr_err("Unable to register lse clock\n");
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pr_err("Unable to register lse clock\n");
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