cpufreq: exynos: remove exynos5250 specific cpufreq driver support
Exynos5250 based platforms have switched over to use generic cpufreq driver for cpufreq functionality. So the Exynos specific cpufreq support for these platforms can be removed. Cc: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org> Tested-by: Javier Martinez Canillas <javier@dowhile0.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> [k.kozlowski: Rebased the patch around exynos-cpufreq.c] Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
This commit is contained in:
Bartlomiej Zolnierkiewicz
Kukjin Kim
parent
d770e558e2
commit
ac4c90c82e
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@ -47,17 +47,6 @@ config ARM_EXYNOS4X12_CPUFREQ
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If in doubt, say N.
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config ARM_EXYNOS5250_CPUFREQ
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bool "SAMSUNG EXYNOS5250"
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depends on SOC_EXYNOS5250
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depends on ARM_EXYNOS_CPUFREQ
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default y
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help
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This adds the CPUFreq driver for Samsung EXYNOS5250
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SoC.
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If in doubt, say N.
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config ARM_EXYNOS_CPU_FREQ_BOOST_SW
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bool "EXYNOS Frequency Overclocking - Software"
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depends on ARM_EXYNOS_CPUFREQ && THERMAL
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@ -55,7 +55,6 @@ obj-$(CONFIG_UX500_SOC_DB8500) += dbx500-cpufreq.o
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obj-$(CONFIG_ARM_EXYNOS_CPUFREQ) += arm-exynos-cpufreq.o
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arm-exynos-cpufreq-y := exynos-cpufreq.o
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arm-exynos-cpufreq-$(CONFIG_ARM_EXYNOS4X12_CPUFREQ) += exynos4x12-cpufreq.o
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arm-exynos-cpufreq-$(CONFIG_ARM_EXYNOS5250_CPUFREQ) += exynos5250-cpufreq.o
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obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ) += exynos5440-cpufreq.o
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obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o
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obj-$(CONFIG_ARM_HISI_ACPU_CPUFREQ) += hisi-acpu-cpufreq.o
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@ -175,9 +175,6 @@ static int exynos_cpufreq_probe(struct platform_device *pdev)
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} else if (of_machine_is_compatible("samsung,exynos4412")) {
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exynos_info->type = EXYNOS_SOC_4412;
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ret = exynos4x12_cpufreq_init(exynos_info);
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} else if (of_machine_is_compatible("samsung,exynos5250")) {
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exynos_info->type = EXYNOS_SOC_5250;
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ret = exynos5250_cpufreq_init(exynos_info);
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} else {
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pr_err("%s: Unknown SoC type\n", __func__);
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return -ENODEV;
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@ -20,7 +20,6 @@ enum cpufreq_level_index {
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enum exynos_soc_type {
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EXYNOS_SOC_4212,
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EXYNOS_SOC_4412,
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EXYNOS_SOC_5250,
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};
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#define APLL_FREQ(f, a0, a1, a2, a3, a4, a5, a6, a7, b0, b1, b2, m, p, s) \
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@ -60,14 +59,6 @@ static inline int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
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return -EOPNOTSUPP;
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}
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#endif
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#ifdef CONFIG_ARM_EXYNOS5250_CPUFREQ
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extern int exynos5250_cpufreq_init(struct exynos_dvfs_info *);
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#else
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static inline int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
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{
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return -EOPNOTSUPP;
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}
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#endif
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#define EXYNOS4_CLKSRC_CPU 0x14200
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#define EXYNOS4_CLKMUX_STATCPU 0x14400
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@ -79,11 +70,3 @@ static inline int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
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#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16)
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#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)
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#define EXYNOS5_APLL_LOCK 0x00000
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#define EXYNOS5_APLL_CON0 0x00100
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#define EXYNOS5_CLKMUX_STATCPU 0x00400
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#define EXYNOS5_CLKDIV_CPU0 0x00500
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#define EXYNOS5_CLKDIV_CPU1 0x00504
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#define EXYNOS5_CLKDIV_STATCPU0 0x00600
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#define EXYNOS5_CLKDIV_STATCPU1 0x00604
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@ -1,210 +0,0 @@
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/*
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* Copyright (c) 2010-20122Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS5250 - CPU frequency scaling support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/cpufreq.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include "exynos-cpufreq.h"
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static struct clk *cpu_clk;
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static struct clk *moutcore;
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static struct clk *mout_mpll;
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static struct clk *mout_apll;
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static struct exynos_dvfs_info *cpufreq;
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static unsigned int exynos5250_volt_table[] = {
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1300000, 1250000, 1225000, 1200000, 1150000,
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1125000, 1100000, 1075000, 1050000, 1025000,
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1012500, 1000000, 975000, 950000, 937500,
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925000
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};
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static struct cpufreq_frequency_table exynos5250_freq_table[] = {
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{0, L0, 1700 * 1000},
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{0, L1, 1600 * 1000},
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{0, L2, 1500 * 1000},
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{0, L3, 1400 * 1000},
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{0, L4, 1300 * 1000},
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{0, L5, 1200 * 1000},
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{0, L6, 1100 * 1000},
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{0, L7, 1000 * 1000},
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{0, L8, 900 * 1000},
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{0, L9, 800 * 1000},
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{0, L10, 700 * 1000},
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{0, L11, 600 * 1000},
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{0, L12, 500 * 1000},
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{0, L13, 400 * 1000},
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{0, L14, 300 * 1000},
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{0, L15, 200 * 1000},
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{0, 0, CPUFREQ_TABLE_END},
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};
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static struct apll_freq apll_freq_5250[] = {
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/*
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* values:
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* freq
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* clock divider for ARM, CPUD, ACP, PERIPH, ATB, PCLK_DBG, APLL, ARM2
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* clock divider for COPY, HPM, RESERVED
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* PLL M, P, S
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*/
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APLL_FREQ(1700, 0, 3, 7, 7, 7, 3, 5, 0, 0, 2, 0, 425, 6, 0),
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APLL_FREQ(1600, 0, 3, 7, 7, 7, 1, 4, 0, 0, 2, 0, 200, 3, 0),
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APLL_FREQ(1500, 0, 2, 7, 7, 7, 1, 4, 0, 0, 2, 0, 250, 4, 0),
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APLL_FREQ(1400, 0, 2, 7, 7, 6, 1, 4, 0, 0, 2, 0, 175, 3, 0),
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APLL_FREQ(1300, 0, 2, 7, 7, 6, 1, 3, 0, 0, 2, 0, 325, 6, 0),
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APLL_FREQ(1200, 0, 2, 7, 7, 5, 1, 3, 0, 0, 2, 0, 200, 4, 0),
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APLL_FREQ(1100, 0, 3, 7, 7, 5, 1, 3, 0, 0, 2, 0, 275, 6, 0),
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APLL_FREQ(1000, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 125, 3, 0),
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APLL_FREQ(900, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 150, 4, 0),
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APLL_FREQ(800, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 100, 3, 0),
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APLL_FREQ(700, 0, 1, 7, 7, 3, 1, 1, 0, 0, 2, 0, 175, 3, 1),
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APLL_FREQ(600, 0, 1, 7, 7, 3, 1, 1, 0, 0, 2, 0, 200, 4, 1),
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APLL_FREQ(500, 0, 1, 7, 7, 2, 1, 1, 0, 0, 2, 0, 125, 3, 1),
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APLL_FREQ(400, 0, 1, 7, 7, 2, 1, 1, 0, 0, 2, 0, 100, 3, 1),
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APLL_FREQ(300, 0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 200, 4, 2),
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APLL_FREQ(200, 0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 100, 3, 2),
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};
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static void set_clkdiv(unsigned int div_index)
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{
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unsigned int tmp;
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/* Change Divider - CPU0 */
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tmp = apll_freq_5250[div_index].clk_div_cpu0;
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__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS5_CLKDIV_CPU0);
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while (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKDIV_STATCPU0)
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& 0x11111111)
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cpu_relax();
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/* Change Divider - CPU1 */
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tmp = apll_freq_5250[div_index].clk_div_cpu1;
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__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS5_CLKDIV_CPU1);
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while (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKDIV_STATCPU1) & 0x11)
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cpu_relax();
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}
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static void set_apll(unsigned int index)
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{
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unsigned int tmp;
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unsigned int freq = apll_freq_5250[index].freq;
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/* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
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clk_set_parent(moutcore, mout_mpll);
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do {
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cpu_relax();
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tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKMUX_STATCPU)
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>> 16);
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tmp &= 0x7;
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} while (tmp != 0x2);
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clk_set_rate(mout_apll, freq * 1000);
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/* MUX_CORE_SEL = APLL */
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clk_set_parent(moutcore, mout_apll);
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do {
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cpu_relax();
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tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKMUX_STATCPU);
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tmp &= (0x7 << 16);
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} while (tmp != (0x1 << 16));
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}
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static void exynos5250_set_frequency(unsigned int old_index,
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unsigned int new_index)
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{
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if (old_index > new_index) {
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set_clkdiv(new_index);
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set_apll(new_index);
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} else if (old_index < new_index) {
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set_apll(new_index);
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set_clkdiv(new_index);
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}
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}
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int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
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{
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struct device_node *np;
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unsigned long rate;
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/*
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* HACK: This is a temporary workaround to get access to clock
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* controller registers directly and remove static mappings and
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* dependencies on platform headers. It is necessary to enable
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* Exynos multi-platform support and will be removed together with
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* this whole driver as soon as Exynos gets migrated to use
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* cpufreq-dt driver.
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*/
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np = of_find_compatible_node(NULL, NULL, "samsung,exynos5250-clock");
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if (!np) {
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pr_err("%s: failed to find clock controller DT node\n",
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__func__);
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return -ENODEV;
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}
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info->cmu_regs = of_iomap(np, 0);
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if (!info->cmu_regs) {
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pr_err("%s: failed to map CMU registers\n", __func__);
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return -EFAULT;
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}
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cpu_clk = clk_get(NULL, "armclk");
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if (IS_ERR(cpu_clk))
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return PTR_ERR(cpu_clk);
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moutcore = clk_get(NULL, "mout_cpu");
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if (IS_ERR(moutcore))
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goto err_moutcore;
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mout_mpll = clk_get(NULL, "mout_mpll");
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if (IS_ERR(mout_mpll))
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goto err_mout_mpll;
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rate = clk_get_rate(mout_mpll) / 1000;
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mout_apll = clk_get(NULL, "mout_apll");
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if (IS_ERR(mout_apll))
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goto err_mout_apll;
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info->mpll_freq_khz = rate;
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/* 800Mhz */
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info->pll_safe_idx = L9;
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info->cpu_clk = cpu_clk;
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info->volt_table = exynos5250_volt_table;
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info->freq_table = exynos5250_freq_table;
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info->set_freq = exynos5250_set_frequency;
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cpufreq = info;
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return 0;
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err_mout_apll:
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clk_put(mout_mpll);
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err_mout_mpll:
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clk_put(moutcore);
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err_moutcore:
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clk_put(cpu_clk);
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pr_err("%s: failed initialization\n", __func__);
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return -EINVAL;
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}
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