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Merge branch 'master' into sh/smp 

Conflicts:
	arch/sh/mm/cache-sh4.c
This commit is contained in:
Paul Mundt 2009-09-01 13:54:14 +09:00
parent e76a0136a3 ce3f7cb96e
commit ac6a0cf671
414 changed files with 15153 additions and 2589 deletions
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26
Documentation/filesystems/afs.txt
View File

@ -23,16 +23,14 @@ it does support include:
(*) Security (currently only AFS kaserver and KerberosIV tickets).
(*) File reading.
(*) File reading and writing.
(*) Automounting.
(*) Local caching (via fscache).
It does not yet support the following AFS features:
(*) Write support.
(*) Local caching.
(*) pioctl() system call.
@ -56,7 +54,7 @@ They permit the debugging messages to be turned on dynamically by manipulating
the masks in the following files:
/sys/module/af_rxrpc/parameters/debug
/sys/module/afs/parameters/debug
/sys/module/kafs/parameters/debug
=====
@ -66,9 +64,9 @@ USAGE
When inserting the driver modules the root cell must be specified along with a
list of volume location server IP addresses:
insmod af_rxrpc.o
insmod rxkad.o
insmod kafs.o rootcell=cambridge.redhat.com:172.16.18.73:172.16.18.91
modprobe af_rxrpc
modprobe rxkad
modprobe kafs rootcell=cambridge.redhat.com:172.16.18.73:172.16.18.91
The first module is the AF_RXRPC network protocol driver. This provides the
RxRPC remote operation protocol and may also be accessed from userspace. See:
@ -81,7 +79,7 @@ is the actual filesystem driver for the AFS filesystem.
Once the module has been loaded, more modules can be added by the following
procedure:
echo add grand.central.org 18.7.14.88:128.2.191.224 >/proc/fs/afs/cells
echo add grand.central.org 18.9.48.14:128.2.203.61:130.237.48.87 >/proc/fs/afs/cells
Where the parameters to the "add" command are the name of a cell and a list of
volume location servers within that cell, with the latter separated by colons.
@ -101,7 +99,7 @@ The name of the volume can be suffixes with ".backup" or ".readonly" to
specify connection to only volumes of those types.
The name of the cell is optional, and if not given during a mount, then the
named volume will be looked up in the cell specified during insmod.
named volume will be looked up in the cell specified during modprobe.
Additional cells can be added through /proc (see later section).
@ -163,14 +161,14 @@ THE CELL DATABASE
The filesystem maintains an internal database of all the cells it knows and the
IP addresses of the volume location servers for those cells. The cell to which
the system belongs is added to the database when insmod is performed by the
the system belongs is added to the database when modprobe is performed by the
"rootcell=" argument or, if compiled in, using a "kafs.rootcell=" argument on
the kernel command line.
Further cells can be added by commands similar to the following:
echo add CELLNAME VLADDR[:VLADDR][:VLADDR]... >/proc/fs/afs/cells
echo add grand.central.org 18.7.14.88:128.2.191.224 >/proc/fs/afs/cells
echo add grand.central.org 18.9.48.14:128.2.203.61:130.237.48.87 >/proc/fs/afs/cells
No other cell database operations are available at this time.
@ -233,7 +231,7 @@ insmod /tmp/kafs.o rootcell=cambridge.redhat.com:172.16.18.91
mount -t afs \%root.afs. /afs
mount -t afs \%cambridge.redhat.com:root.cell. /afs/cambridge.redhat.com/
echo add grand.central.org 18.7.14.88:128.2.191.224 > /proc/fs/afs/cells
echo add grand.central.org 18.9.48.14:128.2.203.61:130.237.48.87 > /proc/fs/afs/cells
mount -t afs "#grand.central.org:root.cell." /afs/grand.central.org/
mount -t afs "#grand.central.org:root.archive." /afs/grand.central.org/archive
mount -t afs "#grand.central.org:root.contrib." /afs/grand.central.org/contrib

15
Documentation/filesystems/proc.txt
View File

@ -1167,13 +1167,11 @@ CHAPTER 3: PER-PROCESS PARAMETERS
3.1 /proc/<pid>/oom_adj - Adjust the oom-killer score
------------------------------------------------------
This file can be used to adjust the score used to select which processes should
be killed in an out-of-memory situation. The oom_adj value is a characteristic
of the task's mm, so all threads that share an mm with pid will have the same
oom_adj value. A high value will increase the likelihood of this process being
killed by the oom-killer. Valid values are in the range -16 to +15 as
explained below and a special value of -17, which disables oom-killing
altogether for threads sharing pid's mm.
This file can be used to adjust the score used to select which processes
should be killed in an out-of-memory situation. Giving it a high score will
increase the likelihood of this process being killed by the oom-killer. Valid
values are in the range -16 to +15, plus the special value -17, which disables
oom-killing altogether for this process.
The process to be killed in an out-of-memory situation is selected among all others
based on its badness score. This value equals the original memory size of the process
@ -1187,9 +1185,6 @@ the parent's score if they do not share the same memory. Thus forking servers
are the prime candidates to be killed. Having only one 'hungry' child will make
parent less preferable than the child.
/proc/<pid>/oom_adj cannot be changed for kthreads since they are immune from
oom-killing already.
/proc/<pid>/oom_score shows process' current badness score.
The following heuristics are then applied:

378
Documentation/power/runtime_pm.txt Normal file
View File

@ -0,0 +1,378 @@
Run-time Power Management Framework for I/O Devices
(C) 2009 Rafael J. Wysocki <rjw@sisk.pl>, Novell Inc.
1. Introduction
Support for run-time power management (run-time PM) of I/O devices is provided
at the power management core (PM core) level by means of:
* The power management workqueue pm_wq in which bus types and device drivers can
put their PM-related work items. It is strongly recommended that pm_wq be
used for queuing all work items related to run-time PM, because this allows
them to be synchronized with system-wide power transitions (suspend to RAM,
hibernation and resume from system sleep states). pm_wq is declared in
include/linux/pm_runtime.h and defined in kernel/power/main.c.
* A number of run-time PM fields in the 'power' member of 'struct device' (which
is of the type 'struct dev_pm_info', defined in include/linux/pm.h) that can
be used for synchronizing run-time PM operations with one another.
* Three device run-time PM callbacks in 'struct dev_pm_ops' (defined in
include/linux/pm.h).
* A set of helper functions defined in drivers/base/power/runtime.c that can be
used for carrying out run-time PM operations in such a way that the
synchronization between them is taken care of by the PM core. Bus types and
device drivers are encouraged to use these functions.
The run-time PM callbacks present in 'struct dev_pm_ops', the device run-time PM
fields of 'struct dev_pm_info' and the core helper functions provided for
run-time PM are described below.
2. Device Run-time PM Callbacks
There are three device run-time PM callbacks defined in 'struct dev_pm_ops':
struct dev_pm_ops {
...
int (*runtime_suspend)(struct device *dev);
int (*runtime_resume)(struct device *dev);
void (*runtime_idle)(struct device *dev);
...
};
The ->runtime_suspend() callback is executed by the PM core for the bus type of
the device being suspended. The bus type's callback is then _entirely_
_responsible_ for handling the device as appropriate, which may, but need not
include executing the device driver's own ->runtime_suspend() callback (from the
PM core's point of view it is not necessary to implement a ->runtime_suspend()
callback in a device driver as long as the bus type's ->runtime_suspend() knows
what to do to handle the device).
* Once the bus type's ->runtime_suspend() callback has completed successfully
for given device, the PM core regards the device as suspended, which need
not mean that the device has been put into a low power state. It is
supposed to mean, however, that the device will not process data and will
not communicate with the CPU(s) and RAM until its bus type's
->runtime_resume() callback is executed for it. The run-time PM status of
a device after successful execution of its bus type's ->runtime_suspend()
callback is 'suspended'.
* If the bus type's ->runtime_suspend() callback returns -EBUSY or -EAGAIN,
the device's run-time PM status is supposed to be 'active', which means that
the device _must_ be fully operational afterwards.
* If the bus type's ->runtime_suspend() callback returns an error code
different from -EBUSY or -EAGAIN, the PM core regards this as a fatal
error and will refuse to run the helper functions described in Section 4
for the device, until the status of it is directly set either to 'active'
or to 'suspended' (the PM core provides special helper functions for this
purpose).
In particular, if the driver requires remote wakeup capability for proper
functioning and device_may_wakeup() returns 'false' for the device, then
->runtime_suspend() should return -EBUSY. On the other hand, if
device_may_wakeup() returns 'true' for the device and the device is put
into a low power state during the execution of its bus type's
->runtime_suspend(), it is expected that remote wake-up (i.e. hardware mechanism
allowing the device to request a change of its power state, such as PCI PME)
will be enabled for the device. Generally, remote wake-up should be enabled
for all input devices put into a low power state at run time.
The ->runtime_resume() callback is executed by the PM core for the bus type of
the device being woken up. The bus type's callback is then _entirely_
_responsible_ for handling the device as appropriate, which may, but need not
include executing the device driver's own ->runtime_resume() callback (from the
PM core's point of view it is not necessary to implement a ->runtime_resume()
callback in a device driver as long as the bus type's ->runtime_resume() knows
what to do to handle the device).
* Once the bus type's ->runtime_resume() callback has completed successfully,
the PM core regards the device as fully operational, which means that the
device _must_ be able to complete I/O operations as needed. The run-time
PM status of the device is then 'active'.
* If the bus type's ->runtime_resume() callback returns an error code, the PM
core regards this as a fatal error and will refuse to run the helper
functions described in Section 4 for the device, until its status is
directly set either to 'active' or to 'suspended' (the PM core provides
special helper functions for this purpose).
The ->runtime_idle() callback is executed by the PM core for the bus type of
given device whenever the device appears to be idle, which is indicated to the
PM core by two counters, the device's usage counter and the counter of 'active'
children of the device.
* If any of these counters is decreased using a helper function provided by
the PM core and it turns out to be equal to zero, the other counter is
checked. If that counter also is equal to zero, the PM core executes the
device bus type's ->runtime_idle() callback (with the device as an
argument).
The action performed by a bus type's ->runtime_idle() callback is totally
dependent on the bus type in question, but the expected and recommended action
is to check if the device can be suspended (i.e. if all of the conditions
necessary for suspending the device are satisfied) and to queue up a suspend
request for the device in that case.
The helper functions provided by the PM core, described in Section 4, guarantee
that the following constraints are met with respect to the bus type's run-time
PM callbacks:
(1) The callbacks are mutually exclusive (e.g. it is forbidden to execute
->runtime_suspend() in parallel with ->runtime_resume() or with another
instance of ->runtime_suspend() for the same device) with the exception that
->runtime_suspend() or ->runtime_resume() can be executed in parallel with
->runtime_idle() (although ->runtime_idle() will not be started while any
of the other callbacks is being executed for the same device).
(2) ->runtime_idle() and ->runtime_suspend() can only be executed for 'active'
devices (i.e. the PM core will only execute ->runtime_idle() or
->runtime_suspend() for the devices the run-time PM status of which is
'active').
(3) ->runtime_idle() and ->runtime_suspend() can only be executed for a device
the usage counter of which is equal to zero _and_ either the counter of
'active' children of which is equal to zero, or the 'power.ignore_children'
flag of which is set.
(4) ->runtime_resume() can only be executed for 'suspended' devices (i.e. the
PM core will only execute ->runtime_resume() for the devices the run-time
PM status of which is 'suspended').
Additionally, the helper functions provided by the PM core obey the following
rules:
* If ->runtime_suspend() is about to be executed or there's a pending request
to execute it, ->runtime_idle() will not be executed for the same device.
* A request to execute or to schedule the execution of ->runtime_suspend()
will cancel any pending requests to execute ->runtime_idle() for the same
device.
* If ->runtime_resume() is about to be executed or there's a pending request
to execute it, the other callbacks will not be executed for the same device.
* A request to execute ->runtime_resume() will cancel any pending or
scheduled requests to execute the other callbacks for the same device.
3. Run-time PM Device Fields
The following device run-time PM fields are present in 'struct dev_pm_info', as
defined in include/linux/pm.h:
struct timer_list suspend_timer;
- timer used for scheduling (delayed) suspend request
unsigned long timer_expires;
- timer expiration time, in jiffies (if this is different from zero, the
timer is running and will expire at that time, otherwise the timer is not
running)
struct work_struct work;
- work structure used for queuing up requests (i.e. work items in pm_wq)
wait_queue_head_t wait_queue;
- wait queue used if any of the helper functions needs to wait for another
one to complete
spinlock_t lock;
- lock used for synchronisation
atomic_t usage_count;
- the usage counter of the device
atomic_t child_count;
- the count of 'active' children of the device
unsigned int ignore_children;
- if set, the value of child_count is ignored (but still updated)
unsigned int disable_depth;
- used for disabling the helper funcions (they work normally if this is
equal to zero); the initial value of it is 1 (i.e. run-time PM is
initially disabled for all devices)
unsigned int runtime_error;
- if set, there was a fatal error (one of the callbacks returned error code
as described in Section 2), so the helper funtions will not work until
this flag is cleared; this is the error code returned by the failing
callback
unsigned int idle_notification;
- if set, ->runtime_idle() is being executed
unsigned int request_pending;
- if set, there's a pending request (i.e. a work item queued up into pm_wq)
enum rpm_request request;
- type of request that's pending (valid if request_pending is set)
unsigned int deferred_resume;
- set if ->runtime_resume() is about to be run while ->runtime_suspend() is
being executed for that device and it is not practical to wait for the
suspend to complete; means "start a resume as soon as you've suspended"
enum rpm_status runtime_status;
- the run-time PM status of the device; this field's initial value is
RPM_SUSPENDED, which means that each device is initially regarded by the
PM core as 'suspended', regardless of its real hardware status
All of the above fields are members of the 'power' member of 'struct device'.
4. Run-time PM Device Helper Functions
The following run-time PM helper functions are defined in
drivers/base/power/runtime.c and include/linux/pm_runtime.h:
void pm_runtime_init(struct device *dev);
- initialize the device run-time PM fields in 'struct dev_pm_info'
void pm_runtime_remove(struct device *dev);
- make sure that the run-time PM of the device will be disabled after
removing the device from device hierarchy
int pm_runtime_idle(struct device *dev);
- execute ->runtime_idle() for the device's bus type; returns 0 on success
or error code on failure, where -EINPROGRESS means that ->runtime_idle()
is already being executed
int pm_runtime_suspend(struct device *dev);
- execute ->runtime_suspend() for the device's bus type; returns 0 on
success, 1 if the device's run-time PM status was already 'suspended', or
error code on failure, where -EAGAIN or -EBUSY means it is safe to attempt
to suspend the device again in future
int pm_runtime_resume(struct device *dev);
- execute ->runtime_resume() for the device's bus type; returns 0 on
success, 1 if the device's run-time PM status was already 'active' or
error code on failure, where -EAGAIN means it may be safe to attempt to
resume the device again in future, but 'power.runtime_error' should be
checked additionally
int pm_request_idle(struct device *dev);
- submit a request to execute ->runtime_idle() for the device's bus type
(the request is represented by a work item in pm_wq); returns 0 on success
or error code if the request has not been queued up
int pm_schedule_suspend(struct device *dev, unsigned int delay);
- schedule the execution of ->runtime_suspend() for the device's bus type
in future, where 'delay' is the time to wait before queuing up a suspend
work item in pm_wq, in milliseconds (if 'delay' is zero, the work item is
queued up immediately); returns 0 on success, 1 if the device's PM
run-time status was already 'suspended', or error code if the request
hasn't been scheduled (or queued up if 'delay' is 0); if the execution of
->runtime_suspend() is already scheduled and not yet expired, the new
value of 'delay' will be used as the time to wait
int pm_request_resume(struct device *dev);
- submit a request to execute ->runtime_resume() for the device's bus type
(the request is represented by a work item in pm_wq); returns 0 on
success, 1 if the device's run-time PM status was already 'active', or
error code if the request hasn't been queued up
void pm_runtime_get_noresume(struct device *dev);
- increment the device's usage counter
int pm_runtime_get(struct device *dev);
- increment the device's usage counter, run pm_request_resume(dev) and
return its result
int pm_runtime_get_sync(struct device *dev);
- increment the device's usage counter, run pm_runtime_resume(dev) and
return its result
void pm_runtime_put_noidle(struct device *dev);
- decrement the device's usage counter
int pm_runtime_put(struct device *dev);
- decrement the device's usage counter, run pm_request_idle(dev) and return
its result
int pm_runtime_put_sync(struct device *dev);
- decrement the device's usage counter, run pm_runtime_idle(dev) and return
its result
void pm_runtime_enable(struct device *dev);
- enable the run-time PM helper functions to run the device bus type's
run-time PM callbacks described in Section 2
int pm_runtime_disable(struct device *dev);
- prevent the run-time PM helper functions from running the device bus
type's run-time PM callbacks, make sure that all of the pending run-time
PM operations on the device are either completed or canceled; returns
1 if there was a resume request pending and it was necessary to execute
->runtime_resume() for the device's bus type to satisfy that request,
otherwise 0 is returned
void pm_suspend_ignore_children(struct device *dev, bool enable);
- set/unset the power.ignore_children flag of the device
int pm_runtime_set_active(struct device *dev);
- clear the device's 'power.runtime_error' flag, set the device's run-time
PM status to 'active' and update its parent's counter of 'active'
children as appropriate (it is only valid to use this function if
'power.runtime_error' is set or 'power.disable_depth' is greater than
zero); it will fail and return error code if the device has a parent
which is not active and the 'power.ignore_children' flag of which is unset
void pm_runtime_set_suspended(struct device *dev);
- clear the device's 'power.runtime_error' flag, set the device's run-time
PM status to 'suspended' and update its parent's counter of 'active'
children as appropriate (it is only valid to use this function if
'power.runtime_error' is set or 'power.disable_depth' is greater than
zero)
It is safe to execute the following helper functions from interrupt context:
pm_request_idle()
pm_schedule_suspend()
pm_request_resume()
pm_runtime_get_noresume()
pm_runtime_get()
pm_runtime_put_noidle()
pm_runtime_put()
pm_suspend_ignore_children()
pm_runtime_set_active()
pm_runtime_set_suspended()
pm_runtime_enable()
5. Run-time PM Initialization, Device Probing and Removal
Initially, the run-time PM is disabled for all devices, which means that the
majority of the run-time PM helper funtions described in Section 4 will return
-EAGAIN until pm_runtime_enable() is called for the device.
In addition to that, the initial run-time PM status of all devices is
'suspended', but it need not reflect the actual physical state of the device.
Thus, if the device is initially active (i.e. it is able to process I/O), its
run-time PM status must be changed to 'active', with the help of
pm_runtime_set_active(), before pm_runtime_enable() is called for the device.
However, if the device has a parent and the parent's run-time PM is enabled,
calling pm_runtime_set_active() for the device will affect the parent, unless
the parent's 'power.ignore_children' flag is set. Namely, in that case the
parent won't be able to suspend at run time, using the PM core's helper
functions, as long as the child's status is 'active', even if the child's
run-time PM is still disabled (i.e. pm_runtime_enable() hasn't been called for
the child yet or pm_runtime_disable() has been called for it). For this reason,
once pm_runtime_set_active() has been called for the device, pm_runtime_enable()
should be called for it too as soon as reasonably possible or its run-time PM
status should be changed back to 'suspended' with the help of
pm_runtime_set_suspended().
If the default initial run-time PM status of the device (i.e. 'suspended')
reflects the actual state of the device, its bus type's or its driver's
->probe() callback will likely need to wake it up using one of the PM core's
helper functions described in Section 4. In that case, pm_runtime_resume()
should be used. Of course, for this purpose the device's run-time PM has to be
enabled earlier by calling pm_runtime_enable().
If the device bus type's or driver's ->probe() or ->remove() callback runs
pm_runtime_suspend() or pm_runtime_idle() or their asynchronous counterparts,
they will fail returning -EAGAIN, because the device's usage counter is
incremented by the core before executing ->probe() and ->remove(). Still, it
may be desirable to suspend the device as soon as ->probe() or ->remove() has
finished, so the PM core uses pm_runtime_idle_sync() to invoke the device bus
type's ->runtime_idle() callback at that time.

2
Documentation/video4linux/CARDLIST.em28xx
View File

@ -1,5 +1,5 @@
0 -> Unknown EM2800 video grabber (em2800) [eb1a:2800]
1 -> Unknown EM2750/28xx video grabber (em2820/em2840) [eb1a:2820,eb1a:2821,eb1a:2860,eb1a:2861,eb1a:2870,eb1a:2881,eb1a:2883]
1 -> Unknown EM2750/28xx video grabber (em2820/em2840) [eb1a:2710,eb1a:2820,eb1a:2821,eb1a:2860,eb1a:2861,eb1a:2870,eb1a:2881,eb1a:2883]
2 -> Terratec Cinergy 250 USB (em2820/em2840) [0ccd:0036]
3 -> Pinnacle PCTV USB 2 (em2820/em2840) [2304:0208]
4 -> Hauppauge WinTV USB 2 (em2820/em2840) [2040:4200,2040:4201]

4
Documentation/video4linux/CARDLIST.saa7134
View File

@ -153,8 +153,8 @@
152 -> Asus Tiger Rev:1.00 [1043:4857]
153 -> Kworld Plus TV Analog Lite PCI [17de:7128]
154 -> Avermedia AVerTV GO 007 FM Plus [1461:f31d]
155 -> Hauppauge WinTV-HVR1120 ATSC/QAM-Hybrid [0070:6706,0070:6708]
156 -> Hauppauge WinTV-HVR1110r3 DVB-T/Hybrid [0070:6707,0070:6709,0070:670a]
155 -> Hauppauge WinTV-HVR1150 ATSC/QAM-Hybrid [0070:6706,0070:6708]
156 -> Hauppauge WinTV-HVR1120 DVB-T/Hybrid [0070:6707,0070:6709,0070:670a]
157 -> Avermedia AVerTV Studio 507UA [1461:a11b]
158 -> AVerMedia Cardbus TV/Radio (E501R) [1461:b7e9]
159 -> Beholder BeholdTV 505 RDS [0000:505B]

18
MAINTAINERS
View File

@ -904,7 +904,7 @@ F: drivers/input/misc/ati_remote2.c
ATLX ETHERNET DRIVERS
M: Jay Cliburn <jcliburn@gmail.com>
M: Chris Snook <csnook@redhat.com>
M: Chris Snook <chris.snook@gmail.com>
M: Jie Yang <jie.yang@atheros.com>
L: atl1-devel@lists.sourceforge.net
W: http://sourceforge.net/projects/atl1
@ -2238,6 +2238,14 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-2.6.git
S: Maintained
F: drivers/media/video/gspca/pac207.c
GSPCA SN9C20X SUBDRIVER
P: Brian Johnson
M: brijohn@gmail.com
L: linux-media@vger.kernel.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-2.6.git
S: Maintained
F: drivers/media/video/gspca/sn9c20x.c
GSPCA T613 SUBDRIVER
M: Leandro Costantino <lcostantino@gmail.com>
L: linux-media@vger.kernel.org
@ -3421,6 +3429,7 @@ F: drivers/mfd/
MULTIMEDIA CARD (MMC), SECURE DIGITAL (SD) AND SDIO SUBSYSTEM
S: Orphan
L: linux-mmc@vger.kernel.org
F: drivers/mmc/
F: include/linux/mmc/
@ -3555,6 +3564,9 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6.git
S: Maintained
F: net/
F: include/net/
F: include/linux/in.h
F: include/linux/net.h
F: include/linux/netdevice.h
NETWORKING [IPv4/IPv6]
M: "David S. Miller" <davem@davemloft.net>
@ -3590,6 +3602,8 @@ W: http://www.linuxfoundation.org/en/Net
T: git git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6.git
S: Odd Fixes
F: drivers/net/
F: include/linux/if_*
F: include/linux/*device.h
NETXEN (1/10) GbE SUPPORT
M: Dhananjay Phadke <dhananjay@netxen.com>
@ -3796,7 +3810,7 @@ W: http://open-osd.org
T: git git://git.open-osd.org/open-osd.git
S: Maintained
F: drivers/scsi/osd/
F: drivers/include/scsi/osd_*
F: include/scsi/osd_*
F: fs/exofs/
P54 WIRELESS DRIVER

2
Makefile
View File

@ -1,7 +1,7 @@
VERSION = 2
PATCHLEVEL = 6
SUBLEVEL = 31
EXTRAVERSION = -rc6
EXTRAVERSION = -rc7
NAME = Man-Eating Seals of Antiquity
# *DOCUMENTATION*

5
REPORTING-BUGS
View File

@ -15,7 +15,10 @@ worry too much about getting the wrong person. If you are unsure send it
to the person responsible for the code relevant to what you were doing.
If it occurs repeatably try and describe how to recreate it. That is
worth even more than the oops itself. The list of maintainers and
mailing lists is in the MAINTAINERS file in this directory.
mailing lists is in the MAINTAINERS file in this directory. If you
know the file name that causes the problem you can use the following
command in this directory to find some of the maintainers of that file:
perl scripts/get_maintainer.pl -f <filename>
If it is a security bug, please copy the Security Contact listed
in the MAINTAINERS file. They can help coordinate bugfix and disclosure.

7
arch/arm/configs/rx51_defconfig
View File

@ -282,7 +282,7 @@ CONFIG_ALIGNMENT_TRAP=y
#
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="init=/sbin/preinit ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs rootflags=bulk_read,no_chk_data_crc rw console=ttyMTD,log console=tty0"
CONFIG_CMDLINE="init=/sbin/preinit ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs rootflags=bulk_read,no_chk_data_crc rw console=ttyMTD,log console=tty0 console=ttyS2,115200n8"
# CONFIG_XIP_KERNEL is not set
# CONFIG_KEXEC is not set
@ -1354,7 +1354,7 @@ CONFIG_USB_OTG_UTILS=y
# CONFIG_USB_GPIO_VBUS is not set
# CONFIG_ISP1301_OMAP is not set
CONFIG_TWL4030_USB=y
CONFIG_MMC=m
CONFIG_MMC=y
# CONFIG_MMC_DEBUG is not set
# CONFIG_MMC_UNSAFE_RESUME is not set
@ -1449,7 +1449,8 @@ CONFIG_RTC_DRV_TWL4030=m
# on-CPU RTC drivers
#
# CONFIG_DMADEVICES is not set
# CONFIG_REGULATOR is not set
CONFIG_REGULATOR=y
CONFIG_REGULATOR_TWL4030=y
# CONFIG_UIO is not set
# CONFIG_STAGING is not set

3
arch/arm/include/asm/device.h
View File

@ -12,4 +12,7 @@ struct dev_archdata {
#endif
};
struct pdev_archdata {
};
#endif

3
arch/arm/include/asm/setup.h
View File

@ -201,7 +201,8 @@ static struct tagtable __tagtable_##fn __tag = { tag, fn }
struct membank {
unsigned long start;
unsigned long size;
int node;
unsigned short node;
unsigned short highmem;
};
struct meminfo {

2
arch/arm/mach-ixp4xx/include/mach/io.h
View File

@ -17,7 +17,7 @@
#include <mach/hardware.h>
#define IO_SPACE_LIMIT 0xffff0000
#define IO_SPACE_LIMIT 0x0000ffff
extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);

2
arch/arm/mach-mx3/mx31moboard-devboard.c
View File

@ -63,7 +63,7 @@ static struct imxuart_platform_data uart_pdata = {
static int devboard_sdhc2_get_ro(struct device *dev)
{
return gpio_get_value(SDHC2_WP);
return !gpio_get_value(SDHC2_WP);
}
static int devboard_sdhc2_init(struct device *dev, irq_handler_t detect_irq,

2
arch/arm/mach-mx3/mx31moboard-marxbot.c
View File

@ -67,7 +67,7 @@ static unsigned int marxbot_pins[] = {
static int marxbot_sdhc2_get_ro(struct device *dev)
{
return gpio_get_value(SDHC2_WP);
return !gpio_get_value(SDHC2_WP);
}
static int marxbot_sdhc2_init(struct device *dev, irq_handler_t detect_irq,

2
arch/arm/mach-mx3/mx31moboard.c
View File

@ -94,7 +94,7 @@ static struct imxi2c_platform_data moboard_i2c1_pdata = {
static int moboard_sdhc1_get_ro(struct device *dev)
{
return gpio_get_value(SDHC1_WP);
return !gpio_get_value(SDHC1_WP);
}
static int moboard_sdhc1_init(struct device *dev, irq_handler_t detect_irq,

9
arch/arm/mach-mx3/pcm037_eet.c
View File

@ -24,15 +24,6 @@
#include "devices.h"
static unsigned int pcm037_eet_pins[] = {
/* SPI #1 */
MX31_PIN_CSPI1_MISO__MISO,
MX31_PIN_CSPI1_MOSI__MOSI,
MX31_PIN_CSPI1_SCLK__SCLK,
MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
MX31_PIN_CSPI1_SS0__SS0,
MX31_PIN_CSPI1_SS1__SS1,
MX31_PIN_CSPI1_SS2__SS2,
/* Reserve and hardwire GPIO 57 high - S6E63D6 chipselect */
IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_GPIO),
/* GPIO keys */

2
arch/arm/mach-omap2/board-2430sdp.c
View File

@ -141,7 +141,7 @@ static inline void board_smc91x_init(void)
static void __init omap_2430sdp_init_irq(void)
{
omap2_init_common_hw(NULL);
omap2_init_common_hw(NULL, NULL);
omap_init_irq();
omap_gpio_init();
}

2
arch/arm/mach-omap2/board-3430sdp.c
View File

@ -169,7 +169,7 @@ static struct platform_device *sdp3430_devices[] __initdata = {
static void __init omap_3430sdp_init_irq(void)
{
omap2_init_common_hw(hyb18m512160af6_sdrc_params);
omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL);
omap_init_irq();
omap_gpio_init();
}

2
arch/arm/mach-omap2/board-4430sdp.c
View File

@ -59,7 +59,7 @@ static void __init gic_init_irq(void)
static void __init omap_4430sdp_init_irq(void)
{
omap2_init_common_hw(NULL);
omap2_init_common_hw(NULL, NULL);
#ifdef CONFIG_OMAP_32K_TIMER
omap2_gp_clockevent_set_gptimer(1);
#endif

2
arch/arm/mach-omap2/board-apollon.c
View File

@ -250,7 +250,7 @@ out:
static void __init omap_apollon_init_irq(void)
{
omap2_init_common_hw(NULL);
omap2_init_common_hw(NULL, NULL);
omap_init_irq();
omap_gpio_init();
apollon_init_smc91x();

2
arch/arm/mach-omap2/board-generic.c
View File

@ -33,7 +33,7 @@
static void __init omap_generic_init_irq(void)
{
omap2_init_common_hw(NULL);
omap2_init_common_hw(NULL, NULL);
omap_init_irq();
}

2
arch/arm/mach-omap2/board-h4.c
View File

@ -270,7 +270,7 @@ static void __init h4_init_flash(void)
static void __init omap_h4_init_irq(void)
{
omap2_init_common_hw(NULL);
omap2_init_common_hw(NULL, NULL);
omap_init_irq();
omap_gpio_init();
h4_init_flash();

2
arch/arm/mach-omap2/board-ldp.c
View File

@ -270,7 +270,7 @@ static inline void __init ldp_init_smsc911x(void)
static void __init omap_ldp_init_irq(void)
{
omap2_init_common_hw(NULL);
omap2_init_common_hw(NULL, NULL);
omap_init_irq();
omap_gpio_init();
ldp_init_smsc911x();

7
arch/arm/mach-omap2/board-omap3beagle.c
View File

@ -282,7 +282,8 @@ static int __init omap3_beagle_i2c_init(void)
static void __init omap3_beagle_init_irq(void)
{
omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params);
omap_init_irq();
#ifdef CONFIG_OMAP_32K_TIMER
omap2_gp_clockevent_set_gptimer(12);
@ -408,6 +409,10 @@ static void __init omap3_beagle_init(void)
usb_musb_init();
omap3beagle_flash_init();
/* Ensure SDRC pins are mux'd for self-refresh */
omap_cfg_reg(H16_34XX_SDRC_CKE0);
omap_cfg_reg(H17_34XX_SDRC_CKE1);
}
static void __init omap3_beagle_map_io(void)

2
arch/arm/mach-omap2/board-omap3evm.c
View File

@ -280,7 +280,7 @@ struct spi_board_info omap3evm_spi_board_info[] = {
static void __init omap3_evm_init_irq(void)
{
omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL);
omap_init_irq();
omap_gpio_init();
omap3evm_init_smc911x();

8
arch/arm/mach-omap2/board-omap3pandora.c
View File

@ -40,6 +40,7 @@
#include <mach/mcspi.h>
#include <mach/usb.h>
#include <mach/keypad.h>
#include <mach/mux.h>
#include "sdram-micron-mt46h32m32lf-6.h"
#include "mmc-twl4030.h"
@ -310,7 +311,8 @@ static int __init omap3pandora_i2c_init(void)
static void __init omap3pandora_init_irq(void)
{
omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params);
omap_init_irq();
omap_gpio_init();
}
@ -397,6 +399,10 @@ static void __init omap3pandora_init(void)
omap3pandora_ads7846_init();
pandora_keys_gpio_init();
usb_musb_init();
/* Ensure SDRC pins are mux'd for self-refresh */
omap_cfg_reg(H16_34XX_SDRC_CKE0);
omap_cfg_reg(H17_34XX_SDRC_CKE1);
}
static void __init omap3pandora_map_io(void)

11
arch/arm/mach-omap2/board-overo.c
View File

@ -44,6 +44,7 @@
#include <mach/gpmc.h>
#include <mach/hardware.h>
#include <mach/nand.h>
#include <mach/mux.h>
#include <mach/usb.h>
#include "sdram-micron-mt46h32m32lf-6.h"
@ -51,6 +52,7 @@
#define OVERO_GPIO_BT_XGATE 15
#define OVERO_GPIO_W2W_NRESET 16
#define OVERO_GPIO_PENDOWN 114
#define OVERO_GPIO_BT_NRESET 164
#define OVERO_GPIO_USBH_CPEN 168
#define OVERO_GPIO_USBH_NRESET 183
@ -146,7 +148,7 @@ static struct platform_device overo_smsc911x_device = {
.name = "smsc911x",
.id = -1,
.num_resources = ARRAY_SIZE(overo_smsc911x_resources),
.resource = &overo_smsc911x_resources,
.resource = overo_smsc911x_resources,
.dev = {
.platform_data = &overo_smsc911x_config,
},
@ -360,7 +362,8 @@ static int __init overo_i2c_init(void)
static void __init overo_init_irq(void)
{
omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params);
omap_init_irq();
omap_gpio_init();
}
@ -395,6 +398,10 @@ static void __init overo_init(void)
overo_ads7846_init();
overo_init_smsc911x();
/* Ensure SDRC pins are mux'd for self-refresh */
omap_cfg_reg(H16_34XX_SDRC_CKE0);
omap_cfg_reg(H17_34XX_SDRC_CKE1);
if ((gpio_request(OVERO_GPIO_W2W_NRESET,
"OVERO_GPIO_W2W_NRESET") == 0) &&
(gpio_direction_output(OVERO_GPIO_W2W_NRESET, 1) == 0)) {

5
arch/arm/mach-omap2/board-rx51-peripherals.c
View File

@ -278,6 +278,10 @@ static struct twl4030_gpio_platform_data rx51_gpio_data = {
.setup = rx51_twlgpio_setup,
};
static struct twl4030_usb_data rx51_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
};
static struct twl4030_platform_data rx51_twldata = {
.irq_base = TWL4030_IRQ_BASE,
.irq_end = TWL4030_IRQ_END,
@ -286,6 +290,7 @@ static struct twl4030_platform_data rx51_twldata = {
.gpio = &rx51_gpio_data,
.keypad = &rx51_kp_data,
.madc = &rx51_madc_data,
.usb = &rx51_usb_data,
.vaux1 = &rx51_vaux1,
.vaux2 = &rx51_vaux2,

6
arch/arm/mach-omap2/board-rx51.c
View File

@ -61,7 +61,7 @@ static struct omap_board_config_kernel rx51_config[] = {
static void __init rx51_init_irq(void)
{
omap2_init_common_hw(NULL);
omap2_init_common_hw(NULL, NULL);
omap_init_irq();
omap_gpio_init();
}
@ -75,6 +75,10 @@ static void __init rx51_init(void)
omap_serial_init();
usb_musb_init();
rx51_peripherals_init();
/* Ensure SDRC pins are mux'd for self-refresh */
omap_cfg_reg(H16_34XX_SDRC_CKE0);
omap_cfg_reg(H17_34XX_SDRC_CKE1);
}
static void __init rx51_map_io(void)

2
arch/arm/mach-omap2/board-zoom2.c
View File

@ -25,7 +25,7 @@
static void __init omap_zoom2_init_irq(void)
{
omap2_init_common_hw(NULL);
omap2_init_common_hw(NULL, NULL);
omap_init_irq();
omap_gpio_init();
}

164
arch/arm/mach-omap2/clock.c
View File

@ -27,6 +27,7 @@
#include <mach/clock.h>
#include <mach/clockdomain.h>
#include <mach/cpu.h>
#include <mach/prcm.h>
#include <asm/div64.h>
#include <mach/sdrc.h>
@ -38,8 +39,6 @@
#include "cm-regbits-24xx.h"
#include "cm-regbits-34xx.h"
#define MAX_CLOCK_ENABLE_WAIT 100000
/* DPLL rate rounding: minimum DPLL multiplier, divider values */
#define DPLL_MIN_MULTIPLIER 1
#define DPLL_MIN_DIVIDER 1
@ -274,83 +273,97 @@ unsigned long omap2_fixed_divisor_recalc(struct clk *clk)
}
/**
* omap2_wait_clock_ready - wait for clock to enable
* @reg: physical address of clock IDLEST register
* @mask: value to mask against to determine if the clock is active
* @name: name of the clock (for printk)
* omap2_clk_dflt_find_companion - find companion clock to @clk
* @clk: struct clk * to find the companion clock of
* @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
* @other_bit: u8 ** to return the companion clock bit shift in
*
* Returns 1 if the clock enabled in time, or 0 if it failed to enable
* in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
*/
int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
{
int i = 0;
int ena = 0;
/*
* 24xx uses 0 to indicate not ready, and 1 to indicate ready.
* 34xx reverses this, just to keep us on our toes
*/
if (cpu_mask & (RATE_IN_242X | RATE_IN_243X))
ena = mask;
else if (cpu_mask & RATE_IN_343X)
ena = 0;
/* Wait for lock */
while (((__raw_readl(reg) & mask) != ena) &&
(i++ < MAX_CLOCK_ENABLE_WAIT)) {
udelay(1);
}
if (i <= MAX_CLOCK_ENABLE_WAIT)
pr_debug("Clock %s stable after %d loops\n", name, i);
else
printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
name, MAX_CLOCK_ENABLE_WAIT);
return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
};
/*
* Note: We don't need special code here for INVERT_ENABLE
* for the time being since INVERT_ENABLE only applies to clocks enabled by
* Note: We don't need special code here for INVERT_ENABLE for the
* time being since INVERT_ENABLE only applies to clocks enabled by
* CM_CLKEN_PLL
*
* Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's
* just a matter of XORing the bits.
*
* Some clocks don't have companion clocks. For example, modules with
* only an interface clock (such as MAILBOXES) don't have a companion
* clock. Right now, this code relies on the hardware exporting a bit
* in the correct companion register that indicates that the
* nonexistent 'companion clock' is active. Future patches will
* associate this type of code with per-module data structures to
* avoid this issue, and remove the casts. No return value.
*/
static void omap2_clk_wait_ready(struct clk *clk)
void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
u8 *other_bit)
{
void __iomem *reg, *other_reg, *st_reg;
u32 bit;
/*
* REVISIT: This code is pretty ugly. It would be nice to generalize
* it and pull it into struct clk itself somehow.
*/
reg = clk->enable_reg;
u32 r;
/*
* Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes
* it's just a matter of XORing the bits.
*/
other_reg = (void __iomem *)((u32)reg ^ (CM_FCLKEN ^ CM_ICLKEN));
r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN));
/* Check if both functional and interface clocks
* are running. */
bit = 1 << clk->enable_bit;
if (!(__raw_readl(other_reg) & bit))
return;
st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
omap2_wait_clock_ready(st_reg, bit, clk->name);
*other_reg = (__force void __iomem *)r;
*other_bit = clk->enable_bit;
}
static int omap2_dflt_clk_enable(struct clk *clk)
/**
* omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk
* @clk: struct clk * to find IDLEST info for
* @idlest_reg: void __iomem ** to return the CM_IDLEST va in
* @idlest_bit: u8 ** to return the CM_IDLEST bit shift in
*
* Return the CM_IDLEST register address and bit shift corresponding
* to the module that "owns" this clock. This default code assumes
* that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that
* the IDLEST register address ID corresponds to the CM_*CLKEN
* register address ID (e.g., that CM_FCLKEN2 corresponds to
* CM_IDLEST2). This is not true for all modules. No return value.
*/
void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
u8 *idlest_bit)
{
u32 r;
r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
*idlest_reg = (__force void __iomem *)r;
*idlest_bit = clk->enable_bit;
}
/**
* omap2_module_wait_ready - wait for an OMAP module to leave IDLE
* @clk: struct clk * belonging to the module
*
* If the necessary clocks for the OMAP hardware IP block that
* corresponds to clock @clk are enabled, then wait for the module to
* indicate readiness (i.e., to leave IDLE). This code does not
* belong in the clock code and will be moved in the medium term to
* module-dependent code. No return value.
*/
static void omap2_module_wait_ready(struct clk *clk)
{
void __iomem *companion_reg, *idlest_reg;
u8 other_bit, idlest_bit;
/* Not all modules have multiple clocks that their IDLEST depends on */
if (clk->ops->find_companion) {
clk->ops->find_companion(clk, &companion_reg, &other_bit);
if (!(__raw_readl(companion_reg) & (1 << other_bit)))
return;
}
clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit);
omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), clk->name);
}
int omap2_dflt_clk_enable(struct clk *clk)
{
u32 v;
if (unlikely(clk->enable_reg == NULL)) {
printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
pr_err("clock.c: Enable for %s without enable code\n",
clk->name);
return 0; /* REVISIT: -EINVAL */
}
@ -363,26 +376,13 @@ static int omap2_dflt_clk_enable(struct clk *clk)
__raw_writel(v, clk->enable_reg);
v = __raw_readl(clk->enable_reg); /* OCP barrier */
if (clk->ops->find_idlest)
omap2_module_wait_ready(clk);
return 0;
}
static int omap2_dflt_clk_enable_wait(struct clk *clk)
{
int ret;
if (!clk->enable_reg) {
printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
clk->name);
return 0; /* REVISIT: -EINVAL */
}
ret = omap2_dflt_clk_enable(clk);
if (ret == 0)
omap2_clk_wait_ready(clk);
return ret;
}
static void omap2_dflt_clk_disable(struct clk *clk)
void omap2_dflt_clk_disable(struct clk *clk)
{
u32 v;
@ -406,8 +406,10 @@ static void omap2_dflt_clk_disable(struct clk *clk)
}
const struct clkops clkops_omap2_dflt_wait = {
.enable = omap2_dflt_clk_enable_wait,
.enable = omap2_dflt_clk_enable,
.disable = omap2_dflt_clk_disable,
.find_companion = omap2_clk_dflt_find_companion,
.find_idlest = omap2_clk_dflt_find_idlest,
};
const struct clkops clkops_omap2_dflt = {

6
arch/arm/mach-omap2/clock.h
View File

@ -65,6 +65,12 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
u32 omap2_get_dpll_rate(struct clk *clk);
int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
void omap2_clk_prepare_for_reboot(void);
int omap2_dflt_clk_enable(struct clk *clk);
void omap2_dflt_clk_disable(struct clk *clk);
void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
u8 *other_bit);
void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
u8 *idlest_bit);
extern const struct clkops clkops_omap2_dflt_wait;
extern const struct clkops clkops_omap2_dflt;

37
arch/arm/mach-omap2/clock24xx.c
View File

@ -30,6 +30,7 @@
#include <mach/clock.h>
#include <mach/sram.h>
#include <mach/prcm.h>
#include <asm/div64.h>
#include <asm/clkdev.h>
@ -43,6 +44,18 @@
static const struct clkops clkops_oscck;
static const struct clkops clkops_fixed;
static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
void __iomem **idlest_reg,
u8 *idlest_bit);
/* 2430 I2CHS has non-standard IDLEST register */
static const struct clkops clkops_omap2430_i2chs_wait = {
.enable = omap2_dflt_clk_enable,
.disable = omap2_dflt_clk_disable,
.find_idlest = omap2430_clk_i2chs_find_idlest,
.find_companion = omap2_clk_dflt_find_companion,
};
#include "clock24xx.h"
struct omap_clk {
@ -239,6 +252,26 @@ static void __iomem *prcm_clksrc_ctrl;
* Omap24xx specific clock functions
*-------------------------------------------------------------------------*/
/**
* omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS
* @clk: struct clk * being enabled
* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
*
* OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the
* CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE. This custom function
* passes back the correct CM_IDLEST register address for I2CHS
* modules. No return value.
*/
static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
void __iomem **idlest_reg,
u8 *idlest_bit)
{
*idlest_reg = OMAP_CM_REGADDR(CORE_MOD, CM_IDLEST);
*idlest_bit = clk->enable_bit;
}
/**
* omap2xxx_clk_get_core_rate - return the CORE_CLK rate
* @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")
@ -325,8 +358,8 @@ static int omap2_clk_fixed_enable(struct clk *clk)
else if (clk == &apll54_ck)
cval = OMAP24XX_ST_54M_APLL;
omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
clk->name);
omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
clk->name);
/*
* REVISIT: Should we return an error code if omap2_wait_clock_ready()

4
arch/arm/mach-omap2/clock24xx.h
View File

@ -2337,7 +2337,7 @@ static struct clk i2c2_fck = {
static struct clk i2chs2_fck = {
.name = "i2c_fck",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2430_i2chs_wait,
.id = 2,
.parent = &func_96m_ck,
.clkdm_name = "core_l4_clkdm",
@ -2370,7 +2370,7 @@ static struct clk i2c1_fck = {
static struct clk i2chs1_fck = {
.name = "i2c_fck",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2430_i2chs_wait,
.id = 1,
.parent = &func_96m_ck,
.clkdm_name = "core_l4_clkdm",

153
arch/arm/mach-omap2/clock34xx.c
View File

@ -2,7 +2,7 @@
* OMAP3-specific clock framework functions
*
* Copyright (C) 2007-2008 Texas Instruments, Inc.
* Copyright (C) 2007-2008 Nokia Corporation
* Copyright (C) 2007-2009 Nokia Corporation
*
* Written by Paul Walmsley
* Testing and integration fixes by Jouni Högander
@ -41,6 +41,37 @@
static const struct clkops clkops_noncore_dpll_ops;
static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
void __iomem **idlest_reg,
u8 *idlest_bit);
static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
void __iomem **idlest_reg,
u8 *idlest_bit);
static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
void __iomem **idlest_reg,
u8 *idlest_bit);
static const struct clkops clkops_omap3430es2_ssi_wait = {
.enable = omap2_dflt_clk_enable,
.disable = omap2_dflt_clk_disable,
.find_idlest = omap3430es2_clk_ssi_find_idlest,
.find_companion = omap2_clk_dflt_find_companion,
};
static const struct clkops clkops_omap3430es2_hsotgusb_wait = {
.enable = omap2_dflt_clk_enable,
.disable = omap2_dflt_clk_disable,
.find_idlest = omap3430es2_clk_hsotgusb_find_idlest,
.find_companion = omap2_clk_dflt_find_companion,
};
static const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
.enable = omap2_dflt_clk_enable,
.disable = omap2_dflt_clk_disable,
.find_idlest = omap3430es2_clk_dss_usbhost_find_idlest,
.find_companion = omap2_clk_dflt_find_companion,
};
#include "clock34xx.h"
struct omap_clk {
@ -157,10 +188,13 @@ static struct omap_clk omap34xx_clks[] = {
CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X),
CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X),
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck, CK_343X),
CLK(NULL, "ssi_sst_fck", &ssi_sst_fck, CK_343X),
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2),
CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2),
CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X),
CLK("musb_hdrc", "ick", &hsotgusb_ick, CK_343X),
CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2),
CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X),
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X),
CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
@ -193,18 +227,21 @@ static struct omap_clk omap34xx_clks[] = {
CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X),
CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X),
CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X),
CLK(NULL, "ssi_ick", &ssi_ick, CK_343X),
CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1),
CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2),
CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X),
CLK(NULL, "aes1_ick", &aes1_ick, CK_343X),
CLK("omap_rng", "ick", &rng_ick, CK_343X),
CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
CLK(NULL, "des1_ick", &des1_ick, CK_343X),
CLK("omapfb", "dss1_fck", &dss1_alwon_fck, CK_343X),
CLK("omapfb", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
CLK("omapfb", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2),
CLK("omapfb", "tv_fck", &dss_tv_fck, CK_343X),
CLK("omapfb", "video_fck", &dss_96m_fck, CK_343X),
CLK("omapfb", "dss2_fck", &dss2_alwon_fck, CK_343X),
CLK("omapfb", "ick", &dss_ick, CK_343X),
CLK("omapfb", "ick", &dss_ick_3430es1, CK_3430ES1),
CLK("omapfb", "ick", &dss_ick_3430es2, CK_3430ES2),
CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
CLK(NULL, "cam_ick", &cam_ick, CK_343X),
CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X),
@ -300,6 +337,73 @@ static struct omap_clk omap34xx_clks[] = {
*/
#define SDRC_MPURATE_LOOPS 96
/**
* omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
* @clk: struct clk * being enabled
* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
*
* The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift
* from the CM_{I,F}CLKEN bit. Pass back the correct info via
* @idlest_reg and @idlest_bit. No return value.
*/
static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
void __iomem **idlest_reg,
u8 *idlest_bit)
{
u32 r;
r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
*idlest_reg = (__force void __iomem *)r;
*idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT;
}
/**
* omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
* @clk: struct clk * being enabled
* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
*
* Some OMAP modules on OMAP3 ES2+ chips have both initiator and
* target IDLEST bits. For our purposes, we are concerned with the
* target IDLEST bits, which exist at a different bit position than
* the *CLKEN bit position for these modules (DSS and USBHOST) (The
* default find_idlest code assumes that they are at the same
* position.) No return value.
*/
static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
void __iomem **idlest_reg,
u8 *idlest_bit)
{
u32 r;
r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
*idlest_reg = (__force void __iomem *)r;
/* USBHOST_IDLE has same shift */
*idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT;
}
/**
* omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
* @clk: struct clk * being enabled
* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
*
* The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different
* shift from the CM_{I,F}CLKEN bit. Pass back the correct info via
* @idlest_reg and @idlest_bit. No return value.
*/
static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
void __iomem **idlest_reg,
u8 *idlest_bit)
{
u32 r;
r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
*idlest_reg = (__force void __iomem *)r;
*idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT;
}
/**
* omap3_dpll_recalc - recalculate DPLL rate
* @clk: DPLL struct clk
@ -725,7 +829,9 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
u32 unlock_dll = 0;
u32 c;
unsigned long validrate, sdrcrate, mpurate;
struct omap_sdrc_params *sp;
struct omap_sdrc_params *sdrc_cs0;
struct omap_sdrc_params *sdrc_cs1;
int ret;
if (!clk || !rate)
return -EINVAL;
@ -743,8 +849,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
else
sdrcrate >>= ((clk->rate / rate) >> 1);
sp = omap2_sdrc_get_params(sdrcrate);
if (!sp)
ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
if (ret)
return -EINVAL;
if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
@ -765,12 +871,29 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
validrate);
pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
pr_debug("clock: SDRC CS0 timing params used:"
" RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
if (sdrc_cs1)
pr_debug("clock: SDRC CS1 timing params used: "
" RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
sp->actim_ctrlb, new_div, unlock_dll, c,
sp->mr, rate > clk->rate);
if (sdrc_cs1)
omap3_configure_core_dpll(
new_div, unlock_dll, c, rate > clk->rate,
sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
else
omap3_configure_core_dpll(
new_div, unlock_dll, c, rate > clk->rate,
sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
0, 0, 0, 0);
return 0;
}

85
arch/arm/mach-omap2/clock34xx.h
View File

@ -1568,7 +1568,7 @@ static const struct clksel ssi_ssr_clksel[] = {
{ .parent = NULL }
};
static struct clk ssi_ssr_fck = {
static struct clk ssi_ssr_fck_3430es1 = {
.name = "ssi_ssr_fck",
.ops = &clkops_omap2_dflt,
.init = &omap2_init_clksel_parent,
@ -1581,10 +1581,31 @@ static struct clk ssi_ssr_fck = {
.recalc = &omap2_clksel_recalc,
};
static struct clk ssi_sst_fck = {
static struct clk ssi_ssr_fck_3430es2 = {
.name = "ssi_ssr_fck",
.ops = &clkops_omap3430es2_ssi_wait,
.init = &omap2_init_clksel_parent,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_SSI_SHIFT,
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
.clksel = ssi_ssr_clksel,
.clkdm_name = "core_l4_clkdm",
.recalc = &omap2_clksel_recalc,
};
static struct clk ssi_sst_fck_3430es1 = {
.name = "ssi_sst_fck",
.ops = &clkops_null,
.parent = &ssi_ssr_fck,
.parent = &ssi_ssr_fck_3430es1,
.fixed_div = 2,
.recalc = &omap2_fixed_divisor_recalc,
};
static struct clk ssi_sst_fck_3430es2 = {
.name = "ssi_sst_fck",
.ops = &clkops_null,
.parent = &ssi_ssr_fck_3430es2,
.fixed_div = 2,
.recalc = &omap2_fixed_divisor_recalc,
};
@ -1606,9 +1627,19 @@ static struct clk core_l3_ick = {
.recalc = &followparent_recalc,
};
static struct clk hsotgusb_ick = {
static struct clk hsotgusb_ick_3430es1 = {
.name = "hsotgusb_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_dflt,
.parent = &core_l3_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
.clkdm_name = "core_l3_clkdm",
.recalc = &followparent_recalc,
};
static struct clk hsotgusb_ick_3430es2 = {
.name = "hsotgusb_ick",
.ops = &clkops_omap3430es2_hsotgusb_wait,
.parent = &core_l3_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
@ -1947,7 +1978,7 @@ static struct clk ssi_l4_ick = {
.recalc = &followparent_recalc,
};
static struct clk ssi_ick = {
static struct clk ssi_ick_3430es1 = {
.name = "ssi_ick",
.ops = &clkops_omap2_dflt,
.parent = &ssi_l4_ick,
@ -1957,6 +1988,16 @@ static struct clk ssi_ick = {
.recalc = &followparent_recalc,
};
static struct clk ssi_ick_3430es2 = {
.name = "ssi_ick",
.ops = &clkops_omap3430es2_ssi_wait,
.parent = &ssi_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_SSI_SHIFT,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
/* REVISIT: Technically the TRM claims that this is CORE_CLK based,
* but l4_ick makes more sense to me */
@ -2024,7 +2065,7 @@ static struct clk des1_ick = {
};
/* DSS */
static struct clk dss1_alwon_fck = {
static struct clk dss1_alwon_fck_3430es1 = {
.name = "dss1_alwon_fck",
.ops = &clkops_omap2_dflt,
.parent = &dpll4_m4x2_ck,
@ -2034,6 +2075,16 @@ static struct clk dss1_alwon_fck = {
.recalc = &followparent_recalc,
};
static struct clk dss1_alwon_fck_3430es2 = {
.name = "dss1_alwon_fck",
.ops = &clkops_omap3430es2_dss_usbhost_wait,
.parent = &dpll4_m4x2_ck,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_DSS1_SHIFT,
.clkdm_name = "dss_clkdm",
.recalc = &followparent_recalc,
};
static struct clk dss_tv_fck = {
.name = "dss_tv_fck",
.ops = &clkops_omap2_dflt,
@ -2067,7 +2118,7 @@ static struct clk dss2_alwon_fck = {
.recalc = &followparent_recalc,
};
static struct clk dss_ick = {
static struct clk dss_ick_3430es1 = {
/* Handles both L3 and L4 clocks */
.name = "dss_ick",
.ops = &clkops_omap2_dflt,
@ -2079,6 +2130,18 @@ static struct clk dss_ick = {
.recalc = &followparent_recalc,
};
static struct clk dss_ick_3430es2 = {
/* Handles both L3 and L4 clocks */
.name = "dss_ick",
.ops = &clkops_omap3430es2_dss_usbhost_wait,
.parent = &l4_ick,
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
.clkdm_name = "dss_clkdm",
.recalc = &followparent_recalc,
};
/* CAM */
static struct clk cam_mclk = {
@ -2118,7 +2181,7 @@ static struct clk csi2_96m_fck = {
static struct clk usbhost_120m_fck = {
.name = "usbhost_120m_fck",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap2_dflt,
.parent = &dpll5_m2_ck,
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
@ -2129,7 +2192,7 @@ static struct clk usbhost_120m_fck = {
static struct clk usbhost_48m_fck = {
.name = "usbhost_48m_fck",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap3430es2_dss_usbhost_wait,
.parent = &omap_48m_fck,
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
@ -2141,7 +2204,7 @@ static struct clk usbhost_48m_fck = {
static struct clk usbhost_ick = {
/* Handles both L3 and L4 clocks */
.name = "usbhost_ick",
.ops = &clkops_omap2_dflt_wait,
.ops = &clkops_omap3430es2_dss_usbhost_wait,
.parent = &l4_ick,
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),

6
arch/arm/mach-omap2/cm.h
View File

@ -29,9 +29,9 @@
* These registers appear once per CM module.
*/
#define OMAP3430_CM_REVISION OMAP_CM_REGADDR(OCP_MOD, 0x0000)
#define OMAP3430_CM_SYSCONFIG OMAP_CM_REGADDR(OCP_MOD, 0x0010)
#define OMAP3430_CM_POLCTRL OMAP_CM_REGADDR(OCP_MOD, 0x009c)
#define OMAP3430_CM_REVISION OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
#define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
#define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
#define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070
#define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)

5
arch/arm/mach-omap2/io.c
View File

@ -276,14 +276,15 @@ static int __init _omap2_init_reprogram_sdrc(void)
return v;
}
void __init omap2_init_common_hw(struct omap_sdrc_params *sp)
void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1)
{
omap2_mux_init();
#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
pwrdm_init(powerdomains_omap);
clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
omap2_clk_init();
omap2_sdrc_init(sp);
omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
_omap2_init_reprogram_sdrc();
#endif
gpmc_init();

6
arch/arm/mach-omap2/mmc-twl4030.c
View File

@ -119,6 +119,7 @@ static int twl_mmc_late_init(struct device *dev)
if (i != 0)
break;
ret = PTR_ERR(reg);
hsmmc[i].vcc = NULL;
goto err;
}
hsmmc[i].vcc = reg;
@ -165,8 +166,13 @@ done:
static void twl_mmc_cleanup(struct device *dev)
{
struct omap_mmc_platform_data *mmc = dev->platform_data;
int i;
gpio_free(mmc->slots[0].switch_pin);
for(i = 0; i < ARRAY_SIZE(hsmmc); i++) {
regulator_put(hsmmc[i].vcc);
regulator_put(hsmmc[i].vcc_aux);
}
}
#ifdef CONFIG_PM

6
arch/arm/mach-omap2/mux.c
View File

@ -486,6 +486,12 @@ MUX_CFG_34XX("H19_34XX_GPIO164_OUT", 0x19c,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
MUX_CFG_34XX("H16_34XX_SDRC_CKE0", 0x262,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
MUX_CFG_34XX("H17_34XX_SDRC_CKE1", 0x264,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
};
#define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins)

3
arch/arm/mach-omap2/pm.h
View File

@ -11,9 +11,6 @@
#ifndef __ARCH_ARM_MACH_OMAP2_PM_H
#define __ARCH_ARM_MACH_OMAP2_PM_H
extern int omap2_pm_init(void);
extern int omap3_pm_init(void);
#ifdef CONFIG_PM_DEBUG
extern void omap2_pm_dump(int mode, int resume, unsigned int us);
extern int omap2_pm_debug;

2
arch/arm/mach-omap2/pm24xx.c
View File

@ -470,7 +470,7 @@ static void __init prcm_setup_regs(void)
WKUP_MOD, PM_WKEN);
}
int __init omap2_pm_init(void)
static int __init omap2_pm_init(void)
{
u32 l;

51
arch/arm/mach-omap2/pm34xx.c
View File

@ -39,7 +39,9 @@
struct power_state {
struct powerdomain *pwrdm;
u32 next_state;
#ifdef CONFIG_SUSPEND
u32 saved_state;
#endif
struct list_head node;
};
@ -293,6 +295,9 @@ out:
local_irq_enable();
}
#ifdef CONFIG_SUSPEND
static suspend_state_t suspend_state;
static int omap3_pm_prepare(void)
{
disable_hlt();
@ -321,7 +326,6 @@ static int omap3_pm_suspend(void)
restore:
/* Restore next_pwrsts */
list_for_each_entry(pwrst, &pwrst_list, node) {
set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
if (state > pwrst->next_state) {
printk(KERN_INFO "Powerdomain (%s) didn't enter "
@ -329,6 +333,7 @@ restore:
pwrst->pwrdm->name, pwrst->next_state);
ret = -1;
}
set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
}
if (ret)
printk(KERN_ERR "Could not enter target state in pm_suspend\n");
@ -339,11 +344,11 @@ restore:
return ret;
}
static int omap3_pm_enter(suspend_state_t state)
static int omap3_pm_enter(suspend_state_t unused)
{
int ret = 0;
switch (state) {
switch (suspend_state) {
case PM_SUSPEND_STANDBY:
case PM_SUSPEND_MEM:
ret = omap3_pm_suspend();
@ -360,12 +365,30 @@ static void omap3_pm_finish(void)
enable_hlt();
}
/* Hooks to enable / disable UART interrupts during suspend */
static int omap3_pm_begin(suspend_state_t state)
{
suspend_state = state;
omap_uart_enable_irqs(0);
return 0;
}
static void omap3_pm_end(void)
{
suspend_state = PM_SUSPEND_ON;
omap_uart_enable_irqs(1);
return;
}
static struct platform_suspend_ops omap_pm_ops = {
.begin = omap3_pm_begin,
.end = omap3_pm_end,
.prepare = omap3_pm_prepare,
.enter = omap3_pm_enter,
.finish = omap3_pm_finish,
.valid = suspend_valid_only_mem,
};
#endif /* CONFIG_SUSPEND */
/**
@ -613,6 +636,24 @@ static void __init prcm_setup_regs(void)
/* Clear any pending PRCM interrupts */
prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
/* Don't attach IVA interrupts */
prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
/* Clear any pending 'reset' flags */
prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
/* Clear any pending PRCM interrupts */
prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
omap3_iva_idle();
omap3_d2d_idle();
}
@ -652,7 +693,7 @@ static int __init clkdms_setup(struct clockdomain *clkdm)
return 0;
}
int __init omap3_pm_init(void)
static int __init omap3_pm_init(void)
{
struct power_state *pwrst, *tmp;
int ret;
@ -692,7 +733,9 @@ int __init omap3_pm_init(void)
_omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
omap34xx_cpu_suspend_sz);
#ifdef CONFIG_SUSPEND
suspend_set_ops(&omap_pm_ops);
#endif /* CONFIG_SUSPEND */
pm_idle = omap3_pm_idle;

43
arch/arm/mach-omap2/prcm.c
View File

@ -17,6 +17,7 @@
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <mach/common.h>
#include <mach/prcm.h>
@ -28,6 +29,8 @@
static void __iomem *prm_base;
static void __iomem *cm_base;
#define MAX_MODULE_ENABLE_WAIT 100000
u32 omap_prcm_get_reset_sources(void)
{
/* XXX This presumably needs modification for 34XX */
@ -120,6 +123,46 @@ u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
}
EXPORT_SYMBOL(cm_rmw_mod_reg_bits);
/**
* omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
* @reg: physical address of module IDLEST register
* @mask: value to mask against to determine if the module is active
* @name: name of the clock (for printk)
*
* Returns 1 if the module indicated readiness in time, or 0 if it
* failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
*/
int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name)
{
int i = 0;
int ena = 0;
/*
* 24xx uses 0 to indicate not ready, and 1 to indicate ready.
* 34xx reverses this, just to keep us on our toes
*/
if (cpu_is_omap24xx())
ena = mask;
else if (cpu_is_omap34xx())
ena = 0;
else
BUG();
/* Wait for lock */
while (((__raw_readl(reg) & mask) != ena) &&
(i++ < MAX_MODULE_ENABLE_WAIT))
udelay(1);
if (i < MAX_MODULE_ENABLE_WAIT)
pr_debug("cm: Module associated with clock %s ready after %d "
"loops\n", name, i);
else
pr_err("cm: Module associated with clock %s didn't enable in "
"%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
};
void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
{
prm_base = omap2_globals->prm;

68
arch/arm/mach-omap2/sdrc.c
View File

@ -32,7 +32,7 @@
#include <mach/sdrc.h>
#include "sdrc.h"
static struct omap_sdrc_params *sdrc_init_params;
static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
void __iomem *omap2_sdrc_base;
void __iomem *omap2_sms_base;
@ -45,33 +45,49 @@ void __iomem *omap2_sms_base;
/**
* omap2_sdrc_get_params - return SDRC register values for a given clock rate
* @r: SDRC clock rate (in Hz)
* @sdrc_cs0: chip select 0 ram timings **
* @sdrc_cs1: chip select 1 ram timings **
*
* Return pre-calculated values for the SDRC_ACTIM_CTRLA,
* SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL, and SDRC_MR registers, for a given
* SDRC clock rate 'r'. These parameters control various timing
* delays in the SDRAM controller that are expressed in terms of the
* number of SDRC clock cycles to wait; hence the clock rate
* dependency. Note that sdrc_init_params must be sorted rate
* descending. Also assumes that both chip-selects use the same
* timing parameters. Returns a struct omap_sdrc_params * upon
* success, or NULL upon failure.
* SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01]
* structs,for a given SDRC clock rate 'r'.
* These parameters control various timing delays in the SDRAM controller
* that are expressed in terms of the number of SDRC clock cycles to
* wait; hence the clock rate dependency.
*
* Supports 2 different timing parameters for both chip selects.
*
* Note 1: the sdrc_init_params_cs[01] must be sorted rate descending.
* Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size
* as sdrc_init_params_cs_0.
*
* Fills in the struct omap_sdrc_params * for each chip select.
* Returns 0 upon success or -1 upon failure.
*/
struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r)
int omap2_sdrc_get_params(unsigned long r,
struct omap_sdrc_params **sdrc_cs0,
struct omap_sdrc_params **sdrc_cs1)
{
struct omap_sdrc_params *sp;
struct omap_sdrc_params *sp0, *sp1;
if (!sdrc_init_params)
return NULL;
if (!sdrc_init_params_cs0)
return -1;
sp = sdrc_init_params;
sp0 = sdrc_init_params_cs0;
sp1 = sdrc_init_params_cs1;
while (sp->rate && sp->rate != r)
sp++;
while (sp0->rate && sp0->rate != r) {
sp0++;
if (sdrc_init_params_cs1)
sp1++;
}
if (!sp->rate)
return NULL;
if (!sp0->rate)
return -1;
return sp;
*sdrc_cs0 = sp0;
*sdrc_cs1 = sp1;
return 0;
}
@ -83,13 +99,15 @@ void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
/**
* omap2_sdrc_init - initialize SMS, SDRC devices on boot
* @sp: pointer to a null-terminated list of struct omap_sdrc_params
* @sdrc_cs[01]: pointers to a null-terminated list of struct omap_sdrc_params
* Support for 2 chip selects timings
*
* Turn on smart idle modes for SDRAM scheduler and controller.
* Program a known-good configuration for the SDRC to deal with buggy
* bootloaders.
*/
void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1)
{
u32 l;
@ -103,11 +121,15 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
l |= (0x2 << 3);
sdrc_write_reg(l, SDRC_SYSCONFIG);
sdrc_init_params = sp;
sdrc_init_params_cs0 = sdrc_cs0;
sdrc_init_params_cs1 = sdrc_cs1;
/* XXX Enable SRFRONIDLEREQ here also? */
/*
* PWDENA should not be set due to 34xx erratum 1.150 - PWDENA
* can cause random memory corruption
*/
l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
(1 << SDRC_POWER_PWDENA_SHIFT) |
(1 << SDRC_POWER_PAGEPOLICY_SHIFT);
sdrc_write_reg(l, SDRC_POWER);
}

199
arch/arm/mach-omap2/serial.c
View File

@ -54,6 +54,7 @@ struct omap_uart_state {
struct plat_serial8250_port *p;
struct list_head node;
struct platform_device pdev;
#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
int context_valid;
@ -68,10 +69,9 @@ struct omap_uart_state {
#endif
};
static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS];
static LIST_HEAD(uart_list);
static struct plat_serial8250_port serial_platform_data[] = {
static struct plat_serial8250_port serial_platform_data0[] = {
{
.membase = IO_ADDRESS(OMAP_UART1_BASE),
.mapbase = OMAP_UART1_BASE,
@ -81,6 +81,12 @@ static struct plat_serial8250_port serial_platform_data[] = {
.regshift = 2,
.uartclk = OMAP24XX_BASE_BAUD * 16,
}, {
.flags = 0
}
};
static struct plat_serial8250_port serial_platform_data1[] = {
{
.membase = IO_ADDRESS(OMAP_UART2_BASE),
.mapbase = OMAP_UART2_BASE,
.irq = 73,
@ -89,6 +95,12 @@ static struct plat_serial8250_port serial_platform_data[] = {
.regshift = 2,
.uartclk = OMAP24XX_BASE_BAUD * 16,
}, {
.flags = 0
}
};
static struct plat_serial8250_port serial_platform_data2[] = {
{
.membase = IO_ADDRESS(OMAP_UART3_BASE),
.mapbase = OMAP_UART3_BASE,
.irq = 74,
@ -217,6 +229,40 @@ static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
clk_disable(uart->fck);
}
static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
{
/* Set wake-enable bit */
if (uart->wk_en && uart->wk_mask) {
u32 v = __raw_readl(uart->wk_en);
v |= uart->wk_mask;
__raw_writel(v, uart->wk_en);
}
/* Ensure IOPAD wake-enables are set */
if (cpu_is_omap34xx() && uart->padconf) {
u16 v = omap_ctrl_readw(uart->padconf);
v |= OMAP3_PADCONF_WAKEUPENABLE0;
omap_ctrl_writew(v, uart->padconf);
}
}
static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
{
/* Clear wake-enable bit */
if (uart->wk_en && uart->wk_mask) {
u32 v = __raw_readl(uart->wk_en);
v &= ~uart->wk_mask;
__raw_writel(v, uart->wk_en);
}
/* Ensure IOPAD wake-enables are cleared */
if (cpu_is_omap34xx() && uart->padconf) {
u16 v = omap_ctrl_readw(uart->padconf);
v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
omap_ctrl_writew(v, uart->padconf);
}
}
static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
int enable)
{
@ -246,6 +292,11 @@ static void omap_uart_block_sleep(struct omap_uart_state *uart)
static void omap_uart_allow_sleep(struct omap_uart_state *uart)
{
if (device_may_wakeup(&uart->pdev.dev))
omap_uart_enable_wakeup(uart);
else
omap_uart_disable_wakeup(uart);
if (!uart->clocked)
return;
@ -292,7 +343,6 @@ void omap_uart_resume_idle(int num)
/* Check for normal UART wakeup */
if (__raw_readl(uart->wk_st) & uart->wk_mask)
omap_uart_block_sleep(uart);
return;
}
}
@ -346,16 +396,13 @@ static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
return IRQ_NONE;
}
static u32 sleep_timeout = DEFAULT_TIMEOUT;
static void omap_uart_idle_init(struct omap_uart_state *uart)
{
u32 v;
struct plat_serial8250_port *p = uart->p;
int ret;
uart->can_sleep = 0;
uart->timeout = sleep_timeout;
uart->timeout = DEFAULT_TIMEOUT;
setup_timer(&uart->timer, omap_uart_idle_timer,
(unsigned long) uart);
mod_timer(&uart->timer, jiffies + uart->timeout);
@ -413,76 +460,101 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
uart->padconf = 0;
}
/* Set wake-enable bit */
if (uart->wk_en && uart->wk_mask) {
v = __raw_readl(uart->wk_en);
v |= uart->wk_mask;
__raw_writel(v, uart->wk_en);
}
/* Ensure IOPAD wake-enables are set */
if (cpu_is_omap34xx() && uart->padconf) {
u16 v;
v = omap_ctrl_readw(uart->padconf);
v |= OMAP3_PADCONF_WAKEUPENABLE0;
omap_ctrl_writew(v, uart->padconf);
}
p->flags |= UPF_SHARE_IRQ;
ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
"serial idle", (void *)uart);
WARN_ON(ret);
}
static ssize_t sleep_timeout_show(struct kobject *kobj,
struct kobj_attribute *attr,
char *buf)
void omap_uart_enable_irqs(int enable)
{
return sprintf(buf, "%u\n", sleep_timeout / HZ);
int ret;
struct omap_uart_state *uart;
list_for_each_entry(uart, &uart_list, node) {
if (enable)
ret = request_irq(uart->p->irq, omap_uart_interrupt,
IRQF_SHARED, "serial idle", (void *)uart);
else
free_irq(uart->p->irq, (void *)uart);
}
}
static ssize_t sleep_timeout_store(struct kobject *kobj,
struct kobj_attribute *attr,
static ssize_t sleep_timeout_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct platform_device *pdev = container_of(dev,
struct platform_device, dev);
struct omap_uart_state *uart = container_of(pdev,
struct omap_uart_state, pdev);
return sprintf(buf, "%u\n", uart->timeout / HZ);
}
static ssize_t sleep_timeout_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t n)
{
struct omap_uart_state *uart;
struct platform_device *pdev = container_of(dev,
struct platform_device, dev);
struct omap_uart_state *uart = container_of(pdev,
struct omap_uart_state, pdev);
unsigned int value;
if (sscanf(buf, "%u", &value) != 1) {
printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
return -EINVAL;
}
sleep_timeout = value * HZ;
list_for_each_entry(uart, &uart_list, node) {
uart->timeout = sleep_timeout;
if (uart->timeout)
mod_timer(&uart->timer, jiffies + uart->timeout);
else
/* A zero value means disable timeout feature */
omap_uart_block_sleep(uart);
}
uart->timeout = value * HZ;
if (uart->timeout)
mod_timer(&uart->timer, jiffies + uart->timeout);
else
/* A zero value means disable timeout feature */
omap_uart_block_sleep(uart);
return n;
}
static struct kobj_attribute sleep_timeout_attr =
__ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
#define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
#else
static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
#define DEV_CREATE_FILE(dev, attr)
#endif /* CONFIG_PM */
static struct platform_device serial_device = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = serial_platform_data,
static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS] = {
{
.pdev = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = serial_platform_data0,
},
},
}, {
.pdev = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM1,
.dev = {
.platform_data = serial_platform_data1,
},
},
}, {
.pdev = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM2,
.dev = {
.platform_data = serial_platform_data2,
},
},
},
};
void __init omap_serial_init(void)
{
int i, err;
int i;
const struct omap_uart_config *info;
char name[16];
@ -496,14 +568,12 @@ void __init omap_serial_init(void)
if (info == NULL)
return;
if (cpu_is_omap44xx()) {
for (i = 0; i < OMAP_MAX_NR_PORTS; i++)
serial_platform_data[i].irq += 32;
}
for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
struct plat_serial8250_port *p = serial_platform_data + i;
struct omap_uart_state *uart = &omap_uart[i];
struct platform_device *pdev = &uart->pdev;
struct device *dev = &pdev->dev;
struct plat_serial8250_port *p = dev->platform_data;
if (!(info->enabled_uarts & (1 << i))) {
p->membase = NULL;
@ -531,20 +601,21 @@ void __init omap_serial_init(void)
uart->num = i;
p->private_data = uart;
uart->p = p;
list_add(&uart->node, &uart_list);
list_add_tail(&uart->node, &uart_list);
if (cpu_is_omap44xx())
p->irq += 32;
omap_uart_enable_clocks(uart);
omap_uart_reset(uart);
omap_uart_idle_init(uart);
if (WARN_ON(platform_device_register(pdev)))
continue;
if ((cpu_is_omap34xx() && uart->padconf) ||
(uart->wk_en && uart->wk_mask)) {
device_init_wakeup(dev, true);
DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
}
}
err = platform_device_register(&serial_device);
#ifdef CONFIG_PM
if (!err)
err = sysfs_create_file(&serial_device.dev.kobj,
&sleep_timeout_attr.attr);
#endif
}

147
arch/arm/mach-omap2/sram34xx.S
View File

@ -36,7 +36,7 @@
.text
/* r4 parameters */
/* r1 parameters */
#define SDRC_NO_UNLOCK_DLL 0x0
#define SDRC_UNLOCK_DLL 0x1
@ -58,7 +58,6 @@
/* SDRC_POWER bit settings */
#define SRFRONIDLEREQ_MASK 0x40
#define PWDENA_MASK 0x4
/* CM_IDLEST1_CORE bit settings */
#define ST_SDRC_MASK 0x2
@ -71,41 +70,72 @@
/*
* omap3_sram_configure_core_dpll - change DPLL3 M2 divider
* r0 = new SDRC_RFR_CTRL register contents
* r1 = new SDRC_ACTIM_CTRLA register contents
* r2 = new SDRC_ACTIM_CTRLB register contents
* r3 = new M2 divider setting (only 1 and 2 supported right now)
* r4 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for
* SDRC rates < 83MHz
* r5 = number of MPU cycles to wait for SDRC to stabilize after
* reprogramming the SDRC when switching to a slower MPU speed
* r6 = new SDRC_MR_0 register value
* r7 = increasing SDRC rate? (1 = yes, 0 = no)
*
* Params passed in registers:
* r0 = new M2 divider setting (only 1 and 2 supported right now)
* r1 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for
* SDRC rates < 83MHz
* r2 = number of MPU cycles to wait for SDRC to stabilize after
* reprogramming the SDRC when switching to a slower MPU speed
* r3 = increasing SDRC rate? (1 = yes, 0 = no)
*
* Params passed via the stack. The needed params will be copied in SRAM
* before use by the code in SRAM (SDRAM is not accessible during SDRC
* reconfiguration):
* new SDRC_RFR_CTRL_0 register contents
* new SDRC_ACTIM_CTRL_A_0 register contents
* new SDRC_ACTIM_CTRL_B_0 register contents
* new SDRC_MR_0 register value
* new SDRC_RFR_CTRL_1 register contents
* new SDRC_ACTIM_CTRL_A_1 register contents
* new SDRC_ACTIM_CTRL_B_1 register contents
* new SDRC_MR_1 register value
*
* If the param SDRC_RFR_CTRL_1 is 0, the parameters
* are not programmed into the SDRC CS1 registers
*/
ENTRY(omap3_sram_configure_core_dpll)
stmfd sp!, {r1-r12, lr} @ store regs to stack
ldr r4, [sp, #52] @ pull extra args off the stack
ldr r5, [sp, #56] @ load extra args from the stack
ldr r6, [sp, #60] @ load extra args from the stack
ldr r7, [sp, #64] @ load extra args from the stack
@ pull the extra args off the stack
@ and store them in SRAM
ldr r4, [sp, #52]
str r4, omap_sdrc_rfr_ctrl_0_val
ldr r4, [sp, #56]
str r4, omap_sdrc_actim_ctrl_a_0_val
ldr r4, [sp, #60]
str r4, omap_sdrc_actim_ctrl_b_0_val
ldr r4, [sp, #64]
str r4, omap_sdrc_mr_0_val
ldr r4, [sp, #68]
str r4, omap_sdrc_rfr_ctrl_1_val
cmp r4, #0 @ if SDRC_RFR_CTRL_1 is 0,
beq skip_cs1_params @ do not use cs1 params
ldr r4, [sp, #72]
str r4, omap_sdrc_actim_ctrl_a_1_val
ldr r4, [sp, #76]
str r4, omap_sdrc_actim_ctrl_b_1_val
ldr r4, [sp, #80]
str r4, omap_sdrc_mr_1_val
skip_cs1_params:
dsb @ flush buffered writes to interconnect
cmp r7, #1 @ if increasing SDRC clk rate,
cmp r3, #1 @ if increasing SDRC clk rate,
bleq configure_sdrc @ program the SDRC regs early (for RFR)
cmp r4, #SDRC_UNLOCK_DLL @ set the intended DLL state
cmp r1, #SDRC_UNLOCK_DLL @ set the intended DLL state
bleq unlock_dll
blne lock_dll
bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC
bl configure_core_dpll @ change the DPLL3 M2 divider
mov r12, r2
bl wait_clk_stable @ wait for SDRC to stabilize
bl enable_sdrc @ take SDRC out of idle
cmp r4, #SDRC_UNLOCK_DLL @ wait for DLL status to change
cmp r1, #SDRC_UNLOCK_DLL @ wait for DLL status to change
bleq wait_dll_unlock
blne wait_dll_lock
cmp r7, #1 @ if increasing SDRC clk rate,
cmp r3, #1 @ if increasing SDRC clk rate,
beq return_to_sdram @ return to SDRAM code, otherwise,
bl configure_sdrc @ reprogram SDRC regs now
mov r12, r5
bl wait_clk_stable @ wait for SDRC to stabilize
return_to_sdram:
isb @ prevent speculative exec past here
mov r0, #0 @ return value
@ -113,7 +143,7 @@ return_to_sdram:
unlock_dll:
ldr r11, omap3_sdrc_dlla_ctrl
ldr r12, [r11]
and r12, r12, #FIXEDDELAY_MASK
bic r12, r12, #FIXEDDELAY_MASK
orr r12, r12, #FIXEDDELAY_DEFAULT
orr r12, r12, #DLLIDLE_MASK
str r12, [r11] @ (no OCP barrier needed)
@ -129,7 +159,6 @@ sdram_in_selfrefresh:
ldr r12, [r11] @ read the contents of SDRC_POWER
mov r9, r12 @ keep a copy of SDRC_POWER bits
orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle
bic r12, r12, #PWDENA_MASK @ clear PWDENA
str r12, [r11] @ write back to SDRC_POWER register
ldr r12, [r11] @ posted-write barrier for SDRC
idle_sdrc:
@ -149,7 +178,7 @@ configure_core_dpll:
ldr r12, [r11]
ldr r10, core_m2_mask_val @ modify m2 for core dpll
and r12, r12, r10
orr r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
orr r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
str r12, [r11]
ldr r12, [r11] @ posted-write barrier for CM
bx lr
@ -187,15 +216,34 @@ wait_dll_unlock:
bne wait_dll_unlock
bx lr
configure_sdrc:
ldr r11, omap3_sdrc_rfr_ctrl
str r0, [r11]
ldr r11, omap3_sdrc_actim_ctrla
str r1, [r11]
ldr r11, omap3_sdrc_actim_ctrlb
str r2, [r11]
ldr r12, omap_sdrc_rfr_ctrl_0_val @ fetch value from SRAM
ldr r11, omap3_sdrc_rfr_ctrl_0 @ fetch addr from SRAM
str r12, [r11] @ store
ldr r12, omap_sdrc_actim_ctrl_a_0_val
ldr r11, omap3_sdrc_actim_ctrl_a_0
str r12, [r11]
ldr r12, omap_sdrc_actim_ctrl_b_0_val
ldr r11, omap3_sdrc_actim_ctrl_b_0
str r12, [r11]
ldr r12, omap_sdrc_mr_0_val
ldr r11, omap3_sdrc_mr_0
str r6, [r11]
ldr r6, [r11] @ posted-write barrier for SDRC
str r12, [r11]
ldr r12, omap_sdrc_rfr_ctrl_1_val
cmp r12, #0 @ if SDRC_RFR_CTRL_1 is 0,
beq skip_cs1_prog @ do not program cs1 params
ldr r11, omap3_sdrc_rfr_ctrl_1
str r12, [r11]
ldr r12, omap_sdrc_actim_ctrl_a_1_val
ldr r11, omap3_sdrc_actim_ctrl_a_1
str r12, [r11]
ldr r12, omap_sdrc_actim_ctrl_b_1_val
ldr r11, omap3_sdrc_actim_ctrl_b_1
str r12, [r11]
ldr r12, omap_sdrc_mr_1_val
ldr r11, omap3_sdrc_mr_1
str r12, [r11]
skip_cs1_prog:
ldr r12, [r11] @ posted-write barrier for SDRC
bx lr
omap3_sdrc_power:
@ -206,14 +254,40 @@ omap3_cm_idlest1_core:
.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
omap3_cm_iclken1_core:
.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
omap3_sdrc_rfr_ctrl:
omap3_sdrc_rfr_ctrl_0:
.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
omap3_sdrc_actim_ctrla:
omap3_sdrc_rfr_ctrl_1:
.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
omap3_sdrc_actim_ctrl_a_0:
.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
omap3_sdrc_actim_ctrlb:
omap3_sdrc_actim_ctrl_a_1:
.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
omap3_sdrc_actim_ctrl_b_0:
.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
omap3_sdrc_actim_ctrl_b_1:
.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
omap3_sdrc_mr_0:
.word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
omap3_sdrc_mr_1:
.word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
omap_sdrc_rfr_ctrl_0_val:
.word 0xDEADBEEF
omap_sdrc_rfr_ctrl_1_val:
.word 0xDEADBEEF
omap_sdrc_actim_ctrl_a_0_val:
.word 0xDEADBEEF
omap_sdrc_actim_ctrl_a_1_val:
.word 0xDEADBEEF
omap_sdrc_actim_ctrl_b_0_val:
.word 0xDEADBEEF
omap_sdrc_actim_ctrl_b_1_val:
.word 0xDEADBEEF
omap_sdrc_mr_0_val:
.word 0xDEADBEEF
omap_sdrc_mr_1_val:
.word 0xDEADBEEF
omap3_sdrc_dlla_status:
.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
omap3_sdrc_dlla_ctrl:
@ -223,3 +297,4 @@ core_m2_mask_val:
ENTRY(omap3_sram_configure_core_dpll_sz)
.word . - omap3_sram_configure_core_dpll

2
arch/arm/mach-u300/core.c
View File

@ -510,7 +510,7 @@ static struct db_chip db_chips[] __initdata = {
}
};
static void u300_init_check_chip(void)
static void __init u300_init_check_chip(void)
{
u16 val;

118
arch/arm/mm/init.c
View File

@ -120,6 +120,32 @@ void show_mem(void)
printk("%d pages swap cached\n", cached);
}
static void __init find_node_limits(int node, struct meminfo *mi,
unsigned long *min, unsigned long *max_low, unsigned long *max_high)
{
int i;
*min = -1UL;
*max_low = *max_high = 0;
for_each_nodebank(i, mi, node) {
struct membank *bank = &mi->bank[i];
unsigned long start, end;
start = bank_pfn_start(bank);
end = bank_pfn_end(bank);
if (*min > start)
*min = start;
if (*max_high < end)
*max_high = end;
if (bank->highmem)
continue;
if (*max_low < end)
*max_low = end;
}
}
/*
* FIXME: We really want to avoid allocating the bootmap bitmap
* over the top of the initrd. Hopefully, this is located towards
@ -210,40 +236,24 @@ static inline void map_memory_bank(struct membank *bank)
#endif
}
static unsigned long __init bootmem_init_node(int node, struct meminfo *mi)
static void __init bootmem_init_node(int node, struct meminfo *mi,
unsigned long start_pfn, unsigned long end_pfn)
{
unsigned long start_pfn, end_pfn, boot_pfn;
unsigned long boot_pfn;
unsigned int boot_pages;
pg_data_t *pgdat;
int i;
start_pfn = -1UL;
end_pfn = 0;
/*
* Calculate the pfn range, and map the memory banks for this node.
* Map the memory banks for this node.
*/
for_each_nodebank(i, mi, node) {
struct membank *bank = &mi->bank[i];
unsigned long start, end;
start = bank_pfn_start(bank);
end = bank_pfn_end(bank);
if (start_pfn > start)
start_pfn = start;
if (end_pfn < end)
end_pfn = end;
map_memory_bank(bank);
if (!bank->highmem)
map_memory_bank(bank);
}
/*
* If there is no memory in this node, ignore it.
*/
if (end_pfn == 0)
return end_pfn;
/*
* Allocate the bootmem bitmap page.
*/
@ -260,7 +270,8 @@ static unsigned long __init bootmem_init_node(int node, struct meminfo *mi)
for_each_nodebank(i, mi, node) {
struct membank *bank = &mi->bank[i];
free_bootmem_node(pgdat, bank_phys_start(bank), bank_phys_size(bank));
if (!bank->highmem)
free_bootmem_node(pgdat, bank_phys_start(bank), bank_phys_size(bank));
memory_present(node, bank_pfn_start(bank), bank_pfn_end(bank));
}
@ -269,8 +280,6 @@ static unsigned long __init bootmem_init_node(int node, struct meminfo *mi)
*/
reserve_bootmem_node(pgdat, boot_pfn << PAGE_SHIFT,
boot_pages << PAGE_SHIFT, BOOTMEM_DEFAULT);
return end_pfn;
}
static void __init bootmem_reserve_initrd(int node)
@ -297,33 +306,39 @@ static void __init bootmem_reserve_initrd(int node)
static void __init bootmem_free_node(int node, struct meminfo *mi)
{
unsigned long zone_size[MAX_NR_ZONES], zhole_size[MAX_NR_ZONES];
unsigned long start_pfn, end_pfn;
pg_data_t *pgdat = NODE_DATA(node);
unsigned long min, max_low, max_high;
int i;
start_pfn = pgdat->bdata->node_min_pfn;
end_pfn = pgdat->bdata->node_low_pfn;
find_node_limits(node, mi, &min, &max_low, &max_high);
/*
* initialise the zones within this node.
*/
memset(zone_size, 0, sizeof(zone_size));
memset(zhole_size, 0, sizeof(zhole_size));
/*
* The size of this node has already been determined. If we need
* to do anything fancy with the allocation of this memory to the
* zones, now is the time to do it.
*/
zone_size[0] = end_pfn - start_pfn;
zone_size[0] = max_low - min;
#ifdef CONFIG_HIGHMEM
zone_size[ZONE_HIGHMEM] = max_high - max_low;
#endif
/*
* For each bank in this node, calculate the size of the holes.
* holes = node_size - sum(bank_sizes_in_node)
*/
zhole_size[0] = zone_size[0];
for_each_nodebank(i, mi, node)
zhole_size[0] -= bank_pfn_size(&mi->bank[i]);
memcpy(zhole_size, zone_size, sizeof(zhole_size));
for_each_nodebank(i, mi, node) {
int idx = 0;
#ifdef CONFIG_HIGHMEM
if (mi->bank[i].highmem)
idx = ZONE_HIGHMEM;
#endif
zhole_size[idx] -= bank_pfn_size(&mi->bank[i]);
}
/*
* Adjust the sizes according to any special requirements for
@ -331,13 +346,13 @@ static void __init bootmem_free_node(int node, struct meminfo *mi)
*/
arch_adjust_zones(node, zone_size, zhole_size);
free_area_init_node(node, zone_size, start_pfn, zhole_size);
free_area_init_node(node, zone_size, min, zhole_size);
}
void __init bootmem_init(void)
{
struct meminfo *mi = &meminfo;
unsigned long memend_pfn = 0;
unsigned long min, max_low, max_high;
int node, initrd_node;
/*
@ -345,11 +360,29 @@ void __init bootmem_init(void)
*/
initrd_node = check_initrd(mi);
max_low = max_high = 0;
/*
* Run through each node initialising the bootmem allocator.
*/
for_each_node(node) {
unsigned long end_pfn = bootmem_init_node(node, mi);
unsigned long node_low, node_high;
find_node_limits(node, mi, &min, &node_low, &node_high);
if (node_low > max_low)
max_low = node_low;
if (node_high > max_high)
max_high = node_high;
/*
* If there is no memory in this node, ignore it.
* (We can't have nodes which have no lowmem)
*/
if (node_low == 0)
continue;
bootmem_init_node(node, mi, min, node_low);
/*
* Reserve any special node zero regions.
@ -362,12 +395,6 @@ void __init bootmem_init(void)
*/
if (node == initrd_node)
bootmem_reserve_initrd(node);
/*
* Remember the highest memory PFN.
*/
if (end_pfn > memend_pfn)
memend_pfn = end_pfn;
}
/*
@ -383,7 +410,7 @@ void __init bootmem_init(void)
for_each_node(node)
bootmem_free_node(node, mi);
high_memory = __va((memend_pfn << PAGE_SHIFT) - 1) + 1;
high_memory = __va((max_low << PAGE_SHIFT) - 1) + 1;
/*
* This doesn't seem to be used by the Linux memory manager any
@ -393,7 +420,8 @@ void __init bootmem_init(void)
* Note: max_low_pfn and max_pfn reflect the number of _pages_ in
* the system, not the maximum PFN.
*/
max_pfn = max_low_pfn = memend_pfn - PHYS_PFN_OFFSET;
max_low_pfn = max_low - PHYS_PFN_OFFSET;
max_pfn = max_high - PHYS_PFN_OFFSET;
}
static inline int free_area(unsigned long pfn, unsigned long end, char *s)

9
arch/arm/mm/mmu.c
View File

@ -687,13 +687,19 @@ __early_param("vmalloc=", early_vmalloc);
static void __init sanity_check_meminfo(void)
{
int i, j;
int i, j, highmem = 0;
for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
struct membank *bank = &meminfo.bank[j];
*bank = meminfo.bank[i];
#ifdef CONFIG_HIGHMEM
if (__va(bank->start) > VMALLOC_MIN ||
__va(bank->start) < (void *)PAGE_OFFSET)
highmem = 1;
bank->highmem = highmem;
/*
* Split those memory banks which are partially overlapping
* the vmalloc area greatly simplifying things later.
@ -714,6 +720,7 @@ static void __init sanity_check_meminfo(void)
i++;
bank[1].size -= VMALLOC_MIN - __va(bank->start);
bank[1].start = __pa(VMALLOC_MIN - 1) + 1;
bank[1].highmem = highmem = 1;
j++;
}
bank->size = VMALLOC_MIN - __va(bank->start);

8
arch/arm/plat-omap/cpu-omap.c
View File

@ -78,10 +78,10 @@ static int omap_target(struct cpufreq_policy *policy,
/* Ensure desired rate is within allowed range. Some govenors
* (ondemand) will just pass target_freq=0 to get the minimum. */
if (target_freq < policy->cpuinfo.min_freq)
target_freq = policy->cpuinfo.min_freq;
if (target_freq > policy->cpuinfo.max_freq)
target_freq = policy->cpuinfo.max_freq;
if (target_freq < policy->min)
target_freq = policy->min;
if (target_freq > policy->max)
target_freq = policy->max;
freqs.old = omap_getspeed(0);
freqs.new = clk_round_rate(mpu_clk, target_freq * 1000) / 1000;

11
arch/arm/plat-omap/debug-leds.c
View File

@ -281,24 +281,27 @@ static int /* __init */ fpga_probe(struct platform_device *pdev)
return 0;
}
static int fpga_suspend_late(struct platform_device *pdev, pm_message_t mesg)
static int fpga_suspend_noirq(struct device *dev)
{
__raw_writew(~0, &fpga->leds);
return 0;
}
static int fpga_resume_early(struct platform_device *pdev)
static int fpga_resume_noirq(struct device *dev)
{
__raw_writew(~hw_led_state, &fpga->leds);
return 0;
}
static struct dev_pm_ops fpga_dev_pm_ops = {
.suspend_noirq = fpga_suspend_noirq,
.resume_noirq = fpga_resume_noirq,
};
static struct platform_driver led_driver = {
.driver.name = "omap_dbg_led",
.driver.pm = &fpga_dev_pm_ops,
.probe = fpga_probe,
.suspend_late = fpga_suspend_late,
.resume_early = fpga_resume_early,
};
static int __init fpga_init(void)

4
arch/arm/plat-omap/dma.c
View File

@ -946,7 +946,9 @@ void omap_start_dma(int lch)
cur_lch = next_lch;
} while (next_lch != -1);
} else if (cpu_class_is_omap2()) {
} else if (cpu_is_omap242x() ||
(cpu_is_omap243x() && omap_type() <= OMAP2430_REV_ES1_0)) {
/* Errata: Need to write lch even if not using chaining */
dma_write(lch, CLNK_CTRL(lch));
}

141
arch/arm/plat-omap/gpio.c
View File

@ -476,14 +476,12 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
__raw_writel(l, reg);
}
static int __omap_get_gpio_datain(int gpio)
static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
{
struct gpio_bank *bank;
void __iomem *reg;
if (check_gpio(gpio) < 0)
return -EINVAL;
bank = get_gpio_bank(gpio);
reg = bank->base;
switch (bank->method) {
#ifdef CONFIG_ARCH_OMAP1
@ -524,6 +522,53 @@ static int __omap_get_gpio_datain(int gpio)
& (1 << get_gpio_index(gpio))) != 0;
}
static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
{
void __iomem *reg;
if (check_gpio(gpio) < 0)
return -EINVAL;
reg = bank->base;
switch (bank->method) {
#ifdef CONFIG_ARCH_OMAP1
case METHOD_MPUIO:
reg += OMAP_MPUIO_OUTPUT;
break;
#endif
#ifdef CONFIG_ARCH_OMAP15XX
case METHOD_GPIO_1510:
reg += OMAP1510_GPIO_DATA_OUTPUT;
break;
#endif
#ifdef CONFIG_ARCH_OMAP16XX
case METHOD_GPIO_1610:
reg += OMAP1610_GPIO_DATAOUT;
break;
#endif
#ifdef CONFIG_ARCH_OMAP730
case METHOD_GPIO_730:
reg += OMAP730_GPIO_DATA_OUTPUT;
break;
#endif
#ifdef CONFIG_ARCH_OMAP850
case METHOD_GPIO_850:
reg += OMAP850_GPIO_DATA_OUTPUT;
break;
#endif
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
defined(CONFIG_ARCH_OMAP4)
case METHOD_GPIO_24XX:
reg += OMAP24XX_GPIO_DATAOUT;
break;
#endif
default:
return -EINVAL;
}
return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
}
#define MOD_REG_BIT(reg, bit_mask, set) \
do { \
int l = __raw_readl(base + reg); \
@ -1189,6 +1234,7 @@ static void gpio_mask_irq(unsigned int irq)
struct gpio_bank *bank = get_irq_chip_data(irq);
_set_gpio_irqenable(bank, gpio, 0);
_set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
}
static void gpio_unmask_irq(unsigned int irq)
@ -1196,6 +1242,11 @@ static void gpio_unmask_irq(unsigned int irq)
unsigned int gpio = irq - IH_GPIO_BASE;
struct gpio_bank *bank = get_irq_chip_data(irq);
unsigned int irq_mask = 1 << get_gpio_index(gpio);
struct irq_desc *desc = irq_to_desc(irq);
u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
if (trigger)
_set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
/* For level-triggered GPIOs, the clearing must be done after
* the HW source is cleared, thus after the handler has run */
@ -1264,8 +1315,9 @@ static struct irq_chip mpuio_irq_chip = {
#include <linux/platform_device.h>
static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
static int omap_mpuio_suspend_noirq(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct gpio_bank *bank = platform_get_drvdata(pdev);
void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
unsigned long flags;
@ -1278,8 +1330,9 @@ static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t me
return 0;
}
static int omap_mpuio_resume_early(struct platform_device *pdev)
static int omap_mpuio_resume_noirq(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct gpio_bank *bank = platform_get_drvdata(pdev);
void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
unsigned long flags;
@ -1291,14 +1344,18 @@ static int omap_mpuio_resume_early(struct platform_device *pdev)
return 0;
}
static struct dev_pm_ops omap_mpuio_dev_pm_ops = {
.suspend_noirq = omap_mpuio_suspend_noirq,
.resume_noirq = omap_mpuio_resume_noirq,
};
/* use platform_driver for this, now that there's no longer any
* point to sys_device (other than not disturbing old code).
*/
static struct platform_driver omap_mpuio_driver = {
.suspend_late = omap_mpuio_suspend_late,
.resume_early = omap_mpuio_resume_early,
.driver = {
.name = "mpuio",
.pm = &omap_mpuio_dev_pm_ops,
},
};
@ -1350,9 +1407,49 @@ static int gpio_input(struct gpio_chip *chip, unsigned offset)
return 0;
}
static int gpio_is_input(struct gpio_bank *bank, int mask)
{
void __iomem *reg = bank->base;
switch (bank->method) {
case METHOD_MPUIO:
reg += OMAP_MPUIO_IO_CNTL;
break;
case METHOD_GPIO_1510:
reg += OMAP1510_GPIO_DIR_CONTROL;
break;
case METHOD_GPIO_1610:
reg += OMAP1610_GPIO_DIRECTION;
break;
case METHOD_GPIO_730:
reg += OMAP730_GPIO_DIR_CONTROL;
break;
case METHOD_GPIO_850:
reg += OMAP850_GPIO_DIR_CONTROL;
break;
case METHOD_GPIO_24XX:
reg += OMAP24XX_GPIO_OE;
break;
}
return __raw_readl(reg) & mask;
}
static int gpio_get(struct gpio_chip *chip, unsigned offset)
{
return __omap_get_gpio_datain(chip->base + offset);
struct gpio_bank *bank;
void __iomem *reg;
int gpio;
u32 mask;
gpio = chip->base + offset;
bank = get_gpio_bank(gpio);
reg = bank->base;
mask = 1 << get_gpio_index(gpio);
if (gpio_is_input(bank, mask))
return _get_gpio_datain(bank, gpio);
else
return _get_gpio_dataout(bank, gpio);
}
static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
@ -1886,34 +1983,6 @@ arch_initcall(omap_gpio_sysinit);
#include <linux/debugfs.h>
#include <linux/seq_file.h>
static int gpio_is_input(struct gpio_bank *bank, int mask)
{
void __iomem *reg = bank->base;
switch (bank->method) {
case METHOD_MPUIO:
reg += OMAP_MPUIO_IO_CNTL;
break;
case METHOD_GPIO_1510:
reg += OMAP1510_GPIO_DIR_CONTROL;
break;
case METHOD_GPIO_1610:
reg += OMAP1610_GPIO_DIRECTION;
break;
case METHOD_GPIO_730:
reg += OMAP730_GPIO_DIR_CONTROL;
break;
case METHOD_GPIO_850:
reg += OMAP850_GPIO_DIR_CONTROL;
break;
case METHOD_GPIO_24XX:
reg += OMAP24XX_GPIO_OE;
break;
}
return __raw_readl(reg) & mask;
}
static int dbg_gpio_show(struct seq_file *s, void *unused)
{
unsigned i, j, gpio;

2
arch/arm/plat-omap/include/mach/clock.h
View File

@ -20,6 +20,8 @@ struct clockdomain;
struct clkops {
int (*enable)(struct clk *);
void (*disable)(struct clk *);
void (*find_idlest)(struct clk *, void __iomem **, u8 *);
void (*find_companion)(struct clk *, void __iomem **, u8 *);
};
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \

5
arch/arm/plat-omap/include/mach/cpu.h
View File

@ -378,9 +378,6 @@ IS_OMAP_TYPE(3430, 0x3430)
#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \
cpu_is_omap44xx())
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
defined(CONFIG_ARCH_OMAP4)
/* Various silicon revisions for omap2 */
#define OMAP242X_CLASS 0x24200024
#define OMAP2420_REV_ES1_0 0x24200024
@ -436,5 +433,3 @@ IS_OMAP_TYPE(3430, 0x3430)
int omap_chip_is(struct omap_chip_id oci);
void omap2_check_revision(void);
#endif /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */

3
arch/arm/plat-omap/include/mach/io.h
View File

@ -228,7 +228,8 @@ extern void omap1_map_common_io(void);
extern void omap1_init_common_hw(void);
extern void omap2_map_common_io(void);
extern void omap2_init_common_hw(struct omap_sdrc_params *sp);
extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1);
#define __arch_ioremap(p,s,t) omap_ioremap(p,s,t)
#define __arch_iounmap(v) omap_iounmap(v)

4
arch/arm/plat-omap/include/mach/mux.h
View File

@ -853,6 +853,10 @@ enum omap34xx_index {
AE5_34XX_GPIO143,
H19_34XX_GPIO164_OUT,
J25_34XX_GPIO170,
/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
H16_34XX_SDRC_CKE0,
H17_34XX_SDRC_CKE1,
};
struct omap_mux_cfg {

1
arch/arm/plat-omap/include/mach/prcm.h
View File

@ -25,6 +25,7 @@
u32 omap_prcm_get_reset_sources(void);
void omap_prcm_arch_reset(char mode);
int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name);
#endif

11
arch/arm/plat-omap/include/mach/sdrc.h
View File

@ -30,6 +30,10 @@
#define SDRC_ACTIM_CTRL_A_0 0x09c
#define SDRC_ACTIM_CTRL_B_0 0x0a0
#define SDRC_RFR_CTRL_0 0x0a4
#define SDRC_MR_1 0x0B4
#define SDRC_ACTIM_CTRL_A_1 0x0C4
#define SDRC_ACTIM_CTRL_B_1 0x0C8
#define SDRC_RFR_CTRL_1 0x0D4
/*
* These values represent the number of memory clock cycles between
@ -102,8 +106,11 @@ struct omap_sdrc_params {
u32 mr;
};
void __init omap2_sdrc_init(struct omap_sdrc_params *sp);
struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r);
void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1);
int omap2_sdrc_get_params(unsigned long r,
struct omap_sdrc_params **sdrc_cs0,
struct omap_sdrc_params **sdrc_cs1);
#ifdef CONFIG_ARCH_OMAP2

1
arch/arm/plat-omap/include/mach/serial.h
View File

@ -59,6 +59,7 @@ extern void omap_uart_check_wakeup(void);
extern void omap_uart_prepare_suspend(void);
extern void omap_uart_prepare_idle(int num);
extern void omap_uart_resume_idle(int num);
extern void omap_uart_enable_irqs(int enable);
#endif
#endif

23
arch/arm/plat-omap/include/mach/sram.h
View File

@ -21,11 +21,12 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
u32 mem_type);
extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb, u32 m2,
u32 unlock_dll, u32 f, u32 sdrc_mr,
u32 inc);
extern u32 omap3_configure_core_dpll(
u32 m2, u32 unlock_dll, u32 f, u32 inc,
u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
/* Do not use these */
extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
@ -59,12 +60,12 @@ extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
u32 mem_type);
extern unsigned long omap243x_sram_reprogram_sdrc_sz;
extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb, u32 m2,
u32 unlock_dll, u32 f, u32 sdrc_mr,
u32 inc);
extern u32 omap3_sram_configure_core_dpll(
u32 m2, u32 unlock_dll, u32 f, u32 inc,
u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
extern unsigned long omap3_sram_configure_core_dpll_sz;
#endif

34
arch/arm/plat-omap/sram.c
View File

@ -44,9 +44,9 @@
#define OMAP2_SRAM_VA 0xe3000000
#define OMAP2_SRAM_PUB_VA (OMAP2_SRAM_VA + 0x800)
#define OMAP3_SRAM_PA 0x40200000
#define OMAP3_SRAM_VA 0xd7000000
#define OMAP3_SRAM_VA 0xe3000000
#define OMAP3_SRAM_PUB_PA 0x40208000
#define OMAP3_SRAM_PUB_VA 0xd7008000
#define OMAP3_SRAM_PUB_VA (OMAP3_SRAM_VA + 0x8000)
#define OMAP4_SRAM_PA 0x40200000 /*0x402f0000*/
#define OMAP4_SRAM_VA 0xd7000000 /*0xd70f0000*/
@ -373,20 +373,26 @@ static inline int omap243x_sram_init(void)
#ifdef CONFIG_ARCH_OMAP3
static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb,
u32 m2, u32 unlock_dll,
u32 f, u32 sdrc_mr, u32 inc);
u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
u32 f, u32 sdrc_mr, u32 inc)
static u32 (*_omap3_sram_configure_core_dpll)(
u32 m2, u32 unlock_dll, u32 f, u32 inc,
u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
{
BUG_ON(!_omap3_sram_configure_core_dpll);
return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
sdrc_actim_ctrla,
sdrc_actim_ctrlb, m2,
unlock_dll, f, sdrc_mr, inc);
return _omap3_sram_configure_core_dpll(
m2, unlock_dll, f, inc,
sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
sdrc_actim_ctrl_b_0, sdrc_mr_0,
sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
sdrc_actim_ctrl_b_1, sdrc_mr_1);
}
/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */

2
arch/arm/plat-s3c24xx/clock-dclk.c
View File

@ -129,7 +129,7 @@ static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
/* calculate the MISCCR setting for the clock */
if (parent == &clk_xtal)
if (parent == &clk_mpll)
source = S3C2410_MISCCR_CLK0_MPLL;
else if (parent == &clk_upll)
source = S3C2410_MISCCR_CLK0_UPLL;

3
arch/ia64/include/asm/device.h
View File

@ -15,4 +15,7 @@ struct dev_archdata {
#endif
};
struct pdev_archdata {
};
#endif /* _ASM_IA64_DEVICE_H */

70
arch/microblaze/configs/mmu_defconfig
View File

@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.30-rc6
# Fri May 22 10:02:33 2009
# Linux kernel version: 2.6.31-rc6
# Tue Aug 18 11:00:02 2009
#
CONFIG_MICROBLAZE=y
# CONFIG_SWAP is not set
@ -18,7 +18,11 @@ CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
CONFIG_GENERIC_GPIO=y
CONFIG_GENERIC_CSUM=y
# CONFIG_PCI is not set
CONFIG_NO_DMA=y
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
CONFIG_CONSTRUCTORS=y
#
# General setup
@ -59,8 +63,8 @@ CONFIG_INITRAMFS_ROOT_GID=0
CONFIG_RD_GZIP=y
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_LZMA is not set
CONFIG_INITRAMFS_COMPRESSION_NONE=y
# CONFIG_INITRAMFS_COMPRESSION_GZIP is not set
# CONFIG_INITRAMFS_COMPRESSION_NONE is not set
CONFIG_INITRAMFS_COMPRESSION_GZIP=y
# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set
# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@ -71,7 +75,6 @@ CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS=y
CONFIG_KALLSYMS_ALL=y
CONFIG_KALLSYMS_EXTRA_PASS=y
# CONFIG_STRIP_ASM_SYMS is not set
# CONFIG_HOTPLUG is not set
CONFIG_PRINTK=y
CONFIG_BUG=y
@ -84,13 +87,22 @@ CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
# CONFIG_SHMEM is not set
CONFIG_AIO=y
#
# Performance Counters
#
CONFIG_VM_EVENT_COUNTERS=y
# CONFIG_STRIP_ASM_SYMS is not set
CONFIG_COMPAT_BRK=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
# CONFIG_PROFILING is not set
# CONFIG_MARKERS is not set
#
# GCOV-based kernel profiling
#
# CONFIG_SLOW_WORK is not set
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_SLABINFO=y
@ -102,7 +114,7 @@ CONFIG_MODULE_UNLOAD=y
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_BLOCK=y
# CONFIG_LBD is not set
CONFIG_LBDAF=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_BLK_DEV_INTEGRITY is not set
@ -194,9 +206,9 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_PHYS_ADDR_T_64BIT is not set
CONFIG_ZONE_DMA_FLAG=0
CONFIG_VIRT_TO_BUS=y
CONFIG_UNEVICTABLE_LRU=y
CONFIG_HAVE_MLOCK=y
CONFIG_HAVE_MLOCKED_PAGE_BIT=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
#
# Exectuable file formats
@ -262,6 +274,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
# CONFIG_PHONET is not set
# CONFIG_IEEE802154 is not set
# CONFIG_NET_SCHED is not set
# CONFIG_DCB is not set
@ -325,7 +338,6 @@ CONFIG_MISC_DEVICES=y
# CONFIG_ATA is not set
# CONFIG_MD is not set
CONFIG_NETDEVICES=y
CONFIG_COMPAT_NET_DEV_OPS=y
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_MACVLAN is not set
@ -344,7 +356,7 @@ CONFIG_NET_ETHERNET=y
# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
# CONFIG_B44 is not set
# CONFIG_KS8842 is not set
CONFIG_NETDEV_1000=y
CONFIG_NETDEV_10000=y
@ -410,6 +422,11 @@ CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_TCG_TPM is not set
# CONFIG_I2C is not set
# CONFIG_SPI is not set
#
# PPS support
#
# CONFIG_PPS is not set
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
# CONFIG_GPIOLIB is not set
# CONFIG_W1 is not set
@ -418,12 +435,6 @@ CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
# CONFIG_THERMAL is not set
# CONFIG_THERMAL_HWMON is not set
# CONFIG_WATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
#
# Sonics Silicon Backplane
#
# CONFIG_SSB is not set
#
# Multifunction device drivers
@ -433,22 +444,7 @@ CONFIG_SSB_POSSIBLE=y
# CONFIG_HTC_PASIC3 is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_REGULATOR is not set
#
# Multimedia devices
#
#
# Multimedia core support
#
# CONFIG_VIDEO_DEV is not set
# CONFIG_DVB_CORE is not set
# CONFIG_VIDEO_MEDIA is not set
#
# Multimedia drivers
#
# CONFIG_DAB is not set
# CONFIG_MEDIA_SUPPORT is not set
#
# Graphics support
@ -469,9 +465,12 @@ CONFIG_SSB_POSSIBLE=y
# CONFIG_NEW_LEDS is not set
# CONFIG_ACCESSIBILITY is not set
# CONFIG_RTC_CLASS is not set
# CONFIG_DMADEVICES is not set
# CONFIG_AUXDISPLAY is not set
# CONFIG_UIO is not set
#
# TI VLYNQ
#
# CONFIG_STAGING is not set
#
@ -485,12 +484,15 @@ CONFIG_EXT2_FS=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
CONFIG_FILE_LOCKING=y
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_BTRFS_FS is not set
CONFIG_FILE_LOCKING=y
CONFIG_FSNOTIFY=y
# CONFIG_DNOTIFY is not set
# CONFIG_INOTIFY is not set
CONFIG_INOTIFY_USER=y
# CONFIG_QUOTA is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
@ -678,6 +680,7 @@ CONFIG_DEBUG_INFO=y
# CONFIG_SYSCTL_SYSCALL_CHECK is not set
# CONFIG_PAGE_POISONING is not set
# CONFIG_SAMPLES is not set
# CONFIG_KMEMCHECK is not set
CONFIG_EARLY_PRINTK=y
CONFIG_HEART_BEAT=y
CONFIG_DEBUG_BOOTMEM=y
@ -793,6 +796,5 @@ CONFIG_ZLIB_INFLATE=y
CONFIG_DECOMPRESS_GZIP=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
CONFIG_HAVE_LMB=y
CONFIG_NLATTR=y

91
arch/microblaze/configs/nommu_defconfig
View File

@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.30-rc5
# Mon May 11 09:01:02 2009
# Linux kernel version: 2.6.31-rc6
# Tue Aug 18 10:35:30 2009
#
CONFIG_MICROBLAZE=y
# CONFIG_SWAP is not set
@ -17,9 +17,12 @@ CONFIG_GENERIC_TIME=y
# CONFIG_GENERIC_TIME_VSYSCALL is not set
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
CONFIG_GENERIC_GPIO=y
CONFIG_GENERIC_CSUM=y
# CONFIG_PCI is not set
# CONFIG_NO_DMA is not set
CONFIG_NO_DMA=y
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
CONFIG_CONSTRUCTORS=y
#
# General setup
@ -64,7 +67,6 @@ CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS=y
CONFIG_KALLSYMS_ALL=y
CONFIG_KALLSYMS_EXTRA_PASS=y
# CONFIG_STRIP_ASM_SYMS is not set
# CONFIG_HOTPLUG is not set
CONFIG_PRINTK=y
CONFIG_BUG=y
@ -76,13 +78,23 @@ CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_AIO=y
#
# Performance Counters
#
CONFIG_VM_EVENT_COUNTERS=y
# CONFIG_STRIP_ASM_SYMS is not set
CONFIG_COMPAT_BRK=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
# CONFIG_PROFILING is not set
# CONFIG_MARKERS is not set
#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
# CONFIG_SLOW_WORK is not set
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_SLABINFO=y
@ -95,7 +107,7 @@ CONFIG_MODULE_UNLOAD=y
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_BLOCK=y
# CONFIG_LBD is not set
CONFIG_LBDAF=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_BLK_DEV_INTEGRITY is not set
@ -156,8 +168,16 @@ CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="console=ttyUL0,115200"
# CONFIG_CMDLINE_FORCE is not set
CONFIG_OF=y
CONFIG_OF_DEVICE=y
CONFIG_PROC_DEVICETREE=y
#
# Advanced setup
#
#
# Default settings for advanced configuration options are used
#
CONFIG_KERNEL_START=0x90000000
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
@ -169,7 +189,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_PHYS_ADDR_T_64BIT is not set
CONFIG_ZONE_DMA_FLAG=0
CONFIG_VIRT_TO_BUS=y
CONFIG_UNEVICTABLE_LRU=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_NOMMU_INITIAL_TRIM_EXCESS=1
#
@ -237,6 +257,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
# CONFIG_PHONET is not set
# CONFIG_IEEE802154 is not set
# CONFIG_NET_SCHED is not set
# CONFIG_DCB is not set
@ -254,7 +275,11 @@ CONFIG_WIRELESS=y
CONFIG_WIRELESS_OLD_REGULATORY=y
# CONFIG_WIRELESS_EXT is not set
# CONFIG_LIB80211 is not set
# CONFIG_MAC80211 is not set
#
# CFG80211 needs to be enabled for MAC80211
#
CONFIG_MAC80211_DEFAULT_PS_VALUE=0
# CONFIG_WIMAX is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
@ -353,6 +378,7 @@ CONFIG_MTD_UCLINUX=y
# UBI - Unsorted block images
#
# CONFIG_MTD_UBI is not set
CONFIG_OF_DEVICE=y
# CONFIG_PARPORT is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
@ -364,6 +390,7 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
# CONFIG_BLK_DEV_XIP is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
# CONFIG_XILINX_SYSACE is not set
CONFIG_MISC_DEVICES=y
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_C2PORT is not set
@ -383,7 +410,6 @@ CONFIG_MISC_DEVICES=y
# CONFIG_ATA is not set
# CONFIG_MD is not set
CONFIG_NETDEVICES=y
CONFIG_COMPAT_NET_DEV_OPS=y
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_MACVLAN is not set
@ -402,7 +428,7 @@ CONFIG_NET_ETHERNET=y
# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
# CONFIG_B44 is not set
# CONFIG_KS8842 is not set
CONFIG_NETDEV_1000=y
CONFIG_NETDEV_10000=y
@ -463,23 +489,25 @@ CONFIG_HW_RANDOM=y
# CONFIG_HW_RANDOM_TIMERIOMEM is not set
# CONFIG_RTC is not set
# CONFIG_GEN_RTC is not set
# CONFIG_XILINX_HWICAP is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
# CONFIG_I2C is not set
# CONFIG_SPI is not set
#
# PPS support
#
# CONFIG_PPS is not set
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
# CONFIG_GPIOLIB is not set
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
# CONFIG_THERMAL is not set
# CONFIG_THERMAL_HWMON is not set
# CONFIG_WATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
#
# Sonics Silicon Backplane
#
# CONFIG_SSB is not set
#
# Multifunction device drivers
@ -489,22 +517,7 @@ CONFIG_SSB_POSSIBLE=y
# CONFIG_HTC_PASIC3 is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_REGULATOR is not set
#
# Multimedia devices
#
#
# Multimedia core support
#
# CONFIG_VIDEO_DEV is not set
# CONFIG_DVB_CORE is not set
# CONFIG_VIDEO_MEDIA is not set
#
# Multimedia drivers
#
CONFIG_DAB=y
# CONFIG_MEDIA_SUPPORT is not set
#
# Graphics support
@ -520,9 +533,10 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y
# CONFIG_DISPLAY_SUPPORT is not set
# CONFIG_SOUND is not set
CONFIG_USB_SUPPORT=y
# CONFIG_USB_ARCH_HAS_HCD is not set
CONFIG_USB_ARCH_HAS_HCD=y
# CONFIG_USB_ARCH_HAS_OHCI is not set
# CONFIG_USB_ARCH_HAS_EHCI is not set
# CONFIG_USB is not set
# CONFIG_USB_OTG_WHITELIST is not set
# CONFIG_USB_OTG_BLACKLIST_HUB is not set
@ -543,9 +557,12 @@ CONFIG_USB_SUPPORT=y
# CONFIG_NEW_LEDS is not set
# CONFIG_ACCESSIBILITY is not set
# CONFIG_RTC_CLASS is not set
# CONFIG_DMADEVICES is not set
# CONFIG_AUXDISPLAY is not set
# CONFIG_UIO is not set
#
# TI VLYNQ
#
# CONFIG_STAGING is not set
#
@ -558,12 +575,15 @@ CONFIG_EXT2_FS=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
CONFIG_FS_POSIX_ACL=y
CONFIG_FILE_LOCKING=y
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_BTRFS_FS is not set
CONFIG_FILE_LOCKING=y
CONFIG_FSNOTIFY=y
# CONFIG_DNOTIFY is not set
# CONFIG_INOTIFY is not set
CONFIG_INOTIFY_USER=y
# CONFIG_QUOTA is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
@ -813,6 +833,5 @@ CONFIG_GENERIC_FIND_LAST_BIT=y
CONFIG_ZLIB_INFLATE=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
CONFIG_HAVE_LMB=y
CONFIG_NLATTR=y

3
arch/microblaze/include/asm/device.h
View File

@ -16,6 +16,9 @@ struct dev_archdata {
struct device_node *of_node;
};
struct pdev_archdata {
};
#endif /* _ASM_MICROBLAZE_DEVICE_H */

2
arch/microblaze/include/asm/hardirq.h
View File

@ -12,8 +12,6 @@
/* should be defined in each interrupt controller driver */
extern unsigned int get_irq(struct pt_regs *regs);
#define ack_bad_irq ack_bad_irq
void ack_bad_irq(unsigned int irq);
#include <asm-generic/hardirq.h>
#endif /* _ASM_MICROBLAZE_HARDIRQ_H */

2
arch/microblaze/kernel/intc.c
View File

@ -12,6 +12,7 @@
#include <linux/irq.h>
#include <asm/page.h>
#include <linux/io.h>
#include <linux/bug.h>
#include <asm/prom.h>
#include <asm/irq.h>
@ -130,6 +131,7 @@ void __init init_IRQ(void)
if (intc)
break;
}
BUG_ON(!intc);
intc_baseaddr = *(int *) of_get_property(intc, "reg", NULL);
intc_baseaddr = (unsigned long) ioremap(intc_baseaddr, PAGE_SIZE);

9
arch/microblaze/kernel/irq.c
View File

@ -30,15 +30,6 @@ unsigned int irq_of_parse_and_map(struct device_node *dev, int index)
}
EXPORT_SYMBOL_GPL(irq_of_parse_and_map);
/*
* 'what should we do if we get a hw irq event on an illegal vector'.
* each architecture has to answer this themselves.
*/
void ack_bad_irq(unsigned int irq)
{
printk(KERN_WARNING "unexpected IRQ trap at vector %02x\n", irq);
}
static u32 concurrent_irq;
void do_IRQ(struct pt_regs *regs)

2
arch/microblaze/kernel/syscall_table.S
View File

@ -313,7 +313,7 @@ ENTRY(sys_call_table)
.long sys_fchmodat
.long sys_faccessat
.long sys_ni_syscall /* pselect6 */
.long sys_ni_syscall /* sys_ppoll */
.long sys_ppoll
.long sys_unshare /* 310 */
.long sys_set_robust_list
.long sys_get_robust_list

2
arch/microblaze/kernel/timer.c
View File

@ -22,6 +22,7 @@
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/io.h>
#include <linux/bug.h>
#include <asm/cpuinfo.h>
#include <asm/setup.h>
#include <asm/prom.h>
@ -234,6 +235,7 @@ void __init time_init(void)
if (timer)
break;
}
BUG_ON(!timer);
timer_baseaddr = *(int *) of_get_property(timer, "reg", NULL);
timer_baseaddr = (unsigned long) ioremap(timer_baseaddr, PAGE_SIZE);

6
arch/microblaze/mm/init.c
View File

@ -130,13 +130,13 @@ void __init setup_memory(void)
* (in case the address isn't page-aligned).
*/
#ifndef CONFIG_MMU
map_size = init_bootmem_node(NODE_DATA(0), PFN_UP(TOPHYS((u32)_end)),
map_size = init_bootmem_node(NODE_DATA(0), PFN_UP(TOPHYS((u32)klimit)),
min_low_pfn, max_low_pfn);
#else
map_size = init_bootmem_node(&contig_page_data,
PFN_UP(TOPHYS((u32)_end)), min_low_pfn, max_low_pfn);
PFN_UP(TOPHYS((u32)klimit)), min_low_pfn, max_low_pfn);
#endif
lmb_reserve(PFN_UP(TOPHYS((u32)_end)) << PAGE_SHIFT, map_size);
lmb_reserve(PFN_UP(TOPHYS((u32)klimit)) << PAGE_SHIFT, map_size);
/* free bootmem is whole main memory */
free_bootmem(memory_start, memory_size);

2
arch/mips/include/asm/page.h
View File

@ -32,10 +32,12 @@
#define PAGE_SIZE (1UL << PAGE_SHIFT)
#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1))
#ifdef CONFIG_HUGETLB_PAGE
#define HPAGE_SHIFT (PAGE_SHIFT + PAGE_SHIFT - 3)
#define HPAGE_SIZE ((1UL) << HPAGE_SHIFT)
#define HPAGE_MASK (~(HPAGE_SIZE - 1))
#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
#endif /* CONFIG_HUGETLB_PAGE */
#ifndef __ASSEMBLY__

3
arch/powerpc/include/asm/device.h
View File

@ -30,4 +30,7 @@ dev_archdata_get_node(const struct dev_archdata *ad)
return ad->of_node;
}
struct pdev_archdata {
};
#endif /* _ASM_POWERPC_DEVICE_H */

36
arch/sh/Kconfig
View File

@ -219,6 +219,8 @@ config CPU_SHX3
config ARCH_SHMOBILE
bool
select ARCH_SUSPEND_POSSIBLE
select PM
select PM_RUNTIME
if SUPERH32
@ -396,6 +398,13 @@ config CPU_SUBTYPE_SH7724
help
Select SH7724 if you have an SH-MobileR2R CPU.
config CPU_SUBTYPE_SH7757
bool "Support SH7757 processor"
select CPU_SH4A
select CPU_SHX2
help
Select SH7757 if you have a SH4A SH7757 CPU.
config CPU_SUBTYPE_SH7763
bool "Support SH7763 processor"
select CPU_SH4A
@ -758,12 +767,31 @@ config UBC_WAKEUP
If unsure, say N.
config CMDLINE_BOOL
bool "Default bootloader kernel arguments"
choice
prompt "Kernel command line"
optional
default CMDLINE_OVERWRITE
help
Setting this option allows the kernel command line arguments
to be set.
config CMDLINE_OVERWRITE
bool "Overwrite bootloader kernel arguments"
help
Given string will overwrite any arguments passed in by
a bootloader.
config CMDLINE_EXTEND
bool "Extend bootloader kernel arguments"
help
Given string will be concatenated with arguments passed in
by a bootloader.
endchoice
config CMDLINE
string "Initial kernel command string"
depends on CMDLINE_BOOL
string "Kernel command line arguments string"
depends on CMDLINE_OVERWRITE || CMDLINE_EXTEND
default "console=ttySC1,115200"
endmenu

1
arch/sh/Kconfig.debug
View File

@ -38,6 +38,7 @@ config EARLY_SCIF_CONSOLE_PORT
default "0xffe00000" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7763 || \
CPU_SUBTYPE_SH7722 || CPU_SUBTYPE_SH7366 || \
CPU_SUBTYPE_SH7343
default "0xfe4c0000" if CPU_SUBTYPE_SH7757
default "0xffeb0000" if CPU_SUBTYPE_SH7785
default "0xffeb0000" if CPU_SUBTYPE_SH7786
default "0xfffe8000" if CPU_SUBTYPE_SH7203

1
arch/sh/Makefile
View File

@ -137,6 +137,7 @@ machdir-$(CONFIG_SH_EDOSK7705) += mach-edosk7705
machdir-$(CONFIG_SH_HIGHLANDER) += mach-highlander
machdir-$(CONFIG_SH_MIGOR) += mach-migor
machdir-$(CONFIG_SH_KFR2R09) += mach-kfr2r09
machdir-$(CONFIG_SH_ECOVEC) += mach-ecovec24
machdir-$(CONFIG_SH_SDK7780) += mach-sdk7780
machdir-$(CONFIG_SH_X3PROTO) += mach-x3proto
machdir-$(CONFIG_SH_SH7763RDP) += mach-sh7763rdp

14
arch/sh/boards/Kconfig
View File

@ -171,6 +171,13 @@ config SH_SH7785LCR_29BIT_PHYSMAPS
DIP switch(S2-5). If you set the DIP switch for S2-5 = ON,
you can access all on-board device in 29bit address mode.
config SH_SH7785LCR_PT
bool "SH7785LCR prototype board on 32-bit MMU mode"
depends on SH_SH7785LCR && 32BIT
default n
help
If you use prototype board, this option is enabled.
config SH_URQUELL
bool "Urquell"
depends on CPU_SUBTYPE_SH7786
@ -200,6 +207,13 @@ config SH_KFR2R09
help
"Kit For R2R for 2009" support.
config SH_ECOVEC
bool "EcoVec"
depends on CPU_SUBTYPE_SH7724
select ARCH_REQUIRE_GPIOLIB
help
Renesas "R0P7724LC0011/21RL (EcoVec)" support.
config SH_SH7763RDP
bool "SH7763RDP"
depends on CPU_SUBTYPE_SH7763

6
arch/sh/boards/board-ap325rxa.c
View File

@ -227,6 +227,9 @@ static struct platform_device lcdc_device = {
.dev = {
.platform_data = &lcdc_info,
},
.archdata = {
.hwblk_id = HWBLK_LCDC,
},
};
static void camera_power(int val)
@ -377,6 +380,9 @@ static struct platform_device ceu_device = {
.dev = {
.platform_data = &sh_mobile_ceu_info,
},
.archdata = {
.hwblk_id = HWBLK_CEU,
},
};
struct spi_gpio_platform_data sdcard_cn3_platform_data = {

18
arch/sh/boards/board-sh7785lcr.c
View File

@ -223,6 +223,19 @@ static struct platform_device sm501_device = {
.resource = sm501_resources,
};
static struct resource i2c_proto_resources[] = {
[0] = {
.start = PCA9564_PROTO_32BIT_ADDR,
.end = PCA9564_PROTO_32BIT_ADDR + PCA9564_SIZE - 1,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
},
[1] = {
.start = 12,
.end = 12,
.flags = IORESOURCE_IRQ,
},
};
static struct resource i2c_resources[] = {
[0] = {
.start = PCA9564_ADDR,
@ -271,6 +284,11 @@ static int __init sh7785lcr_devices_setup(void)
i2c_register_board_info(0, sh7785lcr_i2c_devices,
ARRAY_SIZE(sh7785lcr_i2c_devices));
if (mach_is_sh7785lcr_pt()) {
i2c_device.resource = &i2c_proto_resources;
i2c_device.num_resources = ARRAY_SIZE(i2c_proto_resources);
}
return platform_add_devices(sh7785lcr_devices,
ARRAY_SIZE(sh7785lcr_devices));
}

9
arch/sh/boards/mach-ecovec24/Makefile Normal file
View File

@ -0,0 +1,9 @@
#
# Makefile for the R0P7724LC0011/21RL (EcoVec)
#
# This file is subject to the terms and conditions of the GNU General Public
# License. See the file "COPYING" in the main directory of this archive
# for more details.
#
obj-y := setup.o

516
arch/sh/boards/mach-ecovec24/setup.c Normal file
View File

@ -0,0 +1,516 @@
/*
* Copyright (C) 2009 Renesas Solutions Corp.
*
* Kuninori Morimoto <morimoto.kuninori@renesas.com>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/usb/r8a66597.h>
#include <video/sh_mobile_lcdc.h>
#include <media/sh_mobile_ceu.h>
#include <asm/heartbeat.h>
#include <asm/sh_eth.h>
#include <cpu/sh7724.h>
/*
* Address Interface BusWidth
*-----------------------------------------
* 0x0000_0000 uboot 16bit
* 0x0004_0000 Linux romImage 16bit
* 0x0014_0000 MTD for Linux 16bit
* 0x0400_0000 Internal I/O 16/32bit
* 0x0800_0000 DRAM 32bit
* 0x1800_0000 MFI 16bit
*/
/* Heartbeat */
static unsigned char led_pos[] = { 0, 1, 2, 3 };
static struct heartbeat_data heartbeat_data = {
.regsize = 8,
.nr_bits = 4,
.bit_pos = led_pos,
};
static struct resource heartbeat_resources[] = {
[0] = {
.start = 0xA405012C, /* PTG */
.end = 0xA405012E - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.dev = {
.platform_data = &heartbeat_data,
},
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
};
/* MTD */
static struct mtd_partition nor_flash_partitions[] = {
{
.name = "boot loader",
.offset = 0,
.size = (5 * 1024 * 1024),
.mask_flags = MTD_CAP_ROM,
}, {
.name = "free-area",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
},
};
static struct physmap_flash_data nor_flash_data = {
.width = 2,
.parts = nor_flash_partitions,
.nr_parts = ARRAY_SIZE(nor_flash_partitions),
};
static struct resource nor_flash_resources[] = {
[0] = {
.name = "NOR Flash",
.start = 0x00000000,
.end = 0x03ffffff,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device nor_flash_device = {
.name = "physmap-flash",
.resource = nor_flash_resources,
.num_resources = ARRAY_SIZE(nor_flash_resources),
.dev = {
.platform_data = &nor_flash_data,
},
};
/* SH Eth */
#define SH_ETH_ADDR (0xA4600000)
#define SH_ETH_MAHR (SH_ETH_ADDR + 0x1C0)
#define SH_ETH_MALR (SH_ETH_ADDR + 0x1C8)
static struct resource sh_eth_resources[] = {
[0] = {
.start = SH_ETH_ADDR,
.end = SH_ETH_ADDR + 0x1FC,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 91,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
},
};
struct sh_eth_plat_data sh_eth_plat = {
.phy = 0x1f, /* SMSC LAN8700 */
.edmac_endian = EDMAC_LITTLE_ENDIAN,
};
static struct platform_device sh_eth_device = {
.name = "sh-eth",
.id = 0,
.dev = {
.platform_data = &sh_eth_plat,
},
.num_resources = ARRAY_SIZE(sh_eth_resources),
.resource = sh_eth_resources,
};
/* USB0 host */
void usb0_port_power(int port, int power)
{
gpio_set_value(GPIO_PTB4, power);
}
static struct r8a66597_platdata usb0_host_data = {
.on_chip = 1,
.port_power = usb0_port_power,
};
static struct resource usb0_host_resources[] = {
[0] = {
.start = 0xa4d80000,
.end = 0xa4d80124 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 65,
.end = 65,
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
},
};
static struct platform_device usb0_host_device = {
.name = "r8a66597_hcd",
.id = 0,
.dev = {
.dma_mask = NULL, /* not use dma */
.coherent_dma_mask = 0xffffffff,
.platform_data = &usb0_host_data,
},
.num_resources = ARRAY_SIZE(usb0_host_resources),
.resource = usb0_host_resources,
};
/*
* USB1
*
* CN5 can use both host/function,
* and we can determine it by checking PTB[3]
*
* This time only USB1 host is supported.
*/
void usb1_port_power(int port, int power)
{
if (!gpio_get_value(GPIO_PTB3)) {
printk(KERN_ERR "USB1 function is not supported\n");
return;
}
gpio_set_value(GPIO_PTB5, power);
}
static struct r8a66597_platdata usb1_host_data = {
.on_chip = 1,
.port_power = usb1_port_power,
};
static struct resource usb1_host_resources[] = {
[0] = {
.start = 0xa4d90000,
.end = 0xa4d90124 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 66,
.end = 66,
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
},
};
static struct platform_device usb1_host_device = {
.name = "r8a66597_hcd",
.id = 1,
.dev = {
.dma_mask = NULL, /* not use dma */
.coherent_dma_mask = 0xffffffff,
.platform_data = &usb1_host_data,
},
.num_resources = ARRAY_SIZE(usb1_host_resources),
.resource = usb1_host_resources,
};
/* LCDC */
static struct sh_mobile_lcdc_info lcdc_info = {
.ch[0] = {
.interface_type = RGB18,
.chan = LCDC_CHAN_MAINLCD,
.bpp = 16,
.lcd_cfg = {
.sync = 0, /* hsync and vsync are active low */
},
.lcd_size_cfg = { /* 7.0 inch */
.width = 152,
.height = 91,
},
.board_cfg = {
},
}
};
static struct resource lcdc_resources[] = {
[0] = {
.name = "LCDC",
.start = 0xfe940000,
.end = 0xfe941fff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 106,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device lcdc_device = {
.name = "sh_mobile_lcdc_fb",
.num_resources = ARRAY_SIZE(lcdc_resources),
.resource = lcdc_resources,
.dev = {
.platform_data = &lcdc_info,
},
.archdata = {
.hwblk_id = HWBLK_LCDC,
},
};
/* CEU0 */
static struct sh_mobile_ceu_info sh_mobile_ceu0_info = {
.flags = SH_CEU_FLAG_USE_8BIT_BUS,
};
static struct resource ceu0_resources[] = {
[0] = {
.name = "CEU0",
.start = 0xfe910000,
.end = 0xfe91009f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 52,
.flags = IORESOURCE_IRQ,
},
[2] = {
/* place holder for contiguous memory */
},
};
static struct platform_device ceu0_device = {
.name = "sh_mobile_ceu",
.id = 0, /* "ceu0" clock */
.num_resources = ARRAY_SIZE(ceu0_resources),
.resource = ceu0_resources,
.dev = {
.platform_data = &sh_mobile_ceu0_info,
},
.archdata = {
.hwblk_id = HWBLK_CEU0,
},
};
/* CEU1 */
static struct sh_mobile_ceu_info sh_mobile_ceu1_info = {
.flags = SH_CEU_FLAG_USE_8BIT_BUS,
};
static struct resource ceu1_resources[] = {
[0] = {
.name = "CEU1",
.start = 0xfe914000,
.end = 0xfe91409f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 63,
.flags = IORESOURCE_IRQ,
},
[2] = {
/* place holder for contiguous memory */
},
};
static struct platform_device ceu1_device = {
.name = "sh_mobile_ceu",
.id = 1, /* "ceu1" clock */
.num_resources = ARRAY_SIZE(ceu1_resources),
.resource = ceu1_resources,
.dev = {
.platform_data = &sh_mobile_ceu1_info,
},
.archdata = {
.hwblk_id = HWBLK_CEU1,
},
};
static struct platform_device *ecovec_devices[] __initdata = {
&heartbeat_device,
&nor_flash_device,
&sh_eth_device,
&usb0_host_device,
&usb1_host_device, /* USB1 host support */
&lcdc_device,
&ceu0_device,
&ceu1_device,
};
#define PORT_HIZA 0xA4050158
#define IODRIVEA 0xA405018A
static int __init devices_setup(void)
{
/* enable SCIFA0 */
gpio_request(GPIO_FN_SCIF0_TXD, NULL);
gpio_request(GPIO_FN_SCIF0_RXD, NULL);
/* enable debug LED */
gpio_request(GPIO_PTG0, NULL);
gpio_request(GPIO_PTG1, NULL);
gpio_request(GPIO_PTG2, NULL);
gpio_request(GPIO_PTG3, NULL);
gpio_direction_output(GPIO_PTG0, 0);
gpio_direction_output(GPIO_PTG1, 0);
gpio_direction_output(GPIO_PTG2, 0);
gpio_direction_output(GPIO_PTG3, 0);
/* enable SH-Eth */
gpio_request(GPIO_PTA1, NULL);
gpio_direction_output(GPIO_PTA1, 1);
mdelay(20);
gpio_request(GPIO_FN_RMII_RXD0, NULL);
gpio_request(GPIO_FN_RMII_RXD1, NULL);
gpio_request(GPIO_FN_RMII_TXD0, NULL);
gpio_request(GPIO_FN_RMII_TXD1, NULL);
gpio_request(GPIO_FN_RMII_REF_CLK, NULL);
gpio_request(GPIO_FN_RMII_TX_EN, NULL);
gpio_request(GPIO_FN_RMII_RX_ER, NULL);
gpio_request(GPIO_FN_RMII_CRS_DV, NULL);
gpio_request(GPIO_FN_MDIO, NULL);
gpio_request(GPIO_FN_MDC, NULL);
gpio_request(GPIO_FN_LNKSTA, NULL);
/* enable USB */
gpio_request(GPIO_PTB3, NULL);
gpio_request(GPIO_PTB4, NULL);
gpio_request(GPIO_PTB5, NULL);
gpio_direction_input(GPIO_PTB3);
gpio_direction_output(GPIO_PTB4, 0);
gpio_direction_output(GPIO_PTB5, 0);
ctrl_outw(0x0600, 0xa40501d4);
ctrl_outw(0x0600, 0xa4050192);
/* enable LCDC */
gpio_request(GPIO_FN_LCDD23, NULL);
gpio_request(GPIO_FN_LCDD22, NULL);
gpio_request(GPIO_FN_LCDD21, NULL);
gpio_request(GPIO_FN_LCDD20, NULL);
gpio_request(GPIO_FN_LCDD19, NULL);
gpio_request(GPIO_FN_LCDD18, NULL);
gpio_request(GPIO_FN_LCDD17, NULL);
gpio_request(GPIO_FN_LCDD16, NULL);
gpio_request(GPIO_FN_LCDD15, NULL);
gpio_request(GPIO_FN_LCDD14, NULL);
gpio_request(GPIO_FN_LCDD13, NULL);
gpio_request(GPIO_FN_LCDD12, NULL);
gpio_request(GPIO_FN_LCDD11, NULL);
gpio_request(GPIO_FN_LCDD10, NULL);
gpio_request(GPIO_FN_LCDD9, NULL);
gpio_request(GPIO_FN_LCDD8, NULL);
gpio_request(GPIO_FN_LCDD7, NULL);
gpio_request(GPIO_FN_LCDD6, NULL);
gpio_request(GPIO_FN_LCDD5, NULL);
gpio_request(GPIO_FN_LCDD4, NULL);
gpio_request(GPIO_FN_LCDD3, NULL);
gpio_request(GPIO_FN_LCDD2, NULL);
gpio_request(GPIO_FN_LCDD1, NULL);
gpio_request(GPIO_FN_LCDD0, NULL);
gpio_request(GPIO_FN_LCDDISP, NULL);
gpio_request(GPIO_FN_LCDHSYN, NULL);
gpio_request(GPIO_FN_LCDDCK, NULL);
gpio_request(GPIO_FN_LCDVSYN, NULL);
gpio_request(GPIO_FN_LCDDON, NULL);
gpio_request(GPIO_FN_LCDLCLK, NULL);
ctrl_outw((ctrl_inw(PORT_HIZA) & ~0x0001), PORT_HIZA);
gpio_request(GPIO_PTE6, NULL);
gpio_request(GPIO_PTU1, NULL);
gpio_request(GPIO_PTR1, NULL);
gpio_request(GPIO_PTA2, NULL);
gpio_direction_input(GPIO_PTE6);
gpio_direction_output(GPIO_PTU1, 0);
gpio_direction_output(GPIO_PTR1, 0);
gpio_direction_output(GPIO_PTA2, 0);
/* I/O buffer drive ability is low */
ctrl_outw((ctrl_inw(IODRIVEA) & ~0x00c0) | 0x0040 , IODRIVEA);
if (gpio_get_value(GPIO_PTE6)) {
/* DVI */
lcdc_info.clock_source = LCDC_CLK_EXTERNAL;
lcdc_info.ch[0].clock_divider = 1,
lcdc_info.ch[0].lcd_cfg.name = "DVI";
lcdc_info.ch[0].lcd_cfg.xres = 1280;
lcdc_info.ch[0].lcd_cfg.yres = 720;
lcdc_info.ch[0].lcd_cfg.left_margin = 220;
lcdc_info.ch[0].lcd_cfg.right_margin = 110;
lcdc_info.ch[0].lcd_cfg.hsync_len = 40;
lcdc_info.ch[0].lcd_cfg.upper_margin = 20;
lcdc_info.ch[0].lcd_cfg.lower_margin = 5;
lcdc_info.ch[0].lcd_cfg.vsync_len = 5;
gpio_set_value(GPIO_PTA2, 1);
gpio_set_value(GPIO_PTU1, 1);
} else {
/* Panel */
lcdc_info.clock_source = LCDC_CLK_PERIPHERAL;
lcdc_info.ch[0].clock_divider = 2,
lcdc_info.ch[0].lcd_cfg.name = "Panel";
lcdc_info.ch[0].lcd_cfg.xres = 800;
lcdc_info.ch[0].lcd_cfg.yres = 480;
lcdc_info.ch[0].lcd_cfg.left_margin = 220;
lcdc_info.ch[0].lcd_cfg.right_margin = 110;
lcdc_info.ch[0].lcd_cfg.hsync_len = 70;
lcdc_info.ch[0].lcd_cfg.upper_margin = 20;
lcdc_info.ch[0].lcd_cfg.lower_margin = 5;
lcdc_info.ch[0].lcd_cfg.vsync_len = 5;
gpio_set_value(GPIO_PTR1, 1);
/* FIXME
*
* LCDDON control is needed for Panel,
* but current sh_mobile_lcdc driver doesn't control it.
* It is temporary correspondence
*/
gpio_request(GPIO_PTF4, NULL);
gpio_direction_output(GPIO_PTF4, 1);
}
/* enable CEU0 */
gpio_request(GPIO_FN_VIO0_D15, NULL);
gpio_request(GPIO_FN_VIO0_D14, NULL);
gpio_request(GPIO_FN_VIO0_D13, NULL);
gpio_request(GPIO_FN_VIO0_D12, NULL);
gpio_request(GPIO_FN_VIO0_D11, NULL);
gpio_request(GPIO_FN_VIO0_D10, NULL);
gpio_request(GPIO_FN_VIO0_D9, NULL);
gpio_request(GPIO_FN_VIO0_D8, NULL);
gpio_request(GPIO_FN_VIO0_D7, NULL);
gpio_request(GPIO_FN_VIO0_D6, NULL);
gpio_request(GPIO_FN_VIO0_D5, NULL);
gpio_request(GPIO_FN_VIO0_D4, NULL);
gpio_request(GPIO_FN_VIO0_D3, NULL);
gpio_request(GPIO_FN_VIO0_D2, NULL);
gpio_request(GPIO_FN_VIO0_D1, NULL);
gpio_request(GPIO_FN_VIO0_D0, NULL);
gpio_request(GPIO_FN_VIO0_VD, NULL);
gpio_request(GPIO_FN_VIO0_CLK, NULL);
gpio_request(GPIO_FN_VIO0_FLD, NULL);
gpio_request(GPIO_FN_VIO0_HD, NULL);
platform_resource_setup_memory(&ceu0_device, "ceu0", 4 << 20);
/* enable CEU1 */
gpio_request(GPIO_FN_VIO1_D7, NULL);
gpio_request(GPIO_FN_VIO1_D6, NULL);
gpio_request(GPIO_FN_VIO1_D5, NULL);
gpio_request(GPIO_FN_VIO1_D4, NULL);
gpio_request(GPIO_FN_VIO1_D3, NULL);
gpio_request(GPIO_FN_VIO1_D2, NULL);
gpio_request(GPIO_FN_VIO1_D1, NULL);
gpio_request(GPIO_FN_VIO1_D0, NULL);
gpio_request(GPIO_FN_VIO1_FLD, NULL);
gpio_request(GPIO_FN_VIO1_HD, NULL);
gpio_request(GPIO_FN_VIO1_VD, NULL);
gpio_request(GPIO_FN_VIO1_CLK, NULL);
platform_resource_setup_memory(&ceu1_device, "ceu1", 4 << 20);
return platform_add_devices(ecovec_devices,
ARRAY_SIZE(ecovec_devices));
}
device_initcall(devices_setup);
static struct sh_machine_vector mv_ecovec __initmv = {
.mv_name = "R0P7724 (EcoVec)",
};

116
arch/sh/boards/mach-kfr2r09/setup.c
View File

@ -16,6 +16,8 @@
#include <linux/clk.h>
#include <linux/gpio.h>
#include <linux/input.h>
#include <linux/i2c.h>
#include <linux/usb/r8a66597.h>
#include <video/sh_mobile_lcdc.h>
#include <asm/clock.h>
#include <asm/machvec.h>
@ -113,6 +115,9 @@ static struct platform_device kfr2r09_sh_keysc_device = {
.dev = {
.platform_data = &kfr2r09_sh_keysc_info,
},
.archdata = {
.hwblk_id = HWBLK_KEYSC,
},
};
static struct sh_mobile_lcdc_info kfr2r09_sh_lcdc_info = {
@ -173,6 +178,38 @@ static struct platform_device kfr2r09_sh_lcdc_device = {
.dev = {
.platform_data = &kfr2r09_sh_lcdc_info,
},
.archdata = {
.hwblk_id = HWBLK_LCDC,
},
};
static struct r8a66597_platdata kfr2r09_usb0_gadget_data = {
.on_chip = 1,
};
static struct resource kfr2r09_usb0_gadget_resources[] = {
[0] = {
.start = 0x04d80000,
.end = 0x04d80123,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 65,
.end = 65,
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
},
};
static struct platform_device kfr2r09_usb0_gadget_device = {
.name = "r8a66597_udc",
.id = 0,
.dev = {
.dma_mask = NULL, /* not use dma */
.coherent_dma_mask = 0xffffffff,
.platform_data = &kfr2r09_usb0_gadget_data,
},
.num_resources = ARRAY_SIZE(kfr2r09_usb0_gadget_resources),
.resource = kfr2r09_usb0_gadget_resources,
};
static struct platform_device *kfr2r09_devices[] __initdata = {
@ -186,6 +223,81 @@ static struct platform_device *kfr2r09_devices[] __initdata = {
#define BSC_CS0WCR 0xfec10024
#define BSC_CS4BCR 0xfec10010
#define BSC_CS4WCR 0xfec10030
#define PORT_MSELCRB 0xa4050182
#ifdef CONFIG_I2C
static int kfr2r09_usb0_gadget_i2c_setup(void)
{
struct i2c_adapter *a;
struct i2c_msg msg;
unsigned char buf[2];
int ret;
a = i2c_get_adapter(0);
if (!a)
return -ENODEV;
/* set bit 1 (the second bit) of chip at 0x09, register 0x13 */
buf[0] = 0x13;
msg.addr = 0x09;
msg.buf = buf;
msg.len = 1;
msg.flags = 0;
ret = i2c_transfer(a, &msg, 1);
if (ret != 1)
return -ENODEV;
buf[0] = 0;
msg.addr = 0x09;
msg.buf = buf;
msg.len = 1;
msg.flags = I2C_M_RD;
ret = i2c_transfer(a, &msg, 1);
if (ret != 1)
return -ENODEV;
buf[1] = buf[0] | (1 << 1);
buf[0] = 0x13;
msg.addr = 0x09;
msg.buf = buf;
msg.len = 2;
msg.flags = 0;
ret = i2c_transfer(a, &msg, 1);
if (ret != 1)
return -ENODEV;
return 0;
}
#else
static int kfr2r09_usb0_gadget_i2c_setup(void)
{
return -ENODEV;
}
#endif
static int kfr2r09_usb0_gadget_setup(void)
{
int plugged_in;
gpio_request(GPIO_PTN4, NULL); /* USB_DET */
gpio_direction_input(GPIO_PTN4);
plugged_in = gpio_get_value(GPIO_PTN4);
if (!plugged_in)
return -ENODEV; /* no cable plugged in */
if (kfr2r09_usb0_gadget_i2c_setup() != 0)
return -ENODEV; /* unable to configure using i2c */
ctrl_outw((ctrl_inw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB);
gpio_request(GPIO_FN_PDSTATUS, NULL); /* R-standby disables USB clock */
gpio_request(GPIO_PTV6, NULL); /* USBCLK_ON */
gpio_direction_output(GPIO_PTV6, 1); /* USBCLK_ON = H */
msleep(20); /* wait 20ms to let the clock settle */
clk_enable(clk_get(NULL, "usb0"));
ctrl_outw(0x0600, 0xa40501d4);
return 0;
}
static int __init kfr2r09_devices_setup(void)
{
@ -245,6 +357,10 @@ static int __init kfr2r09_devices_setup(void)
gpio_request(GPIO_PTU0, NULL); /* LEDSTDBY/ */
gpio_direction_output(GPIO_PTU0, 1);
/* setup USB function */
if (kfr2r09_usb0_gadget_setup() == 0)
platform_device_register(&kfr2r09_usb0_gadget_device);
return platform_add_devices(kfr2r09_devices,
ARRAY_SIZE(kfr2r09_devices));
}

9
arch/sh/boards/mach-migor/setup.c
View File

@ -98,6 +98,9 @@ static struct platform_device sh_keysc_device = {
.dev = {
.platform_data = &sh_keysc_info,
},
.archdata = {
.hwblk_id = HWBLK_KEYSC,
},
};
static struct mtd_partition migor_nor_flash_partitions[] =
@ -292,6 +295,9 @@ static struct platform_device migor_lcdc_device = {
.dev = {
.platform_data = &sh_mobile_lcdc_info,
},
.archdata = {
.hwblk_id = HWBLK_LCDC,
},
};
static struct clk *camera_clk;
@ -379,6 +385,9 @@ static struct platform_device migor_ceu_device = {
.dev = {
.platform_data = &sh_mobile_ceu_info,
},
.archdata = {
.hwblk_id = HWBLK_CEU,
},
};
struct spi_gpio_platform_data sdcard_cn9_platform_data = {

4
arch/sh/boards/mach-se/7722/setup.c
View File

@ -22,6 +22,7 @@
#include <asm/io.h>
#include <asm/heartbeat.h>
#include <asm/sh_keysc.h>
#include <cpu/sh7722.h>
/* Heartbeat */
static struct heartbeat_data heartbeat_data = {
@ -137,6 +138,9 @@ static struct platform_device sh_keysc_device = {
.dev = {
.platform_data = &sh_keysc_info,
},
.archdata = {
.hwblk_id = HWBLK_KEYSC,
},
};
static struct platform_device *se7722_devices[] __initdata = {

53
arch/sh/boards/mach-se/7724/setup.c
View File

@ -182,6 +182,9 @@ static struct platform_device lcdc_device = {
.dev = {
.platform_data = &lcdc_info,
},
.archdata = {
.hwblk_id = HWBLK_LCDC,
},
};
/* CEU0 */
@ -213,6 +216,9 @@ static struct platform_device ceu0_device = {
.dev = {
.platform_data = &sh_mobile_ceu0_info,
},
.archdata = {
.hwblk_id = HWBLK_CEU0,
},
};
/* CEU1 */
@ -244,6 +250,9 @@ static struct platform_device ceu1_device = {
.dev = {
.platform_data = &sh_mobile_ceu1_info,
},
.archdata = {
.hwblk_id = HWBLK_CEU1,
},
};
/* KEYSC in SoC (Needs SW33-2 set to ON) */
@ -282,6 +291,9 @@ static struct platform_device keysc_device = {
.dev = {
.platform_data = &keysc_info,
},
.archdata = {
.hwblk_id = HWBLK_KEYSC,
},
};
/* SH Eth */
@ -310,6 +322,9 @@ static struct platform_device sh_eth_device = {
},
.num_resources = ARRAY_SIZE(sh_eth_resources),
.resource = sh_eth_resources,
.archdata = {
.hwblk_id = HWBLK_ETHER,
},
};
static struct r8a66597_platdata sh7724_usb0_host_data = {
@ -319,7 +334,7 @@ static struct r8a66597_platdata sh7724_usb0_host_data = {
static struct resource sh7724_usb0_host_resources[] = {
[0] = {
.start = 0xa4d80000,
.end = 0xa4d800ff,
.end = 0xa4d80124 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
@ -339,6 +354,38 @@ static struct platform_device sh7724_usb0_host_device = {
},
.num_resources = ARRAY_SIZE(sh7724_usb0_host_resources),
.resource = sh7724_usb0_host_resources,
.archdata = {
.hwblk_id = HWBLK_USB0,
},
};
static struct r8a66597_platdata sh7724_usb1_gadget_data = {
.on_chip = 1,
};
static struct resource sh7724_usb1_gadget_resources[] = {
[0] = {
.start = 0xa4d90000,
.end = 0xa4d90123,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 66,
.end = 66,
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
},
};
static struct platform_device sh7724_usb1_gadget_device = {
.name = "r8a66597_udc",
.id = 1, /* USB1 */
.dev = {
.dma_mask = NULL, /* not use dma */
.coherent_dma_mask = 0xffffffff,
.platform_data = &sh7724_usb1_gadget_data,
},
.num_resources = ARRAY_SIZE(sh7724_usb1_gadget_resources),
.resource = sh7724_usb1_gadget_resources,
};
static struct platform_device *ms7724se_devices[] __initdata = {
@ -351,6 +398,7 @@ static struct platform_device *ms7724se_devices[] __initdata = {
&keysc_device,
&sh_eth_device,
&sh7724_usb0_host_device,
&sh7724_usb1_gadget_device,
};
#define EEPROM_OP 0xBA206000
@ -459,6 +507,9 @@ static int __init devices_setup(void)
/* enable USB0 port */
ctrl_outw(0x0600, 0xa40501d4);
/* enable USB1 port */
ctrl_outw(0x0600, 0xa4050192);
/* enable IRQ 0,1,2 */
gpio_request(GPIO_FN_INTC_IRQ0, NULL);
gpio_request(GPIO_FN_INTC_IRQ1, NULL);

2
arch/sh/boot/compressed/head_32.S
View File

@ -22,7 +22,7 @@ startup:
bt clear_bss
sub r0, r2
mov.l bss_start_addr, r0
mov #0xe0, r1
mov #0xffffffe0, r1
and r1, r0 ! align cache line
mov.l text_start_addr, r3
mov r0, r1

1558
arch/sh/configs/ecovec24_defconfig Normal file
View File

File diff suppressed because it is too large Load Diff

774
arch/sh/configs/kfr2r09-romimage_defconfig Normal file
View File

@ -0,0 +1,774 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.31-rc6
# Thu Aug 20 15:09:16 2009
#
CONFIG_SUPERH=y
CONFIG_SUPERH32=y
# CONFIG_SUPERH64 is not set
CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_IRQ_PER_CPU=y
CONFIG_GENERIC_GPIO=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_SYS_SUPPORTS_CMT=y
CONFIG_SYS_SUPPORTS_TMU=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_ARCH_NO_VIRT_TO_BUS=y
CONFIG_ARCH_HAS_DEFAULT_IDLE=y
CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
CONFIG_CONSTRUCTORS=y
#
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_HAVE_KERNEL_GZIP=y
CONFIG_HAVE_KERNEL_BZIP2=y
CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_BZIP2 is not set
# CONFIG_KERNEL_LZMA is not set
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
CONFIG_BSD_PROCESS_ACCT=y
# CONFIG_BSD_PROCESS_ACCT_V3 is not set
# CONFIG_TASKSTATS is not set
# CONFIG_AUDIT is not set
#
# RCU Subsystem
#
CONFIG_CLASSIC_RCU=y
# CONFIG_TREE_RCU is not set
# CONFIG_PREEMPT_RCU is not set
# CONFIG_TREE_RCU_TRACE is not set
# CONFIG_PREEMPT_RCU_TRACE is not set
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_GROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
# CONFIG_RT_GROUP_SCHED is not set
CONFIG_USER_SCHED=y
# CONFIG_CGROUP_SCHED is not set
# CONFIG_CGROUPS is not set
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_RELAY is not set
# CONFIG_NAMESPACES is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_INITRAMFS_ROOT_UID=0
CONFIG_INITRAMFS_ROOT_GID=0
CONFIG_RD_GZIP=y
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_LZMA is not set
# CONFIG_INITRAMFS_COMPRESSION_NONE is not set
CONFIG_INITRAMFS_COMPRESSION_GZIP=y
# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set
# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
CONFIG_EMBEDDED=y
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
# CONFIG_KALLSYMS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_HAVE_PERF_COUNTERS=y
#
# Performance Counters
#
# CONFIG_PERF_COUNTERS is not set
CONFIG_VM_EVENT_COUNTERS=y
# CONFIG_STRIP_ASM_SYMS is not set
CONFIG_COMPAT_BRK=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
# CONFIG_PROFILING is not set
# CONFIG_MARKERS is not set
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_IOREMAP_PROT=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_DMA_API_DEBUG=y
#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
# CONFIG_SLOW_WORK is not set
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
# CONFIG_MODULES is not set
# CONFIG_BLOCK is not set
# CONFIG_FREEZER is not set
#
# System type
#
CONFIG_CPU_SH4=y
CONFIG_CPU_SH4A=y
CONFIG_CPU_SHX2=y
CONFIG_ARCH_SHMOBILE=y
# CONFIG_CPU_SUBTYPE_SH7619 is not set
# CONFIG_CPU_SUBTYPE_SH7201 is not set
# CONFIG_CPU_SUBTYPE_SH7203 is not set
# CONFIG_CPU_SUBTYPE_SH7206 is not set
# CONFIG_CPU_SUBTYPE_SH7263 is not set
# CONFIG_CPU_SUBTYPE_MXG is not set
# CONFIG_CPU_SUBTYPE_SH7705 is not set
# CONFIG_CPU_SUBTYPE_SH7706 is not set
# CONFIG_CPU_SUBTYPE_SH7707 is not set
# CONFIG_CPU_SUBTYPE_SH7708 is not set
# CONFIG_CPU_SUBTYPE_SH7709 is not set
# CONFIG_CPU_SUBTYPE_SH7710 is not set
# CONFIG_CPU_SUBTYPE_SH7712 is not set
# CONFIG_CPU_SUBTYPE_SH7720 is not set
# CONFIG_CPU_SUBTYPE_SH7721 is not set
# CONFIG_CPU_SUBTYPE_SH7750 is not set
# CONFIG_CPU_SUBTYPE_SH7091 is not set
# CONFIG_CPU_SUBTYPE_SH7750R is not set
# CONFIG_CPU_SUBTYPE_SH7750S is not set
# CONFIG_CPU_SUBTYPE_SH7751 is not set
# CONFIG_CPU_SUBTYPE_SH7751R is not set
# CONFIG_CPU_SUBTYPE_SH7760 is not set
# CONFIG_CPU_SUBTYPE_SH4_202 is not set
# CONFIG_CPU_SUBTYPE_SH7723 is not set
CONFIG_CPU_SUBTYPE_SH7724=y
# CONFIG_CPU_SUBTYPE_SH7763 is not set
# CONFIG_CPU_SUBTYPE_SH7770 is not set
# CONFIG_CPU_SUBTYPE_SH7780 is not set
# CONFIG_CPU_SUBTYPE_SH7785 is not set
# CONFIG_CPU_SUBTYPE_SH7786 is not set
# CONFIG_CPU_SUBTYPE_SHX3 is not set
# CONFIG_CPU_SUBTYPE_SH7343 is not set
# CONFIG_CPU_SUBTYPE_SH7722 is not set
# CONFIG_CPU_SUBTYPE_SH7366 is not set
#
# Memory management options
#
CONFIG_QUICKLIST=y
CONFIG_MMU=y
CONFIG_PAGE_OFFSET=0x80000000
CONFIG_FORCE_MAX_ZONEORDER=11
CONFIG_MEMORY_START=0x08000000
CONFIG_MEMORY_SIZE=0x08000000
CONFIG_29BIT=y
# CONFIG_X2TLB is not set
CONFIG_VSYSCALL=y
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SPARSEMEM_DEFAULT=y
CONFIG_MAX_ACTIVE_REGIONS=1
CONFIG_ARCH_POPULATES_NODE_MAP=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_PAGE_SIZE_4KB=y
# CONFIG_PAGE_SIZE_8KB is not set
# CONFIG_PAGE_SIZE_16KB is not set
# CONFIG_PAGE_SIZE_64KB is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_SPARSEMEM_STATIC=y
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_PHYS_ADDR_T_64BIT is not set
CONFIG_ZONE_DMA_FLAG=0
CONFIG_NR_QUICK=2
CONFIG_HAVE_MLOCK=y
CONFIG_HAVE_MLOCKED_PAGE_BIT=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
#
# Cache configuration
#
CONFIG_CACHE_WRITEBACK=y
# CONFIG_CACHE_WRITETHROUGH is not set
# CONFIG_CACHE_OFF is not set
#
# Processor features
#
CONFIG_CPU_LITTLE_ENDIAN=y
# CONFIG_CPU_BIG_ENDIAN is not set
CONFIG_SH_FPU=y
# CONFIG_SH_STORE_QUEUES is not set
CONFIG_CPU_HAS_INTEVT=y
CONFIG_CPU_HAS_SR_RB=y
CONFIG_CPU_HAS_FPU=y
#
# Board support
#
# CONFIG_SH_7724_SOLUTION_ENGINE is not set
CONFIG_SH_KFR2R09=y
# CONFIG_SH_ECOVEC is not set
#
# Timer and clock configuration
#
# CONFIG_SH_TIMER_TMU is not set
CONFIG_SH_TIMER_CMT=y
CONFIG_SH_PCLK_FREQ=33333333
CONFIG_SH_CLK_CPG=y
# CONFIG_NO_HZ is not set
# CONFIG_HIGH_RES_TIMERS is not set
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
#
# CPU Frequency scaling
#
# CONFIG_CPU_FREQ is not set
#
# DMA support
#
# CONFIG_SH_DMA is not set
#
# Companion Chips
#
#
# Additional SuperH Device Drivers
#
# CONFIG_HEARTBEAT is not set
# CONFIG_PUSH_SWITCH is not set
#
# Kernel features
#
CONFIG_HZ_100=y
# CONFIG_HZ_250 is not set
# CONFIG_HZ_300 is not set
# CONFIG_HZ_1000 is not set
CONFIG_HZ=100
# CONFIG_SCHED_HRTICK is not set
CONFIG_KEXEC=y
# CONFIG_CRASH_DUMP is not set
# CONFIG_SECCOMP is not set
CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set
CONFIG_GUSA=y
# CONFIG_SPARSE_IRQ is not set
#
# Boot options
#
CONFIG_ZERO_PAGE_OFFSET=0x00001000
CONFIG_BOOT_LINK_OFFSET=0x00800000
CONFIG_ENTRY_OFFSET=0x00001000
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="console=ttySC1,115200 quiet"
#
# Bus options
#
# CONFIG_ARCH_SUPPORTS_MSI is not set
# CONFIG_PCCARD is not set
#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
# CONFIG_HAVE_AOUT is not set
# CONFIG_BINFMT_MISC is not set
#
# Power management options (EXPERIMENTAL)
#
CONFIG_PM=y
# CONFIG_PM_DEBUG is not set
# CONFIG_SUSPEND is not set
# CONFIG_CPU_IDLE is not set
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=y
CONFIG_PACKET_MMAP=y
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_FIB_HASH=y
# CONFIG_IP_PNP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_XFRM_TUNNEL is not set
# CONFIG_INET_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
# CONFIG_IPV6 is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETFILTER is not set
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_NET_DSA is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
# CONFIG_PHONET is not set
# CONFIG_IEEE802154 is not set
# CONFIG_NET_SCHED is not set
# CONFIG_DCB is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_CAN is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
# CONFIG_WIRELESS is not set
# CONFIG_WIMAX is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=y
CONFIG_FIRMWARE_IN_KERNEL=y
CONFIG_EXTRA_FIRMWARE=""
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_CONNECTOR is not set
# CONFIG_MTD is not set
# CONFIG_PARPORT is not set
# CONFIG_MISC_DEVICES is not set
CONFIG_HAVE_IDE=y
#
# SCSI device support
#
# CONFIG_SCSI_DMA is not set
# CONFIG_SCSI_NETLINK is not set
# CONFIG_NETDEVICES is not set
# CONFIG_ISDN is not set
# CONFIG_PHONE is not set
#
# Input device support
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Hardware I/O ports
#
# CONFIG_SERIO is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_DEVKMEM=y
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
# CONFIG_SERIAL_8250 is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_SH_SCI=y
CONFIG_SERIAL_SH_SCI_NR_UARTS=6
CONFIG_SERIAL_SH_SCI_CONSOLE=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_IPMI_HANDLER is not set
CONFIG_HW_RANDOM=y
# CONFIG_HW_RANDOM_TIMERIOMEM is not set
# CONFIG_R3964 is not set
# CONFIG_TCG_TPM is not set
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
# CONFIG_I2C_CHARDEV is not set
CONFIG_I2C_HELPER_AUTO=y
#
# I2C Hardware Bus support
#
#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_DESIGNWARE is not set
# CONFIG_I2C_GPIO is not set
# CONFIG_I2C_OCORES is not set
CONFIG_I2C_SH_MOBILE=y
# CONFIG_I2C_SIMTEC is not set
#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_TAOS_EVM is not set
#
# Other I2C/SMBus bus drivers
#
# CONFIG_I2C_PCA_PLATFORM is not set
#
# Miscellaneous I2C Chip support
#
# CONFIG_DS1682 is not set
# CONFIG_SENSORS_PCF8574 is not set
# CONFIG_PCF8575 is not set
# CONFIG_SENSORS_PCA9539 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
# CONFIG_SPI is not set
#
# PPS support
#
# CONFIG_PPS is not set
CONFIG_ARCH_REQUIRE_GPIOLIB=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
#
# Memory mapped GPIO expanders:
#
#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
#
# PCI GPIO expanders:
#
#
# SPI GPIO expanders:
#
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
# CONFIG_THERMAL is not set
# CONFIG_THERMAL_HWMON is not set
# CONFIG_WATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
#
# Sonics Silicon Backplane
#
# CONFIG_SSB is not set
#
# Multifunction device drivers
#
# CONFIG_MFD_CORE is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_TPS65010 is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_AB3100_CORE is not set
# CONFIG_REGULATOR is not set
# CONFIG_MEDIA_SUPPORT is not set
#
# Graphics support
#
# CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
# CONFIG_FB is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
#
# Console display driver support
#
CONFIG_DUMMY_CONSOLE=y
# CONFIG_SOUND is not set
# CONFIG_HID_SUPPORT is not set
CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
# CONFIG_USB_ARCH_HAS_OHCI is not set
# CONFIG_USB_ARCH_HAS_EHCI is not set
# CONFIG_USB is not set
# CONFIG_USB_OTG_WHITELIST is not set
# CONFIG_USB_OTG_BLACKLIST_HUB is not set
# CONFIG_USB_GADGET_MUSB_HDRC is not set
#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#
CONFIG_USB_GADGET=y
# CONFIG_USB_GADGET_DEBUG_FILES is not set
# CONFIG_USB_GADGET_DEBUG_FS is not set
CONFIG_USB_GADGET_VBUS_DRAW=2
CONFIG_USB_GADGET_SELECTED=y
# CONFIG_USB_GADGET_AT91 is not set
# CONFIG_USB_GADGET_ATMEL_USBA is not set
# CONFIG_USB_GADGET_FSL_USB2 is not set
# CONFIG_USB_GADGET_LH7A40X is not set
# CONFIG_USB_GADGET_OMAP is not set
# CONFIG_USB_GADGET_PXA25X is not set
CONFIG_USB_GADGET_R8A66597=y
CONFIG_USB_R8A66597=y
# CONFIG_USB_GADGET_PXA27X is not set
# CONFIG_USB_GADGET_S3C_HSOTG is not set
# CONFIG_USB_GADGET_IMX is not set
# CONFIG_USB_GADGET_S3C2410 is not set
# CONFIG_USB_GADGET_M66592 is not set
# CONFIG_USB_GADGET_AMD5536UDC is not set
# CONFIG_USB_GADGET_FSL_QE is not set
# CONFIG_USB_GADGET_CI13XXX is not set
# CONFIG_USB_GADGET_NET2280 is not set
# CONFIG_USB_GADGET_GOKU is not set
# CONFIG_USB_GADGET_LANGWELL is not set
# CONFIG_USB_GADGET_DUMMY_HCD is not set
CONFIG_USB_GADGET_DUALSPEED=y
# CONFIG_USB_ZERO is not set
# CONFIG_USB_AUDIO is not set
# CONFIG_USB_ETH is not set
# CONFIG_USB_GADGETFS is not set
# CONFIG_USB_FILE_STORAGE is not set
# CONFIG_USB_G_SERIAL is not set
# CONFIG_USB_MIDI_GADGET is not set
# CONFIG_USB_G_PRINTER is not set
CONFIG_USB_CDC_COMPOSITE=y
#
# OTG and related infrastructure
#
# CONFIG_USB_GPIO_VBUS is not set
# CONFIG_NOP_USB_XCEIV is not set
# CONFIG_MMC is not set
# CONFIG_MEMSTICK is not set
# CONFIG_NEW_LEDS is not set
# CONFIG_ACCESSIBILITY is not set
CONFIG_RTC_LIB=y
# CONFIG_RTC_CLASS is not set
# CONFIG_DMADEVICES is not set
# CONFIG_AUXDISPLAY is not set
# CONFIG_UIO is not set
#
# TI VLYNQ
#
# CONFIG_STAGING is not set
#
# File systems
#
CONFIG_FILE_LOCKING=y
# CONFIG_FSNOTIFY is not set
# CONFIG_DNOTIFY is not set
# CONFIG_INOTIFY is not set
# CONFIG_INOTIFY_USER is not set
# CONFIG_QUOTA is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set
#
# Caches
#
# CONFIG_FSCACHE is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLBFS is not set
# CONFIG_HUGETLB_PAGE is not set
# CONFIG_CONFIGFS_FS is not set
# CONFIG_MISC_FILESYSTEMS is not set
# CONFIG_NETWORK_FILESYSTEMS is not set
# CONFIG_NLS is not set
# CONFIG_DLM is not set
#
# Kernel hacking
#
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
# CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_WARN_DEPRECATED=y
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_FRAME_WARN=1024
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
CONFIG_DEBUG_FS=y
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_LATENCYTOP is not set
# CONFIG_SYSCTL_SYSCALL_CHECK is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_FTRACE_SYSCALLS=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
# CONFIG_DYNAMIC_DEBUG is not set
# CONFIG_DMA_API_DEBUG is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_SH_STANDARD_BIOS is not set
# CONFIG_EARLY_SCIF_CONSOLE is not set
# CONFIG_DWARF_UNWINDER is not set
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITYFS is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_CRYPTO is not set
# CONFIG_BINARY_PRINTF is not set
#
# Library routines
#
CONFIG_GENERIC_FIND_LAST_BIT=y
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
# CONFIG_CRC_T10DIF is not set
# CONFIG_CRC_ITU_T is not set
# CONFIG_CRC32 is not set
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_DECOMPRESS_GZIP=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
CONFIG_HAVE_LMB=y
CONFIG_NLATTR=y
CONFIG_GENERIC_ATOMIC64=y

212
arch/sh/configs/kfr2r09_defconfig
View File

@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.31-rc3
# Thu Jul 23 17:45:09 2009
# Linux kernel version: 2.6.31-rc6
# Thu Aug 20 21:58:52 2009
#
CONFIG_SUPERH=y
CONFIG_SUPERH32=y
@ -38,6 +38,7 @@ CONFIG_CONSTRUCTORS=y
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_LOCK_KERNEL=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
@ -132,7 +133,12 @@ CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
# CONFIG_MODULES is not set
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_BLOCK=y
CONFIG_LBDAF=y
# CONFIG_BLK_DEV_BSG is not set
@ -255,6 +261,7 @@ CONFIG_CPU_HAS_FPU=y
#
# CONFIG_SH_7724_SOLUTION_ENGINE is not set
CONFIG_SH_KFR2R09=y
# CONFIG_SH_ECOVEC is not set
#
# Timer and clock configuration
@ -301,8 +308,8 @@ CONFIG_KEXEC=y
# CONFIG_CRASH_DUMP is not set
# CONFIG_SECCOMP is not set
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
# CONFIG_PREEMPT_VOLUNTARY is not set
CONFIG_PREEMPT=y
CONFIG_GUSA=y
# CONFIG_SPARSE_IRQ is not set
@ -313,7 +320,7 @@ CONFIG_ZERO_PAGE_OFFSET=0x00001000
CONFIG_BOOT_LINK_OFFSET=0x00800000
CONFIG_ENTRY_OFFSET=0x00001000
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="console=ttySC1,115200"
CONFIG_CMDLINE="console=tty0 console=ttySC1,115200"
#
# Bus options
@ -427,6 +434,7 @@ CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
CONFIG_MTD_CONCAT=y
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_TESTS is not set
# CONFIG_MTD_REDBOOT_PARTS is not set
CONFIG_MTD_CMDLINE_PARTS=y
# CONFIG_MTD_AR7_PARTS is not set
@ -639,6 +647,7 @@ CONFIG_I2C_SH_MOBILE=y
# Other I2C/SMBus bus drivers
#
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_STUB is not set
#
# Miscellaneous I2C Chip support
@ -715,7 +724,35 @@ CONFIG_SSB_POSSIBLE=y
#
# CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
# CONFIG_FB is not set
CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
# CONFIG_FB_DDC is not set
# CONFIG_FB_BOOT_VESA_SUPPORT is not set
# CONFIG_FB_CFB_FILLRECT is not set
# CONFIG_FB_CFB_COPYAREA is not set
# CONFIG_FB_CFB_IMAGEBLIT is not set
# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_FOREIGN_ENDIAN is not set
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_DEFERRED_IO=y
# CONFIG_FB_SVGALIB is not set
# CONFIG_FB_MACMODES is not set
# CONFIG_FB_BACKLIGHT is not set
# CONFIG_FB_MODE_HELPERS is not set
# CONFIG_FB_TILEBLITTING is not set
#
# Frame buffer hardware drivers
#
# CONFIG_FB_S1D13XXX is not set
CONFIG_FB_SH_MOBILE_LCDC=y
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MB862XX is not set
# CONFIG_FB_BROADSHEET is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
@ -727,15 +764,157 @@ CONFIG_SSB_POSSIBLE=y
# Console display driver support
#
CONFIG_DUMMY_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
CONFIG_FONTS=y
# CONFIG_FONT_8x8 is not set
# CONFIG_FONT_8x16 is not set
# CONFIG_FONT_6x11 is not set
# CONFIG_FONT_7x14 is not set
# CONFIG_FONT_PEARL_8x8 is not set
# CONFIG_FONT_ACORN_8x8 is not set
CONFIG_FONT_MINI_4x6=y
# CONFIG_FONT_SUN8x16 is not set
# CONFIG_FONT_SUN12x22 is not set
# CONFIG_FONT_10x18 is not set
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
# CONFIG_LOGO_LINUX_CLUT224 is not set
# CONFIG_LOGO_SUPERH_MONO is not set
CONFIG_LOGO_SUPERH_VGA16=y
# CONFIG_LOGO_SUPERH_CLUT224 is not set
# CONFIG_SOUND is not set
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
# CONFIG_MMC is not set
CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
# CONFIG_USB_ARCH_HAS_OHCI is not set
# CONFIG_USB_ARCH_HAS_EHCI is not set
# CONFIG_USB is not set
# CONFIG_USB_OTG_WHITELIST is not set
# CONFIG_USB_OTG_BLACKLIST_HUB is not set
# CONFIG_USB_GADGET_MUSB_HDRC is not set
#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#
CONFIG_USB_GADGET=y
# CONFIG_USB_GADGET_DEBUG_FILES is not set
# CONFIG_USB_GADGET_DEBUG_FS is not set
CONFIG_USB_GADGET_VBUS_DRAW=2
CONFIG_USB_GADGET_SELECTED=y
# CONFIG_USB_GADGET_AT91 is not set
# CONFIG_USB_GADGET_ATMEL_USBA is not set
# CONFIG_USB_GADGET_FSL_USB2 is not set
# CONFIG_USB_GADGET_LH7A40X is not set
# CONFIG_USB_GADGET_OMAP is not set
# CONFIG_USB_GADGET_PXA25X is not set
CONFIG_USB_GADGET_R8A66597=y
CONFIG_USB_R8A66597=y
# CONFIG_USB_GADGET_PXA27X is not set
# CONFIG_USB_GADGET_S3C_HSOTG is not set
# CONFIG_USB_GADGET_IMX is not set
# CONFIG_USB_GADGET_S3C2410 is not set
# CONFIG_USB_GADGET_M66592 is not set
# CONFIG_USB_GADGET_AMD5536UDC is not set
# CONFIG_USB_GADGET_FSL_QE is not set
# CONFIG_USB_GADGET_CI13XXX is not set
# CONFIG_USB_GADGET_NET2280 is not set
# CONFIG_USB_GADGET_GOKU is not set
# CONFIG_USB_GADGET_LANGWELL is not set
# CONFIG_USB_GADGET_DUMMY_HCD is not set
CONFIG_USB_GADGET_DUALSPEED=y
# CONFIG_USB_ZERO is not set
# CONFIG_USB_AUDIO is not set
# CONFIG_USB_ETH is not set
# CONFIG_USB_GADGETFS is not set
# CONFIG_USB_FILE_STORAGE is not set
# CONFIG_USB_G_SERIAL is not set
# CONFIG_USB_MIDI_GADGET is not set
# CONFIG_USB_G_PRINTER is not set
CONFIG_USB_CDC_COMPOSITE=y
#
# OTG and related infrastructure
#
# CONFIG_USB_GPIO_VBUS is not set
# CONFIG_NOP_USB_XCEIV is not set
CONFIG_MMC=y
# CONFIG_MMC_DEBUG is not set
# CONFIG_MMC_UNSAFE_RESUME is not set
#
# MMC/SD/SDIO Card Drivers
#
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_BOUNCE=y
# CONFIG_SDIO_UART is not set
# CONFIG_MMC_TEST is not set
#
# MMC/SD/SDIO Host Controller Drivers
#
# CONFIG_MMC_SDHCI is not set
# CONFIG_MEMSTICK is not set
# CONFIG_NEW_LEDS is not set
# CONFIG_ACCESSIBILITY is not set
CONFIG_RTC_LIB=y
# CONFIG_RTC_CLASS is not set
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set
#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
# CONFIG_RTC_DRV_TEST is not set
#
# I2C RTC drivers
#
# CONFIG_RTC_DRV_DS1307 is not set
# CONFIG_RTC_DRV_DS1374 is not set
# CONFIG_RTC_DRV_DS1672 is not set
# CONFIG_RTC_DRV_MAX6900 is not set
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_ISL1208 is not set
# CONFIG_RTC_DRV_X1205 is not set
# CONFIG_RTC_DRV_PCF8563 is not set
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
# CONFIG_RTC_DRV_RX8581 is not set
# CONFIG_RTC_DRV_RX8025 is not set
#
# SPI RTC drivers
#
#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_DS1286 is not set
# CONFIG_RTC_DRV_DS1511 is not set
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_BQ4802 is not set
# CONFIG_RTC_DRV_V3020 is not set
#
# on-CPU RTC drivers
#
CONFIG_RTC_DRV_SH=y
# CONFIG_RTC_DRV_GENERIC is not set
# CONFIG_DMADEVICES is not set
# CONFIG_AUXDISPLAY is not set
CONFIG_UIO=y
@ -763,8 +942,10 @@ CONFIG_UIO_PDRV_GENIRQ=y
# CONFIG_OCFS2_FS is not set
# CONFIG_BTRFS_FS is not set
CONFIG_FILE_LOCKING=y
# CONFIG_FSNOTIFY is not set
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
# CONFIG_INOTIFY is not set
CONFIG_INOTIFY_USER=y
# CONFIG_QUOTA is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
@ -829,7 +1010,7 @@ CONFIG_DEBUG_FS=y
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_LATENCYTOP is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
# CONFIG_SYSCTL_SYSCALL_CHECK is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
@ -844,6 +1025,7 @@ CONFIG_TRACING_SUPPORT=y
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_SH_STANDARD_BIOS is not set
# CONFIG_EARLY_SCIF_CONSOLE is not set
# CONFIG_DWARF_UNWINDER is not set
#
# Security options
@ -862,10 +1044,10 @@ CONFIG_BITREVERSE=y
CONFIG_GENERIC_FIND_LAST_BIT=y
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
CONFIG_CRC_T10DIF=y
CONFIG_CRC_ITU_T=y
# CONFIG_CRC_T10DIF is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
CONFIG_CRC7=y
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_DECOMPRESS_GZIP=y

77
arch/sh/configs/snapgear_defconfig
View File

@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.30
# Thu Jun 18 13:11:58 2009
# Linux kernel version: 2.6.31-rc6
# Thu Aug 20 15:03:04 2009
#
CONFIG_SUPERH=y
CONFIG_SUPERH32=y
@ -14,6 +14,7 @@ CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_IRQ_PER_CPU=y
# CONFIG_GENERIC_GPIO is not set
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
@ -28,7 +29,9 @@ CONFIG_HAVE_LATENCYTOP_SUPPORT=y
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_ARCH_NO_VIRT_TO_BUS=y
CONFIG_ARCH_HAS_DEFAULT_IDLE=y
CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
CONFIG_CONSTRUCTORS=y
#
# General setup
@ -38,6 +41,12 @@ CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_HAVE_KERNEL_GZIP=y
CONFIG_HAVE_KERNEL_BZIP2=y
CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_BZIP2 is not set
# CONFIG_KERNEL_LZMA is not set
# CONFIG_SWAP is not set
# CONFIG_SYSVIPC is not set
# CONFIG_POSIX_MQUEUE is not set
@ -86,10 +95,12 @@ CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_HAVE_PERF_COUNTERS=y
#
# Performance Counters
#
# CONFIG_PERF_COUNTERS is not set
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_PCI_QUIRKS=y
# CONFIG_STRIP_ASM_SYMS is not set
@ -106,6 +117,10 @@ CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_DMA_API_DEBUG=y
#
# GCOV-based kernel profiling
#
# CONFIG_SLOW_WORK is not set
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_SLABINFO=y
@ -113,7 +128,7 @@ CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
# CONFIG_MODULES is not set
CONFIG_BLOCK=y
# CONFIG_LBD is not set
CONFIG_LBDAF=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_BLK_DEV_INTEGRITY is not set
@ -534,7 +549,11 @@ CONFIG_HAVE_IDE=y
#
#
# Enable only one of the two stacks, unless you know what you are doing
# You can enable one or both FireWire driver stacks.
#
#
# See the help texts for more information.
#
# CONFIG_FIREWIRE is not set
# CONFIG_IEEE1394 is not set
@ -686,6 +705,11 @@ CONFIG_LEGACY_PTY_COUNT=256
CONFIG_DEVPORT=y
# CONFIG_I2C is not set
# CONFIG_SPI is not set
#
# PPS support
#
# CONFIG_PPS is not set
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
@ -732,7 +756,44 @@ CONFIG_SSB_POSSIBLE=y
# CONFIG_ACCESSIBILITY is not set
# CONFIG_INFINIBAND is not set
CONFIG_RTC_LIB=y
# CONFIG_RTC_CLASS is not set
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set
#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
# CONFIG_RTC_DRV_TEST is not set
#
# SPI RTC drivers
#
#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_DS1286 is not set
CONFIG_RTC_DRV_DS1302=y
# CONFIG_RTC_DRV_DS1511 is not set
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_BQ4802 is not set
# CONFIG_RTC_DRV_V3020 is not set
#
# on-CPU RTC drivers
#
# CONFIG_RTC_DRV_SH is not set
# CONFIG_RTC_DRV_GENERIC is not set
# CONFIG_DMADEVICES is not set
# CONFIG_AUXDISPLAY is not set
# CONFIG_UIO is not set
@ -754,6 +815,7 @@ CONFIG_EXT2_FS=y
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_BTRFS_FS is not set
CONFIG_FILE_LOCKING=y
@ -856,8 +918,11 @@ CONFIG_FRAME_WARN=1024
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_LATENCYTOP is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_FTRACE_SYSCALLS=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
# CONFIG_DMA_API_DEBUG is not set
@ -865,6 +930,7 @@ CONFIG_TRACING_SUPPORT=y
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_SH_STANDARD_BIOS is not set
# CONFIG_EARLY_SCIF_CONSOLE is not set
# CONFIG_DWARF_UNWINDER is not set
#
# Security options
@ -893,5 +959,6 @@ CONFIG_DECOMPRESS_GZIP=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
CONFIG_HAVE_LMB=y
CONFIG_NLATTR=y
CONFIG_GENERIC_ATOMIC64=y

6
arch/sh/drivers/dma/Kconfig
View File

@ -27,12 +27,12 @@ config NR_ONCHIP_DMA_CHANNELS
default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R || \
CPU_SUBTYPE_SH7760
default "12" if CPU_SUBTYPE_SH7723 || CPU_SUBTYPE_SH7780 || \
CPU_SUBTYPE_SH7785
CPU_SUBTYPE_SH7785 || CPU_SUBTYPE_SH7724
default "6"
help
This allows you to specify the number of channels that the on-chip
DMAC supports. This will be 4 for SH7091/SH7750/SH7751 and 8 for the
SH7750R/SH7751R.
DMAC supports. This will be 4 for SH7750/SH7751/Sh7750S/SH7091 and 8 for the
SH7750R/SH7751R/SH7760, 12 for the SH7723/SH7780/SH7785/SH7724, default is 6.
config NR_DMA_CHANNELS_BOOL
depends on SH_DMA

4
arch/sh/drivers/pci/pci.c
View File

@ -295,6 +295,8 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
vma->vm_page_prot);
}
#ifndef CONFIG_GENERIC_IOMAP
static void __iomem *ioport_map_pci(struct pci_dev *dev,
unsigned long port, unsigned int nr)
{
@ -346,6 +348,8 @@ void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
}
EXPORT_SYMBOL(pci_iounmap);
#endif /* CONFIG_GENERIC_IOMAP */
#ifdef CONFIG_HOTPLUG
EXPORT_SYMBOL(pcibios_resource_to_bus);
EXPORT_SYMBOL(pcibios_bus_to_resource);

2
arch/sh/include/asm/Kbuild
View File

@ -1,6 +1,6 @@
include include/asm-generic/Kbuild.asm
header-y += cpu-features.h
header-y += cachectl.h cpu-features.h
unifdef-y += unistd_32.h
unifdef-y += unistd_64.h

31
arch/sh/include/asm/bug.h
View File

@ -2,6 +2,7 @@
#define __ASM_SH_BUG_H
#define TRAPA_BUG_OPCODE 0xc33e /* trapa #0x3e */
#define BUGFLAG_UNWINDER (1 << 1)
#ifdef CONFIG_GENERIC_BUG
#define HAVE_ARCH_BUG
@ -72,6 +73,36 @@ do { \
unlikely(__ret_warn_on); \
})
#define UNWINDER_BUG() \
do { \
__asm__ __volatile__ ( \
"1:\t.short %O0\n" \
_EMIT_BUG_ENTRY \
: \
: "n" (TRAPA_BUG_OPCODE), \
"i" (__FILE__), \
"i" (__LINE__), \
"i" (BUGFLAG_UNWINDER), \
"i" (sizeof(struct bug_entry))); \
} while (0)
#define UNWINDER_BUG_ON(x) ({ \
int __ret_unwinder_on = !!(x); \
if (__builtin_constant_p(__ret_unwinder_on)) { \
if (__ret_unwinder_on) \
UNWINDER_BUG(); \
} else { \
if (unlikely(__ret_unwinder_on)) \
UNWINDER_BUG(); \
} \
unlikely(__ret_unwinder_on); \
})
#else
#define UNWINDER_BUG BUG
#define UNWINDER_BUG_ON BUG_ON
#endif /* CONFIG_GENERIC_BUG */
#include <asm-generic/bug.h>

19
arch/sh/include/asm/cachectl.h Normal file
View File

@ -0,0 +1,19 @@
#ifndef _SH_CACHECTL_H
#define _SH_CACHECTL_H
/* Definitions for the cacheflush system call. */
#define CACHEFLUSH_D_INVAL 0x1 /* invalidate (without write back) */
#define CACHEFLUSH_D_WB 0x2 /* write back (without invalidate) */
#define CACHEFLUSH_D_PURGE 0x3 /* writeback and invalidate */
#define CACHEFLUSH_I 0x4
/*
* Options for cacheflush system call
*/
#define ICACHE CACHEFLUSH_I /* flush instruction cache */
#define DCACHE CACHEFLUSH_D_PURGE /* writeback and flush data cache */
#define BCACHE (ICACHE|DCACHE) /* flush both caches */
#endif /* _SH_CACHECTL_H */

16
arch/sh/include/asm/device.h
View File

@ -3,7 +3,9 @@
*
* This file is released under the GPLv2
*/
#include <asm-generic/device.h>
struct dev_archdata {
};
struct platform_device;
/* allocate contiguous memory chunk and fill in struct resource */
@ -12,3 +14,15 @@ int platform_resource_setup_memory(struct platform_device *pdev,
void plat_early_device_setup(void);
#define PDEV_ARCHDATA_FLAG_INIT 0
#define PDEV_ARCHDATA_FLAG_IDLE 1
#define PDEV_ARCHDATA_FLAG_SUSP 2
struct pdev_archdata {
int hwblk_id;
#ifdef CONFIG_PM_RUNTIME
unsigned long flags;
struct list_head entry;
struct mutex mutex;
#endif
};

30
arch/sh/include/asm/dwarf.h
View File

@ -200,7 +200,7 @@
*/
static __always_inline unsigned long dwarf_read_arch_reg(unsigned int reg)
{
unsigned long value;
unsigned long value = 0;
switch (reg) {
case 14:
@ -265,10 +265,7 @@ struct dwarf_frame {
unsigned long pc;
struct dwarf_reg *regs;
unsigned int num_regs; /* how many regs are allocated? */
unsigned int depth; /* what level are we in the callstack? */
struct list_head reg_list;
unsigned long cfa;
@ -292,20 +289,15 @@ struct dwarf_frame {
* @flags: Describes how to calculate the value of this register
*/
struct dwarf_reg {
struct list_head link;
unsigned int number;
unsigned long addr;
unsigned long flags;
#define DWARF_REG_OFFSET (1 << 0)
};
/**
* dwarf_stack - a DWARF stack contains a collection of DWARF frames
* @depth: the number of frames in the stack
* @level: an array of DWARF frames, indexed by stack level
*
*/
struct dwarf_stack {
unsigned int depth;
struct dwarf_frame **level;
#define DWARF_VAL_OFFSET (1 << 1)
#define DWARF_UNDEFINED (1 << 2)
};
/*
@ -370,17 +362,16 @@ static inline unsigned int DW_CFA_operand(unsigned long insn)
#define DW_EXT_HI 0xffffffff
#define DW_EXT_DWARF64 DW_EXT_HI
extern void dwarf_unwinder_init(void);
extern struct dwarf_frame *dwarf_unwind_stack(unsigned long,
struct dwarf_frame *);
#endif /* __ASSEMBLY__ */
#endif /* !__ASSEMBLY__ */
#define CFI_STARTPROC .cfi_startproc
#define CFI_ENDPROC .cfi_endproc
#define CFI_DEF_CFA .cfi_def_cfa
#define CFI_REGISTER .cfi_register
#define CFI_REL_OFFSET .cfi_rel_offset
#define CFI_UNDEFINED .cfi_undefined
#else
@ -394,6 +385,7 @@ extern struct dwarf_frame *dwarf_unwind_stack(unsigned long,
#define CFI_DEF_CFA CFI_IGNORE
#define CFI_REGISTER CFI_IGNORE
#define CFI_REL_OFFSET CFI_IGNORE
#define CFI_UNDEFINED CFI_IGNORE
#ifndef __ASSEMBLY__
static inline void dwarf_unwinder_init(void)

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