ARM: EXYNOS4: Add support PM for EXYNOS4212
This patch moves regarding clock stuff of PM into clock file to support PM on EXYNOS4210 and EXYNOS4212 with one single kernel image. Because some clock registers are different on each SoCs. Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com> [kgene.kim@samsung.com: use CONFIG_PM_SLEEP instead of CONFIG_PM] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
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2bc02c0daa
commit
acd35616c7
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@ -15,6 +15,7 @@
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/syscore_ops.h>
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#include <plat/cpu-freq.h>
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#include <plat/clock.h>
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@ -23,12 +24,24 @@
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#include <plat/s5p-clock.h>
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#include <plat/clock-clksrc.h>
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#include <plat/exynos4.h>
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#include <plat/pm.h>
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#include <mach/hardware.h>
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#include <mach/map.h>
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#include <mach/regs-clock.h>
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#include <mach/exynos4-clock.h>
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static struct sleep_save exynos4210_clock_save[] = {
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SAVE_ITEM(S5P_CLKSRC_IMAGE),
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SAVE_ITEM(S5P_CLKSRC_LCD1),
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SAVE_ITEM(S5P_CLKDIV_IMAGE),
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SAVE_ITEM(S5P_CLKDIV_LCD1),
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SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
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SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),
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SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
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SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
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};
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static struct clksrc_clk *sysclks[] = {
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/* nothing here yet */
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};
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@ -83,6 +96,29 @@ static struct clk init_clocks_off[] = {
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},
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};
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#ifdef CONFIG_PM_SLEEP
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static int exynos4210_clock_suspend(void)
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{
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s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
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return 0;
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}
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static void exynos4210_clock_resume(void)
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{
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s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
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}
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#else
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#define exynos4210_clock_suspend NULL
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#define exynos4210_clock_resume NULL
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#endif
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struct syscore_ops exynos4210_clock_syscore_ops = {
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.suspend = exynos4210_clock_suspend,
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.resume = exynos4210_clock_resume,
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};
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void __init exynos4210_register_clocks(void)
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{
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int ptr;
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@ -98,4 +134,6 @@ void __init exynos4210_register_clocks(void)
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s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
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s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
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register_syscore_ops(&exynos4210_clock_syscore_ops);
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}
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@ -15,6 +15,7 @@
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/syscore_ops.h>
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#include <plat/cpu-freq.h>
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#include <plat/clock.h>
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@ -23,12 +24,20 @@
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#include <plat/s5p-clock.h>
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#include <plat/clock-clksrc.h>
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#include <plat/exynos4.h>
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#include <plat/pm.h>
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#include <mach/hardware.h>
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#include <mach/map.h>
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#include <mach/regs-clock.h>
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#include <mach/exynos4-clock.h>
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static struct sleep_save exynos4212_clock_save[] = {
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SAVE_ITEM(S5P_CLKSRC_IMAGE),
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SAVE_ITEM(S5P_CLKDIV_IMAGE),
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SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
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SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
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};
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static struct clk *clk_src_mpll_user_list[] = {
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[0] = &clk_fin_mpll,
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[1] = &clk_mout_mpll.clk,
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@ -59,6 +68,29 @@ static struct clk init_clocks_off[] = {
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/* nothing here yet */
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};
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#ifdef CONFIG_PM_SLEEP
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static int exynos4212_clock_suspend(void)
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{
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s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
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return 0;
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}
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static void exynos4212_clock_resume(void)
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{
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s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
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}
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#else
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#define exynos4212_clock_suspend NULL
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#define exynos4212_clock_resume NULL
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#endif
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struct syscore_ops exynos4212_clock_syscore_ops = {
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.suspend = exynos4212_clock_suspend,
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.resume = exynos4212_clock_resume,
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};
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void __init exynos4212_register_clocks(void)
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{
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int ptr;
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@ -81,4 +113,6 @@ void __init exynos4212_register_clocks(void)
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s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
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s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
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register_syscore_ops(&exynos4212_clock_syscore_ops);
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}
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@ -13,6 +13,7 @@
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/syscore_ops.h>
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#include <plat/cpu-freq.h>
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#include <plat/clock.h>
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@ -21,12 +22,77 @@
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#include <plat/s5p-clock.h>
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#include <plat/clock-clksrc.h>
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#include <plat/exynos4.h>
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#include <plat/pm.h>
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#include <mach/map.h>
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#include <mach/regs-clock.h>
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#include <mach/sysmmu.h>
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#include <mach/exynos4-clock.h>
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static struct sleep_save exynos4_clock_save[] = {
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SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
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SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
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SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
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SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
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SAVE_ITEM(S5P_CLKSRC_TOP0),
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SAVE_ITEM(S5P_CLKSRC_TOP1),
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SAVE_ITEM(S5P_CLKSRC_CAM),
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SAVE_ITEM(S5P_CLKSRC_TV),
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SAVE_ITEM(S5P_CLKSRC_MFC),
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SAVE_ITEM(S5P_CLKSRC_G3D),
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SAVE_ITEM(S5P_CLKSRC_LCD0),
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SAVE_ITEM(S5P_CLKSRC_MAUDIO),
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SAVE_ITEM(S5P_CLKSRC_FSYS),
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SAVE_ITEM(S5P_CLKSRC_PERIL0),
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SAVE_ITEM(S5P_CLKSRC_PERIL1),
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SAVE_ITEM(S5P_CLKDIV_CAM),
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SAVE_ITEM(S5P_CLKDIV_TV),
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SAVE_ITEM(S5P_CLKDIV_MFC),
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SAVE_ITEM(S5P_CLKDIV_G3D),
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SAVE_ITEM(S5P_CLKDIV_LCD0),
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SAVE_ITEM(S5P_CLKDIV_MAUDIO),
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SAVE_ITEM(S5P_CLKDIV_FSYS0),
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SAVE_ITEM(S5P_CLKDIV_FSYS1),
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SAVE_ITEM(S5P_CLKDIV_FSYS2),
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SAVE_ITEM(S5P_CLKDIV_FSYS3),
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SAVE_ITEM(S5P_CLKDIV_PERIL0),
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SAVE_ITEM(S5P_CLKDIV_PERIL1),
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SAVE_ITEM(S5P_CLKDIV_PERIL2),
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SAVE_ITEM(S5P_CLKDIV_PERIL3),
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SAVE_ITEM(S5P_CLKDIV_PERIL4),
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SAVE_ITEM(S5P_CLKDIV_PERIL5),
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SAVE_ITEM(S5P_CLKDIV_TOP),
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SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
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SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
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SAVE_ITEM(S5P_CLKSRC_MASK_TV),
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SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
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SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
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SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
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SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
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SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
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SAVE_ITEM(S5P_CLKDIV2_RATIO),
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SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
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SAVE_ITEM(S5P_CLKGATE_IP_CAM),
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SAVE_ITEM(S5P_CLKGATE_IP_TV),
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SAVE_ITEM(S5P_CLKGATE_IP_MFC),
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SAVE_ITEM(S5P_CLKGATE_IP_G3D),
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SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
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SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
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SAVE_ITEM(S5P_CLKGATE_IP_GPS),
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SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
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SAVE_ITEM(S5P_CLKGATE_BLOCK),
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SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
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SAVE_ITEM(S5P_CLKSRC_DMC),
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SAVE_ITEM(S5P_CLKDIV_DMC0),
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SAVE_ITEM(S5P_CLKDIV_DMC1),
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SAVE_ITEM(S5P_CLKGATE_IP_DMC),
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SAVE_ITEM(S5P_CLKSRC_CPU),
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SAVE_ITEM(S5P_CLKDIV_CPU),
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SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
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SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
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SAVE_ITEM(S5P_CLKGATE_IP_CPU),
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};
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struct clk clk_sclk_hdmi27m = {
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.name = "sclk_hdmi27m",
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.rate = 27000000,
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/* Nothing here yet */
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};
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#ifdef CONFIG_PM_SLEEP
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static int exynos4_clock_suspend(void)
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{
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s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
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return 0;
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}
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static void exynos4_clock_resume(void)
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{
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s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
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}
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#else
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#define exynos4_clock_suspend NULL
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#define exynos4_clock_resume NULL
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#endif
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struct syscore_ops exynos4_clock_syscore_ops = {
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.suspend = exynos4_clock_suspend,
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.resume = exynos4_clock_resume,
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};
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void __init exynos4_register_clocks(void)
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{
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int ptr;
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s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
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s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
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register_syscore_ops(&exynos4_clock_syscore_ops);
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s3c_pwmclk_init();
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}
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@ -86,6 +86,8 @@
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#define S5P_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \
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S5P_CLKREG(0x0C930) : \
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S5P_CLKREG(0x04930))
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#define S5P_CLKGATE_IP_IMAGE_4210 S5P_CLKREG(0x0C930)
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#define S5P_CLKGATE_IP_IMAGE_4212 S5P_CLKREG(0x04930)
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#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934)
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#define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940)
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#define S5P_CLKGATE_IP_GPS S5P_CLKREG(0x0C94C)
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#define S5P_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \
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S5P_CLKREG(0x0C960) : \
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S5P_CLKREG(0x08960))
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#define S5P_CLKGATE_IP_PERIR_4210 S5P_CLKREG(0x0C960)
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#define S5P_CLKGATE_IP_PERIR_4212 S5P_CLKREG(0x08960)
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#define S5P_CLKGATE_BLOCK S5P_CLKREG(0x0C970)
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#define S5P_CLKSRC_MASK_DMC S5P_CLKREG(0x10300)
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@ -41,7 +41,6 @@ static struct sleep_save exynos4_set_clksrc[] = {
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{ .reg = S5P_CLKSRC_MASK_CAM , .val = 0x11111111, },
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{ .reg = S5P_CLKSRC_MASK_TV , .val = 0x00000111, },
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{ .reg = S5P_CLKSRC_MASK_LCD0 , .val = 0x00001111, },
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{ .reg = S5P_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
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{ .reg = S5P_CLKSRC_MASK_MAUDIO , .val = 0x00000001, },
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{ .reg = S5P_CLKSRC_MASK_FSYS , .val = 0x01011111, },
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{ .reg = S5P_CLKSRC_MASK_PERIL0 , .val = 0x01111111, },
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{ .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, },
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};
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static struct sleep_save exynos4210_set_clksrc[] = {
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{ .reg = S5P_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
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};
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static struct sleep_save exynos4_epll_save[] = {
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SAVE_ITEM(S5P_EPLL_CON0),
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SAVE_ITEM(S5P_EPLL_CON1),
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};
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static struct sleep_save exynos4_core_save[] = {
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/* CMU side */
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SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
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SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
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SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
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SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
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SAVE_ITEM(S5P_CLKSRC_TOP0),
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SAVE_ITEM(S5P_CLKSRC_TOP1),
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SAVE_ITEM(S5P_CLKSRC_CAM),
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SAVE_ITEM(S5P_CLKSRC_TV),
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SAVE_ITEM(S5P_CLKSRC_MFC),
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SAVE_ITEM(S5P_CLKSRC_G3D),
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SAVE_ITEM(S5P_CLKSRC_IMAGE),
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SAVE_ITEM(S5P_CLKSRC_LCD0),
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SAVE_ITEM(S5P_CLKSRC_LCD1),
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SAVE_ITEM(S5P_CLKSRC_MAUDIO),
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SAVE_ITEM(S5P_CLKSRC_FSYS),
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SAVE_ITEM(S5P_CLKSRC_PERIL0),
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SAVE_ITEM(S5P_CLKSRC_PERIL1),
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SAVE_ITEM(S5P_CLKDIV_CAM),
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SAVE_ITEM(S5P_CLKDIV_TV),
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SAVE_ITEM(S5P_CLKDIV_MFC),
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SAVE_ITEM(S5P_CLKDIV_G3D),
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SAVE_ITEM(S5P_CLKDIV_IMAGE),
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SAVE_ITEM(S5P_CLKDIV_LCD0),
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SAVE_ITEM(S5P_CLKDIV_LCD1),
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SAVE_ITEM(S5P_CLKDIV_MAUDIO),
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SAVE_ITEM(S5P_CLKDIV_FSYS0),
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SAVE_ITEM(S5P_CLKDIV_FSYS1),
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SAVE_ITEM(S5P_CLKDIV_FSYS2),
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SAVE_ITEM(S5P_CLKDIV_FSYS3),
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SAVE_ITEM(S5P_CLKDIV_PERIL0),
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SAVE_ITEM(S5P_CLKDIV_PERIL1),
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SAVE_ITEM(S5P_CLKDIV_PERIL2),
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SAVE_ITEM(S5P_CLKDIV_PERIL3),
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SAVE_ITEM(S5P_CLKDIV_PERIL4),
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SAVE_ITEM(S5P_CLKDIV_PERIL5),
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SAVE_ITEM(S5P_CLKDIV_TOP),
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SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
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SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
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SAVE_ITEM(S5P_CLKSRC_MASK_TV),
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SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
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SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
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SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
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SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
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SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
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SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
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SAVE_ITEM(S5P_CLKDIV2_RATIO),
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SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
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SAVE_ITEM(S5P_CLKGATE_IP_CAM),
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SAVE_ITEM(S5P_CLKGATE_IP_TV),
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SAVE_ITEM(S5P_CLKGATE_IP_MFC),
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SAVE_ITEM(S5P_CLKGATE_IP_G3D),
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SAVE_ITEM(S5P_CLKGATE_IP_IMAGE),
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SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
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SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
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SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
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SAVE_ITEM(S5P_CLKGATE_IP_GPS),
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SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
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SAVE_ITEM(S5P_CLKGATE_IP_PERIR),
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SAVE_ITEM(S5P_CLKGATE_BLOCK),
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SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
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SAVE_ITEM(S5P_CLKSRC_DMC),
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SAVE_ITEM(S5P_CLKDIV_DMC0),
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SAVE_ITEM(S5P_CLKDIV_DMC1),
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SAVE_ITEM(S5P_CLKGATE_IP_DMC),
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||||
SAVE_ITEM(S5P_CLKSRC_CPU),
|
||||
SAVE_ITEM(S5P_CLKDIV_CPU),
|
||||
SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
|
||||
SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_CPU),
|
||||
|
||||
/* GIC side */
|
||||
SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
|
||||
SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
|
||||
|
@ -268,6 +200,9 @@ static void exynos4_pm_prepare(void)
|
|||
|
||||
s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
|
||||
|
||||
if (soc_is_exynos4210())
|
||||
s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
|
||||
|
||||
}
|
||||
|
||||
static int exynos4_pm_add(struct sys_device *sysdev)
|
||||
|
|
Loading…
Reference in New Issue