counter: Add STM32 Timer quadrature encoder
Implement counter part of the STM32 timer hardware block by using counter API. Hardware only supports X2 and X4 quadrature modes. A ceiling value can be set to define the maximum value reachable by the counter. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Co-authored-by: Fabrice Gasnier <fabrice.gasnier@st.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Benjamin Gaignard
Greg Kroah-Hartman
parent
7e798ef90c
commit
ad29937e20
@ -28,4 +28,14 @@ config 104_QUAD_8
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The base port addresses for the devices may be configured via the base
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array module parameter.
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config STM32_TIMER_CNT
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tristate "STM32 Timer encoder counter driver"
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depends on MFD_STM32_TIMERS || COMPILE_TEST
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help
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Select this option to enable STM32 Timer quadrature encoder
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and counter driver.
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To compile this driver as a module, choose M here: the
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module will be called stm32-timer-cnt.
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endif # COUNTER
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@ -5,3 +5,4 @@
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obj-$(CONFIG_COUNTER) += counter.o
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obj-$(CONFIG_104_QUAD_8) += 104-quad-8.o
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obj-$(CONFIG_STM32_TIMER_CNT) += stm32-timer-cnt.o
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390
drivers/counter/stm32-timer-cnt.c
Normal file
390
drivers/counter/stm32-timer-cnt.c
Normal file
@ -0,0 +1,390 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* STM32 Timer Encoder and Counter driver
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*
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* Copyright (C) STMicroelectronics 2018
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*
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* Author: Benjamin Gaignard <benjamin.gaignard@st.com>
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*
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*/
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#include <linux/counter.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/types.h>
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#include <linux/mfd/stm32-timers.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#define TIM_CCMR_CCXS (BIT(8) | BIT(0))
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#define TIM_CCMR_MASK (TIM_CCMR_CC1S | TIM_CCMR_CC2S | \
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TIM_CCMR_IC1F | TIM_CCMR_IC2F)
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#define TIM_CCER_MASK (TIM_CCER_CC1P | TIM_CCER_CC1NP | \
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TIM_CCER_CC2P | TIM_CCER_CC2NP)
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struct stm32_timer_cnt {
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struct counter_device counter;
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struct regmap *regmap;
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struct clk *clk;
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u32 ceiling;
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};
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/**
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* stm32_count_function - enumerates stm32 timer counter encoder modes
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* @STM32_COUNT_SLAVE_MODE_DISABLED: counts on internal clock when CEN=1
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* @STM32_COUNT_ENCODER_MODE_1: counts TI1FP1 edges, depending on TI2FP2 level
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* @STM32_COUNT_ENCODER_MODE_2: counts TI2FP2 edges, depending on TI1FP1 level
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* @STM32_COUNT_ENCODER_MODE_3: counts on both TI1FP1 and TI2FP2 edges
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*/
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enum stm32_count_function {
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STM32_COUNT_SLAVE_MODE_DISABLED = -1,
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STM32_COUNT_ENCODER_MODE_1,
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STM32_COUNT_ENCODER_MODE_2,
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STM32_COUNT_ENCODER_MODE_3,
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};
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static enum counter_count_function stm32_count_functions[] = {
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[STM32_COUNT_ENCODER_MODE_1] = COUNTER_COUNT_FUNCTION_QUADRATURE_X2_A,
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[STM32_COUNT_ENCODER_MODE_2] = COUNTER_COUNT_FUNCTION_QUADRATURE_X2_B,
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[STM32_COUNT_ENCODER_MODE_3] = COUNTER_COUNT_FUNCTION_QUADRATURE_X4,
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};
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static int stm32_count_read(struct counter_device *counter,
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struct counter_count *count,
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struct counter_count_read_value *val)
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{
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struct stm32_timer_cnt *const priv = counter->priv;
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u32 cnt;
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regmap_read(priv->regmap, TIM_CNT, &cnt);
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counter_count_read_value_set(val, COUNTER_COUNT_POSITION, &cnt);
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return 0;
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}
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static int stm32_count_write(struct counter_device *counter,
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struct counter_count *count,
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struct counter_count_write_value *val)
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{
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struct stm32_timer_cnt *const priv = counter->priv;
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u32 cnt;
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int err;
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err = counter_count_write_value_get(&cnt, COUNTER_COUNT_POSITION, val);
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if (err)
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return err;
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if (cnt > priv->ceiling)
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return -EINVAL;
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return regmap_write(priv->regmap, TIM_CNT, cnt);
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}
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static int stm32_count_function_get(struct counter_device *counter,
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struct counter_count *count,
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size_t *function)
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{
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struct stm32_timer_cnt *const priv = counter->priv;
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u32 smcr;
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regmap_read(priv->regmap, TIM_SMCR, &smcr);
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switch (smcr & TIM_SMCR_SMS) {
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case 1:
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*function = STM32_COUNT_ENCODER_MODE_1;
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return 0;
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case 2:
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*function = STM32_COUNT_ENCODER_MODE_2;
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return 0;
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case 3:
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*function = STM32_COUNT_ENCODER_MODE_3;
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return 0;
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}
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return -EINVAL;
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}
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static int stm32_count_function_set(struct counter_device *counter,
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struct counter_count *count,
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size_t function)
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{
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struct stm32_timer_cnt *const priv = counter->priv;
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u32 cr1, sms;
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switch (function) {
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case STM32_COUNT_ENCODER_MODE_1:
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sms = 1;
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break;
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case STM32_COUNT_ENCODER_MODE_2:
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sms = 2;
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break;
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case STM32_COUNT_ENCODER_MODE_3:
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sms = 3;
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break;
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default:
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sms = 0;
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break;
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}
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/* Store enable status */
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regmap_read(priv->regmap, TIM_CR1, &cr1);
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
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/* TIMx_ARR register shouldn't be buffered (ARPE=0) */
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
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regmap_write(priv->regmap, TIM_ARR, priv->ceiling);
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regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);
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/* Make sure that registers are updated */
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regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
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/* Restore the enable status */
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, cr1);
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return 0;
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}
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static ssize_t stm32_count_direction_read(struct counter_device *counter,
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struct counter_count *count,
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void *private, char *buf)
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{
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struct stm32_timer_cnt *const priv = counter->priv;
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const char *direction;
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u32 cr1;
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regmap_read(priv->regmap, TIM_CR1, &cr1);
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direction = (cr1 & TIM_CR1_DIR) ? "backward" : "forward";
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return scnprintf(buf, PAGE_SIZE, "%s\n", direction);
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}
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static ssize_t stm32_count_ceiling_read(struct counter_device *counter,
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struct counter_count *count,
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void *private, char *buf)
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{
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struct stm32_timer_cnt *const priv = counter->priv;
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u32 arr;
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regmap_read(priv->regmap, TIM_ARR, &arr);
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return snprintf(buf, PAGE_SIZE, "%u\n", arr);
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}
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static ssize_t stm32_count_ceiling_write(struct counter_device *counter,
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struct counter_count *count,
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void *private,
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const char *buf, size_t len)
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{
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struct stm32_timer_cnt *const priv = counter->priv;
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unsigned int ceiling;
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int ret;
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ret = kstrtouint(buf, 0, &ceiling);
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if (ret)
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return ret;
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/* TIMx_ARR register shouldn't be buffered (ARPE=0) */
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
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regmap_write(priv->regmap, TIM_ARR, ceiling);
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priv->ceiling = ceiling;
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return len;
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}
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static ssize_t stm32_count_enable_read(struct counter_device *counter,
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struct counter_count *count,
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void *private, char *buf)
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{
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struct stm32_timer_cnt *const priv = counter->priv;
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u32 cr1;
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regmap_read(priv->regmap, TIM_CR1, &cr1);
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return scnprintf(buf, PAGE_SIZE, "%d\n", (bool)(cr1 & TIM_CR1_CEN));
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}
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static ssize_t stm32_count_enable_write(struct counter_device *counter,
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struct counter_count *count,
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void *private,
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const char *buf, size_t len)
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{
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struct stm32_timer_cnt *const priv = counter->priv;
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int err;
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u32 cr1;
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bool enable;
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err = kstrtobool(buf, &enable);
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if (err)
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return err;
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if (enable) {
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regmap_read(priv->regmap, TIM_CR1, &cr1);
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if (!(cr1 & TIM_CR1_CEN))
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clk_enable(priv->clk);
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
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TIM_CR1_CEN);
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} else {
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regmap_read(priv->regmap, TIM_CR1, &cr1);
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
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if (cr1 & TIM_CR1_CEN)
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clk_disable(priv->clk);
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}
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return len;
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}
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static const struct counter_count_ext stm32_count_ext[] = {
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{
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.name = "direction",
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.read = stm32_count_direction_read,
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},
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{
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.name = "enable",
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.read = stm32_count_enable_read,
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.write = stm32_count_enable_write
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},
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{
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.name = "ceiling",
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.read = stm32_count_ceiling_read,
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.write = stm32_count_ceiling_write
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},
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};
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enum stm32_synapse_action {
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STM32_SYNAPSE_ACTION_NONE,
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STM32_SYNAPSE_ACTION_BOTH_EDGES
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};
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static enum counter_synapse_action stm32_synapse_actions[] = {
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[STM32_SYNAPSE_ACTION_NONE] = COUNTER_SYNAPSE_ACTION_NONE,
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[STM32_SYNAPSE_ACTION_BOTH_EDGES] = COUNTER_SYNAPSE_ACTION_BOTH_EDGES
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};
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static int stm32_action_get(struct counter_device *counter,
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struct counter_count *count,
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struct counter_synapse *synapse,
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size_t *action)
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{
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size_t function;
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int err;
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/* Default action mode (e.g. STM32_COUNT_SLAVE_MODE_DISABLED) */
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*action = STM32_SYNAPSE_ACTION_NONE;
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err = stm32_count_function_get(counter, count, &function);
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if (err)
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return 0;
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switch (function) {
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case STM32_COUNT_ENCODER_MODE_1:
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/* counts up/down on TI1FP1 edge depending on TI2FP2 level */
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if (synapse->signal->id == count->synapses[0].signal->id)
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*action = STM32_SYNAPSE_ACTION_BOTH_EDGES;
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break;
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case STM32_COUNT_ENCODER_MODE_2:
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/* counts up/down on TI2FP2 edge depending on TI1FP1 level */
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if (synapse->signal->id == count->synapses[1].signal->id)
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*action = STM32_SYNAPSE_ACTION_BOTH_EDGES;
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break;
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case STM32_COUNT_ENCODER_MODE_3:
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/* counts up/down on both TI1FP1 and TI2FP2 edges */
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*action = STM32_SYNAPSE_ACTION_BOTH_EDGES;
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break;
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}
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return 0;
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}
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static const struct counter_ops stm32_timer_cnt_ops = {
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.count_read = stm32_count_read,
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.count_write = stm32_count_write,
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.function_get = stm32_count_function_get,
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.function_set = stm32_count_function_set,
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.action_get = stm32_action_get,
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};
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static struct counter_signal stm32_signals[] = {
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{
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.id = 0,
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.name = "Channel 1 Quadrature A"
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},
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{
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.id = 1,
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.name = "Channel 1 Quadrature B"
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}
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};
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static struct counter_synapse stm32_count_synapses[] = {
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{
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.actions_list = stm32_synapse_actions,
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.num_actions = ARRAY_SIZE(stm32_synapse_actions),
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.signal = &stm32_signals[0]
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},
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{
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.actions_list = stm32_synapse_actions,
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.num_actions = ARRAY_SIZE(stm32_synapse_actions),
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.signal = &stm32_signals[1]
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}
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};
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static struct counter_count stm32_counts = {
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.id = 0,
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.name = "Channel 1 Count",
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.functions_list = stm32_count_functions,
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.num_functions = ARRAY_SIZE(stm32_count_functions),
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.synapses = stm32_count_synapses,
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.num_synapses = ARRAY_SIZE(stm32_count_synapses),
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.ext = stm32_count_ext,
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.num_ext = ARRAY_SIZE(stm32_count_ext)
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};
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static int stm32_timer_cnt_probe(struct platform_device *pdev)
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{
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struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
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struct device *dev = &pdev->dev;
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struct stm32_timer_cnt *priv;
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if (IS_ERR_OR_NULL(ddata))
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return -EINVAL;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->regmap = ddata->regmap;
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priv->clk = ddata->clk;
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priv->ceiling = ddata->max_arr;
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priv->counter.name = dev_name(dev);
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priv->counter.parent = dev;
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priv->counter.ops = &stm32_timer_cnt_ops;
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priv->counter.counts = &stm32_counts;
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priv->counter.num_counts = 1;
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priv->counter.signals = stm32_signals;
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priv->counter.num_signals = ARRAY_SIZE(stm32_signals);
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priv->counter.priv = priv;
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/* Register Counter device */
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return devm_counter_register(dev, &priv->counter);
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}
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static const struct of_device_id stm32_timer_cnt_of_match[] = {
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{ .compatible = "st,stm32-timer-counter", },
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{},
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};
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MODULE_DEVICE_TABLE(of, stm32_timer_cnt_of_match);
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static struct platform_driver stm32_timer_cnt_driver = {
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.probe = stm32_timer_cnt_probe,
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.driver = {
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.name = "stm32-timer-counter",
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.of_match_table = stm32_timer_cnt_of_match,
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},
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};
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module_platform_driver(stm32_timer_cnt_driver);
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MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
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MODULE_ALIAS("platform:stm32-timer-counter");
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MODULE_DESCRIPTION("STMicroelectronics STM32 TIMER counter driver");
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MODULE_LICENSE("GPL v2");
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