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perf vendor events arm64: Fixup ThunderX2 to use recommended events 

This patch fixes the Cavium ThunderX2 JSON to use event definitions from
the ARMv8 recommended events.

Signed-off-by: John Garry <john.garry@huawei.com>
Tested-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: William Cohen <wcohen@redhat.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linuxarm@huawei.com
Link: http://lkml.kernel.org/r/1520506716-197429-10-git-send-email-john.garry@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
John Garry 2018-03-08 18:58:34 +08:00 committed by Arnaldo Carvalho de Melo
parent 360b7b03af
commit ae43053bd2
1 changed files with 10 additions and 40 deletions
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50
tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
View File

@ -1,62 +1,32 @@
[ [
{ {
"PublicDescription": "Attributable Level 1 data cache access, read", "ArchStdEvent": "L1D_CACHE_RD",
"EventCode": "0x40",
"EventName": "l1d_cache_rd",
"BriefDescription": "L1D cache read",
}, },
{ {
"PublicDescription": "Attributable Level 1 data cache access, write ", "ArchStdEvent": "L1D_CACHE_WR",
"EventCode": "0x41",
"EventName": "l1d_cache_wr",
"BriefDescription": "L1D cache write",
}, },
{ {
"PublicDescription": "Attributable Level 1 data cache refill, read", "ArchStdEvent": "L1D_CACHE_REFILL_RD",
"EventCode": "0x42",
"EventName": "l1d_cache_refill_rd",
"BriefDescription": "L1D cache refill read",
}, },
{ {
"PublicDescription": "Attributable Level 1 data cache refill, write", "ArchStdEvent": "L1D_CACHE_REFILL_WR",
"EventCode": "0x43",
"EventName": "l1d_cache_refill_wr",
"BriefDescription": "L1D refill write",
}, },
{ {
"PublicDescription": "Attributable Level 1 data TLB refill, read", "ArchStdEvent": "L1D_TLB_REFILL_RD",
"EventCode": "0x4C",
"EventName": "l1d_tlb_refill_rd",
"BriefDescription": "L1D tlb refill read",
}, },
{ {
"PublicDescription": "Attributable Level 1 data TLB refill, write", "ArchStdEvent": "L1D_TLB_REFILL_WR",
"EventCode": "0x4D",
"EventName": "l1d_tlb_refill_wr",
"BriefDescription": "L1D tlb refill write",
}, },
{ {
"PublicDescription": "Attributable Level 1 data or unified TLB access, read", "ArchStdEvent": "L1D_TLB_RD",
"EventCode": "0x4E",
"EventName": "l1d_tlb_rd",
"BriefDescription": "L1D tlb read",
}, },
{ {
"PublicDescription": "Attributable Level 1 data or unified TLB access, write", "ArchStdEvent": "L1D_TLB_WR",
"EventCode": "0x4F",
"EventName": "l1d_tlb_wr",
"BriefDescription": "L1D tlb write",
}, },
{ {
"PublicDescription": "Bus access read", "ArchStdEvent": "BUS_ACCESS_RD",
"EventCode": "0x60",
"EventName": "bus_access_rd",
"BriefDescription": "Bus access read",
}, },
{ {
"PublicDescription": "Bus access write", "ArchStdEvent": "BUS_ACCESS_WR",
"EventCode": "0x61",
"EventName": "bus_access_wr",
"BriefDescription": "Bus access write",
} }
] ]