Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS fixes from Ralf Baechle:
"A collection of fixes pretty much across the MIPS code. Even the
change to include/linux/signal.h by David Howells' 2a1486981c
("Fix
breakage in MIPS siginfo handling") should be considered MIPS-specific
as it touches an ifdefed segment that is only relevant to MIPS and
which unfortunately can't be made to go away entirely."
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
Fix breakage in MIPS siginfo handling
Revert "MIPS: BCM63XX: Call board_register_device from device_initcall()"
MIPS: BCM63XX: Make nvram checksum failure non fatal
MIPS: Fix code generation for non-DSP capable CPUs
MIPS: Fix inconsistent formatting inside /proc/cpuinfo
MIPS: SEAD3: Enable LL/SC.
MIPS: Get rid of CONFIG_CPU_HAS_LLSC again
MIPS: Add dependencies for HAVE_ARCH_TRANSPARENT_HUGEPAGE
MIPS: VR4133: Fix probe for LL/SC.
MIPS: Fix logic errors in bitops.c
MIPS: Use CONFIG_CPU_MIPSR2 in csum_partial.S
MIPS: compat: Return same error ENOSYS as native for invalid operation.
This commit is contained in:
commit
aea7fab8ba
|
@ -18,7 +18,7 @@ config MIPS
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select HAVE_KRETPROBES
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select HAVE_KRETPROBES
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select HAVE_DEBUG_KMEMLEAK
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select HAVE_DEBUG_KMEMLEAK
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select ARCH_BINFMT_ELF_RANDOMIZE_PIE
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select ARCH_BINFMT_ELF_RANDOMIZE_PIE
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select HAVE_ARCH_TRANSPARENT_HUGEPAGE
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select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT
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select RTC_LIB if !MACH_LOONGSON
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select RTC_LIB if !MACH_LOONGSON
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select GENERIC_ATOMIC64 if !64BIT
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select GENERIC_ATOMIC64 if !64BIT
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select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
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select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
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@ -1493,7 +1493,6 @@ config CPU_XLP
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select CPU_SUPPORTS_32BIT_KERNEL
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select CPU_SUPPORTS_32BIT_KERNEL
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select CPU_SUPPORTS_64BIT_KERNEL
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select CPU_SUPPORTS_64BIT_KERNEL
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select CPU_SUPPORTS_HIGHMEM
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select CPU_SUPPORTS_HIGHMEM
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select CPU_HAS_LLSC
|
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select WEAK_ORDERING
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select WEAK_ORDERING
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select WEAK_REORDERING_BEYOND_LLSC
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select WEAK_REORDERING_BEYOND_LLSC
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select CPU_HAS_PREFETCH
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select CPU_HAS_PREFETCH
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|
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@ -745,10 +745,7 @@ void __init board_prom_init(void)
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strcpy(cfe_version, "unknown");
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strcpy(cfe_version, "unknown");
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printk(KERN_INFO PFX "CFE version: %s\n", cfe_version);
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printk(KERN_INFO PFX "CFE version: %s\n", cfe_version);
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if (bcm63xx_nvram_init(boot_addr + BCM963XX_NVRAM_OFFSET)) {
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bcm63xx_nvram_init(boot_addr + BCM963XX_NVRAM_OFFSET);
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printk(KERN_ERR PFX "invalid nvram checksum\n");
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return;
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}
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board_name = bcm63xx_nvram_get_name();
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board_name = bcm63xx_nvram_get_name();
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/* find board by name */
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/* find board by name */
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@ -38,7 +38,7 @@ struct bcm963xx_nvram {
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static struct bcm963xx_nvram nvram;
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static struct bcm963xx_nvram nvram;
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static int mac_addr_used;
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static int mac_addr_used;
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int __init bcm63xx_nvram_init(void *addr)
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void __init bcm63xx_nvram_init(void *addr)
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{
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{
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unsigned int check_len;
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unsigned int check_len;
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u32 crc, expected_crc;
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u32 crc, expected_crc;
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@ -60,9 +60,8 @@ int __init bcm63xx_nvram_init(void *addr)
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crc = crc32_le(~0, (u8 *)&nvram, check_len);
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crc = crc32_le(~0, (u8 *)&nvram, check_len);
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if (crc != expected_crc)
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if (crc != expected_crc)
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return -EINVAL;
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pr_warn("nvram checksum failed, contents may be invalid (expected %08x, got %08x)\n",
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expected_crc, crc);
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return 0;
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}
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}
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u8 *bcm63xx_nvram_get_name(void)
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u8 *bcm63xx_nvram_get_name(void)
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|
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@ -157,4 +157,4 @@ int __init bcm63xx_register_devices(void)
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return board_register_devices();
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return board_register_devices();
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}
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}
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|
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device_initcall(bcm63xx_register_devices);
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arch_initcall(bcm63xx_register_devices);
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|
|
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@ -9,10 +9,8 @@
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*
|
*
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* Initialized the local nvram copy from the target address and checks
|
* Initialized the local nvram copy from the target address and checks
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* its checksum.
|
* its checksum.
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*
|
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* Returns 0 on success.
|
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*/
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*/
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int __init bcm63xx_nvram_init(void *nvram);
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void bcm63xx_nvram_init(void *nvram);
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|
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/**
|
/**
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* bcm63xx_nvram_get_name() - returns the board name according to nvram
|
* bcm63xx_nvram_get_name() - returns the board name according to nvram
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|
|
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@ -28,11 +28,7 @@
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/* #define cpu_has_prefetch ? */
|
/* #define cpu_has_prefetch ? */
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#define cpu_has_mcheck 1
|
#define cpu_has_mcheck 1
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/* #define cpu_has_ejtag ? */
|
/* #define cpu_has_ejtag ? */
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#ifdef CONFIG_CPU_HAS_LLSC
|
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||||||
#define cpu_has_llsc 1
|
#define cpu_has_llsc 1
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#else
|
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||||||
#define cpu_has_llsc 0
|
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||||||
#endif
|
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||||||
/* #define cpu_has_vtag_icache ? */
|
/* #define cpu_has_vtag_icache ? */
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||||||
/* #define cpu_has_dc_aliases ? */
|
/* #define cpu_has_dc_aliases ? */
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||||||
/* #define cpu_has_ic_fills_f_dc ? */
|
/* #define cpu_has_ic_fills_f_dc ? */
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||||||
|
|
|
@ -1166,7 +1166,10 @@ do { \
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unsigned int __dspctl; \
|
unsigned int __dspctl; \
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\
|
\
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__asm__ __volatile__( \
|
__asm__ __volatile__( \
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|
" .set push \n" \
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|
" .set dsp \n" \
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" rddsp %0, %x1 \n" \
|
" rddsp %0, %x1 \n" \
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||||||
|
" .set pop \n" \
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||||||
: "=r" (__dspctl) \
|
: "=r" (__dspctl) \
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: "i" (mask)); \
|
: "i" (mask)); \
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__dspctl; \
|
__dspctl; \
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|
@ -1175,30 +1178,198 @@ do { \
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#define wrdsp(val, mask) \
|
#define wrdsp(val, mask) \
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do { \
|
do { \
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__asm__ __volatile__( \
|
__asm__ __volatile__( \
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||||||
|
" .set push \n" \
|
||||||
|
" .set dsp \n" \
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||||||
" wrdsp %0, %x1 \n" \
|
" wrdsp %0, %x1 \n" \
|
||||||
|
" .set pop \n" \
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||||||
: \
|
: \
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||||||
: "r" (val), "i" (mask)); \
|
: "r" (val), "i" (mask)); \
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||||||
} while (0)
|
} while (0)
|
||||||
|
|
||||||
#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
|
#define mflo0() \
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#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
|
({ \
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||||||
#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
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long mflo0; \
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#define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
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__asm__( \
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||||||
|
" .set push \n" \
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||||||
|
" .set dsp \n" \
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||||||
|
" mflo %0, $ac0 \n" \
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||||||
|
" .set pop \n" \
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||||||
|
: "=r" (mflo0)); \
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||||||
|
mflo0; \
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||||||
|
})
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||||||
|
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||||||
#define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
|
#define mflo1() \
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#define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
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({ \
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||||||
#define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
|
long mflo1; \
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||||||
#define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
|
__asm__( \
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||||||
|
" .set push \n" \
|
||||||
|
" .set dsp \n" \
|
||||||
|
" mflo %0, $ac1 \n" \
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||||||
|
" .set pop \n" \
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||||||
|
: "=r" (mflo1)); \
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||||||
|
mflo1; \
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||||||
|
})
|
||||||
|
|
||||||
#define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
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#define mflo2() \
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#define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
|
({ \
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||||||
#define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
|
long mflo2; \
|
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#define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
|
__asm__( \
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||||||
|
" .set push \n" \
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||||||
|
" .set dsp \n" \
|
||||||
|
" mflo %0, $ac2 \n" \
|
||||||
|
" .set pop \n" \
|
||||||
|
: "=r" (mflo2)); \
|
||||||
|
mflo2; \
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||||||
|
})
|
||||||
|
|
||||||
#define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
|
#define mflo3() \
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#define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
|
({ \
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||||||
#define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
|
long mflo3; \
|
||||||
#define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
|
__asm__( \
|
||||||
|
" .set push \n" \
|
||||||
|
" .set dsp \n" \
|
||||||
|
" mflo %0, $ac3 \n" \
|
||||||
|
" .set pop \n" \
|
||||||
|
: "=r" (mflo3)); \
|
||||||
|
mflo3; \
|
||||||
|
})
|
||||||
|
|
||||||
|
#define mfhi0() \
|
||||||
|
({ \
|
||||||
|
long mfhi0; \
|
||||||
|
__asm__( \
|
||||||
|
" .set push \n" \
|
||||||
|
" .set dsp \n" \
|
||||||
|
" mfhi %0, $ac0 \n" \
|
||||||
|
" .set pop \n" \
|
||||||
|
: "=r" (mfhi0)); \
|
||||||
|
mfhi0; \
|
||||||
|
})
|
||||||
|
|
||||||
|
#define mfhi1() \
|
||||||
|
({ \
|
||||||
|
long mfhi1; \
|
||||||
|
__asm__( \
|
||||||
|
" .set push \n" \
|
||||||
|
" .set dsp \n" \
|
||||||
|
" mfhi %0, $ac1 \n" \
|
||||||
|
" .set pop \n" \
|
||||||
|
: "=r" (mfhi1)); \
|
||||||
|
mfhi1; \
|
||||||
|
})
|
||||||
|
|
||||||
|
#define mfhi2() \
|
||||||
|
({ \
|
||||||
|
long mfhi2; \
|
||||||
|
__asm__( \
|
||||||
|
" .set push \n" \
|
||||||
|
" .set dsp \n" \
|
||||||
|
" mfhi %0, $ac2 \n" \
|
||||||
|
" .set pop \n" \
|
||||||
|
: "=r" (mfhi2)); \
|
||||||
|
mfhi2; \
|
||||||
|
})
|
||||||
|
|
||||||
|
#define mfhi3() \
|
||||||
|
({ \
|
||||||
|
long mfhi3; \
|
||||||
|
__asm__( \
|
||||||
|
" .set push \n" \
|
||||||
|
" .set dsp \n" \
|
||||||
|
" mfhi %0, $ac3 \n" \
|
||||||
|
" .set pop \n" \
|
||||||
|
: "=r" (mfhi3)); \
|
||||||
|
mfhi3; \
|
||||||
|
})
|
||||||
|
|
||||||
|
|
||||||
|
#define mtlo0(x) \
|
||||||
|
({ \
|
||||||
|
__asm__( \
|
||||||
|
" .set push \n" \
|
||||||
|
" .set dsp \n" \
|
||||||
|
" mtlo %0, $ac0 \n" \
|
||||||
|
" .set pop \n" \
|
||||||
|
: \
|
||||||
|
: "r" (x)); \
|
||||||
|
})
|
||||||
|
|
||||||
|
#define mtlo1(x) \
|
||||||
|
({ \
|
||||||
|
__asm__( \
|
||||||
|
" .set push \n" \
|
||||||
|
" .set dsp \n" \
|
||||||
|
" mtlo %0, $ac1 \n" \
|
||||||
|
" .set pop \n" \
|
||||||
|
: \
|
||||||
|
: "r" (x)); \
|
||||||
|
})
|
||||||
|
|
||||||
|
#define mtlo2(x) \
|
||||||
|
({ \
|
||||||
|
__asm__( \
|
||||||
|
" .set push \n" \
|
||||||
|
" .set dsp \n" \
|
||||||
|
" mtlo %0, $ac2 \n" \
|
||||||
|
" .set pop \n" \
|
||||||
|
: \
|
||||||
|
: "r" (x)); \
|
||||||
|
})
|
||||||
|
|
||||||
|
#define mtlo3(x) \
|
||||||
|
({ \
|
||||||
|
__asm__( \
|
||||||
|
" .set push \n" \
|
||||||
|
" .set dsp \n" \
|
||||||
|
" mtlo %0, $ac3 \n" \
|
||||||
|
" .set pop \n" \
|
||||||
|
: \
|
||||||
|
: "r" (x)); \
|
||||||
|
})
|
||||||
|
|
||||||
|
#define mthi0(x) \
|
||||||
|
({ \
|
||||||
|
__asm__( \
|
||||||
|
" .set push \n" \
|
||||||
|
" .set dsp \n" \
|
||||||
|
" mthi %0, $ac0 \n" \
|
||||||
|
" .set pop \n" \
|
||||||
|
: \
|
||||||
|
: "r" (x)); \
|
||||||
|
})
|
||||||
|
|
||||||
|
#define mthi1(x) \
|
||||||
|
({ \
|
||||||
|
__asm__( \
|
||||||
|
" .set push \n" \
|
||||||
|
" .set dsp \n" \
|
||||||
|
" mthi %0, $ac1 \n" \
|
||||||
|
" .set pop \n" \
|
||||||
|
: \
|
||||||
|
: "r" (x)); \
|
||||||
|
})
|
||||||
|
|
||||||
|
#define mthi2(x) \
|
||||||
|
({ \
|
||||||
|
__asm__( \
|
||||||
|
" .set push \n" \
|
||||||
|
" .set dsp \n" \
|
||||||
|
" mthi %0, $ac2 \n" \
|
||||||
|
" .set pop \n" \
|
||||||
|
: \
|
||||||
|
: "r" (x)); \
|
||||||
|
})
|
||||||
|
|
||||||
|
#define mthi3(x) \
|
||||||
|
({ \
|
||||||
|
__asm__( \
|
||||||
|
" .set push \n" \
|
||||||
|
" .set dsp \n" \
|
||||||
|
" mthi %0, $ac3 \n" \
|
||||||
|
" .set pop \n" \
|
||||||
|
: \
|
||||||
|
: "r" (x)); \
|
||||||
|
})
|
||||||
|
|
||||||
#else
|
#else
|
||||||
|
|
||||||
|
|
|
@ -21,6 +21,6 @@
|
||||||
#include <asm/sigcontext.h>
|
#include <asm/sigcontext.h>
|
||||||
#include <asm/siginfo.h>
|
#include <asm/siginfo.h>
|
||||||
|
|
||||||
#define __ARCH_HAS_ODD_SIGACTION
|
#define __ARCH_HAS_IRIX_SIGACTION
|
||||||
|
|
||||||
#endif /* _ASM_SIGNAL_H */
|
#endif /* _ASM_SIGNAL_H */
|
||||||
|
|
|
@ -100,29 +100,16 @@ obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_mipsxx.o
|
||||||
obj-$(CONFIG_JUMP_LABEL) += jump_label.o
|
obj-$(CONFIG_JUMP_LABEL) += jump_label.o
|
||||||
|
|
||||||
#
|
#
|
||||||
# DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only. It is safe
|
# DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only. It is not
|
||||||
# to enable DSP assembler support here even if the MIPS Release 2 CPU we
|
# safe to unconditionnaly use the assembler -mdsp / -mdspr2 switches
|
||||||
# are targetting does not support DSP because all code-paths making use of
|
# here because the compiler may use DSP ASE instructions (such as lwx) in
|
||||||
# it properly check that the running CPU *actually does* support these
|
# code paths where we cannot check that the CPU we are running on supports it.
|
||||||
# instructions.
|
# Proper abstraction using HAVE_AS_DSP and macros is done in
|
||||||
|
# arch/mips/include/asm/mipsregs.h.
|
||||||
#
|
#
|
||||||
ifeq ($(CONFIG_CPU_MIPSR2), y)
|
ifeq ($(CONFIG_CPU_MIPSR2), y)
|
||||||
CFLAGS_DSP = -DHAVE_AS_DSP
|
CFLAGS_DSP = -DHAVE_AS_DSP
|
||||||
|
|
||||||
#
|
|
||||||
# Check if assembler supports DSP ASE
|
|
||||||
#
|
|
||||||
ifeq ($(call cc-option-yn,-mdsp), y)
|
|
||||||
CFLAGS_DSP += -mdsp
|
|
||||||
endif
|
|
||||||
|
|
||||||
#
|
|
||||||
# Check if assembler supports DSP ASE Rev2
|
|
||||||
#
|
|
||||||
ifeq ($(call cc-option-yn,-mdspr2), y)
|
|
||||||
CFLAGS_DSP += -mdspr2
|
|
||||||
endif
|
|
||||||
|
|
||||||
CFLAGS_signal.o = $(CFLAGS_DSP)
|
CFLAGS_signal.o = $(CFLAGS_DSP)
|
||||||
CFLAGS_signal32.o = $(CFLAGS_DSP)
|
CFLAGS_signal32.o = $(CFLAGS_DSP)
|
||||||
CFLAGS_process.o = $(CFLAGS_DSP)
|
CFLAGS_process.o = $(CFLAGS_DSP)
|
||||||
|
|
|
@ -580,6 +580,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
||||||
c->tlbsize = 48;
|
c->tlbsize = 48;
|
||||||
break;
|
break;
|
||||||
case PRID_IMP_VR41XX:
|
case PRID_IMP_VR41XX:
|
||||||
|
set_isa(c, MIPS_CPU_ISA_III);
|
||||||
|
c->options = R4K_OPTS;
|
||||||
|
c->tlbsize = 32;
|
||||||
switch (c->processor_id & 0xf0) {
|
switch (c->processor_id & 0xf0) {
|
||||||
case PRID_REV_VR4111:
|
case PRID_REV_VR4111:
|
||||||
c->cputype = CPU_VR4111;
|
c->cputype = CPU_VR4111;
|
||||||
|
@ -604,6 +607,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
||||||
__cpu_name[cpu] = "NEC VR4131";
|
__cpu_name[cpu] = "NEC VR4131";
|
||||||
} else {
|
} else {
|
||||||
c->cputype = CPU_VR4133;
|
c->cputype = CPU_VR4133;
|
||||||
|
c->options |= MIPS_CPU_LLSC;
|
||||||
__cpu_name[cpu] = "NEC VR4133";
|
__cpu_name[cpu] = "NEC VR4133";
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
|
@ -613,9 +617,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
||||||
__cpu_name[cpu] = "NEC Vr41xx";
|
__cpu_name[cpu] = "NEC Vr41xx";
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
set_isa(c, MIPS_CPU_ISA_III);
|
|
||||||
c->options = R4K_OPTS;
|
|
||||||
c->tlbsize = 32;
|
|
||||||
break;
|
break;
|
||||||
case PRID_IMP_R4300:
|
case PRID_IMP_R4300:
|
||||||
c->cputype = CPU_R4300;
|
c->cputype = CPU_R4300;
|
||||||
|
|
|
@ -171,7 +171,7 @@ SYSCALL_DEFINE6(32_ipc, u32, call, long, first, long, second, long, third,
|
||||||
err = compat_sys_shmctl(first, second, compat_ptr(ptr));
|
err = compat_sys_shmctl(first, second, compat_ptr(ptr));
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
err = -EINVAL;
|
err = -ENOSYS;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -67,7 +67,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
|
||||||
if (cpu_has_mips_r) {
|
if (cpu_has_mips_r) {
|
||||||
seq_printf(m, "isa\t\t\t:");
|
seq_printf(m, "isa\t\t\t:");
|
||||||
if (cpu_has_mips_1)
|
if (cpu_has_mips_1)
|
||||||
seq_printf(m, "%s", "mips1");
|
seq_printf(m, "%s", " mips1");
|
||||||
if (cpu_has_mips_2)
|
if (cpu_has_mips_2)
|
||||||
seq_printf(m, "%s", " mips2");
|
seq_printf(m, "%s", " mips2");
|
||||||
if (cpu_has_mips_3)
|
if (cpu_has_mips_3)
|
||||||
|
|
|
@ -90,12 +90,12 @@ int __mips_test_and_set_bit(unsigned long nr,
|
||||||
unsigned bit = nr & SZLONG_MASK;
|
unsigned bit = nr & SZLONG_MASK;
|
||||||
unsigned long mask;
|
unsigned long mask;
|
||||||
unsigned long flags;
|
unsigned long flags;
|
||||||
unsigned long res;
|
int res;
|
||||||
|
|
||||||
a += nr >> SZLONG_LOG;
|
a += nr >> SZLONG_LOG;
|
||||||
mask = 1UL << bit;
|
mask = 1UL << bit;
|
||||||
raw_local_irq_save(flags);
|
raw_local_irq_save(flags);
|
||||||
res = (mask & *a);
|
res = (mask & *a) != 0;
|
||||||
*a |= mask;
|
*a |= mask;
|
||||||
raw_local_irq_restore(flags);
|
raw_local_irq_restore(flags);
|
||||||
return res;
|
return res;
|
||||||
|
@ -116,12 +116,12 @@ int __mips_test_and_set_bit_lock(unsigned long nr,
|
||||||
unsigned bit = nr & SZLONG_MASK;
|
unsigned bit = nr & SZLONG_MASK;
|
||||||
unsigned long mask;
|
unsigned long mask;
|
||||||
unsigned long flags;
|
unsigned long flags;
|
||||||
unsigned long res;
|
int res;
|
||||||
|
|
||||||
a += nr >> SZLONG_LOG;
|
a += nr >> SZLONG_LOG;
|
||||||
mask = 1UL << bit;
|
mask = 1UL << bit;
|
||||||
raw_local_irq_save(flags);
|
raw_local_irq_save(flags);
|
||||||
res = (mask & *a);
|
res = (mask & *a) != 0;
|
||||||
*a |= mask;
|
*a |= mask;
|
||||||
raw_local_irq_restore(flags);
|
raw_local_irq_restore(flags);
|
||||||
return res;
|
return res;
|
||||||
|
@ -141,12 +141,12 @@ int __mips_test_and_clear_bit(unsigned long nr, volatile unsigned long *addr)
|
||||||
unsigned bit = nr & SZLONG_MASK;
|
unsigned bit = nr & SZLONG_MASK;
|
||||||
unsigned long mask;
|
unsigned long mask;
|
||||||
unsigned long flags;
|
unsigned long flags;
|
||||||
unsigned long res;
|
int res;
|
||||||
|
|
||||||
a += nr >> SZLONG_LOG;
|
a += nr >> SZLONG_LOG;
|
||||||
mask = 1UL << bit;
|
mask = 1UL << bit;
|
||||||
raw_local_irq_save(flags);
|
raw_local_irq_save(flags);
|
||||||
res = (mask & *a);
|
res = (mask & *a) != 0;
|
||||||
*a &= ~mask;
|
*a &= ~mask;
|
||||||
raw_local_irq_restore(flags);
|
raw_local_irq_restore(flags);
|
||||||
return res;
|
return res;
|
||||||
|
@ -166,12 +166,12 @@ int __mips_test_and_change_bit(unsigned long nr, volatile unsigned long *addr)
|
||||||
unsigned bit = nr & SZLONG_MASK;
|
unsigned bit = nr & SZLONG_MASK;
|
||||||
unsigned long mask;
|
unsigned long mask;
|
||||||
unsigned long flags;
|
unsigned long flags;
|
||||||
unsigned long res;
|
int res;
|
||||||
|
|
||||||
a += nr >> SZLONG_LOG;
|
a += nr >> SZLONG_LOG;
|
||||||
mask = 1UL << bit;
|
mask = 1UL << bit;
|
||||||
raw_local_irq_save(flags);
|
raw_local_irq_save(flags);
|
||||||
res = (mask & *a);
|
res = (mask & *a) != 0;
|
||||||
*a ^= mask;
|
*a ^= mask;
|
||||||
raw_local_irq_restore(flags);
|
raw_local_irq_restore(flags);
|
||||||
return res;
|
return res;
|
||||||
|
|
|
@ -270,7 +270,7 @@ LEAF(csum_partial)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* odd buffer alignment? */
|
/* odd buffer alignment? */
|
||||||
#ifdef CPU_MIPSR2
|
#ifdef CONFIG_CPU_MIPSR2
|
||||||
wsbh v1, sum
|
wsbh v1, sum
|
||||||
movn sum, v1, t7
|
movn sum, v1, t7
|
||||||
#else
|
#else
|
||||||
|
@ -670,7 +670,7 @@ EXC( sb t0, NBYTES-2(dst), .Ls_exc)
|
||||||
addu sum, v1
|
addu sum, v1
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CPU_MIPSR2
|
#ifdef CONFIG_CPU_MIPSR2
|
||||||
wsbh v1, sum
|
wsbh v1, sum
|
||||||
movn sum, v1, odd
|
movn sum, v1, odd
|
||||||
#else
|
#else
|
||||||
|
|
|
@ -141,11 +141,11 @@ typedef struct {
|
||||||
} compat_sigset_t;
|
} compat_sigset_t;
|
||||||
|
|
||||||
struct compat_sigaction {
|
struct compat_sigaction {
|
||||||
#ifndef __ARCH_HAS_ODD_SIGACTION
|
#ifndef __ARCH_HAS_IRIX_SIGACTION
|
||||||
compat_uptr_t sa_handler;
|
compat_uptr_t sa_handler;
|
||||||
compat_ulong_t sa_flags;
|
compat_ulong_t sa_flags;
|
||||||
#else
|
#else
|
||||||
compat_ulong_t sa_flags;
|
compat_uint_t sa_flags;
|
||||||
compat_uptr_t sa_handler;
|
compat_uptr_t sa_handler;
|
||||||
#endif
|
#endif
|
||||||
#ifdef __ARCH_HAS_SA_RESTORER
|
#ifdef __ARCH_HAS_SA_RESTORER
|
||||||
|
|
|
@ -250,11 +250,11 @@ extern int show_unhandled_signals;
|
||||||
extern int sigsuspend(sigset_t *);
|
extern int sigsuspend(sigset_t *);
|
||||||
|
|
||||||
struct sigaction {
|
struct sigaction {
|
||||||
#ifndef __ARCH_HAS_ODD_SIGACTION
|
#ifndef __ARCH_HAS_IRIX_SIGACTION
|
||||||
__sighandler_t sa_handler;
|
__sighandler_t sa_handler;
|
||||||
unsigned long sa_flags;
|
unsigned long sa_flags;
|
||||||
#else
|
#else
|
||||||
unsigned long sa_flags;
|
unsigned int sa_flags;
|
||||||
__sighandler_t sa_handler;
|
__sighandler_t sa_handler;
|
||||||
#endif
|
#endif
|
||||||
#ifdef __ARCH_HAS_SA_RESTORER
|
#ifdef __ARCH_HAS_SA_RESTORER
|
||||||
|
|
Loading…
Reference in New Issue