Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle: o Add basic support for the Mediatek/Ralink Wireless SoC family. o The Qualcomm Atheros platform is extended by support for the new QCA955X SoC series as well as a bunch of patches that get the code ready for OF support. o Lantiq and BCM47XX platform have a few improvements and bug fixes. o MIPS has sent a few patches that get the kernel ready for the upcoming microMIPS support. o The rest of the series is made up of small bug fixes and cleanups that relate to various parts of the MIPS code. The biggy in there is a whitespace cleanup. After I was sent another set of whitespace cleanup patches I decided it was the time to clean the whitespace "issues" for once and and that touches many files below arch/mips/. Fix up silly conflicts, mostly due to whitespace cleanups. * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (105 commits) MIPS: Quit exporting kernel internel break codes to uapi/asm/break.h MIPS: remove broken conditional inside vpe loader code MIPS: SMTC: fix implicit declaration of set_vi_handler MIPS: early_printk: drop __init annotations MIPS: Probe for and report hardware virtualization support. MIPS: ath79: add support for the Qualcomm Atheros AP136-010 board MIPS: ath79: add USB controller registration code for the QCA955X SoCs MIPS: ath79: add PCI controller registration code for the QCA955X SoCs MIPS: ath79: add WMAC registration code for the QCA955X SoCs MIPS: ath79: register UART for the QCA955X SoCs MIPS: ath79: add QCA955X specific glue to ath79_device_reset_{set, clear} MIPS: ath79: add GPIO setup code for the QCA955X SoCs MIPS: ath79: add IRQ handling code for the QCA955X SoCs MIPS: ath79: add clock setup code for the QCA955X SoCs MIPS: ath79: add SoC detection code for the QCA955X SoCs MIPS: ath79: add early printk support for the QCA955X SoCs MIPS: ath79: fix WMAC IRQ resource assignment mips: reserve elfcorehdr mips: Make sure kernel memory is in iomem MIPS: ath79: use dynamically allocated USB platform devices ...
This commit is contained in:
commit
aebb2afd54
|
@ -0,0 +1,47 @@
|
|||
MIPS CPU interrupt controller
|
||||
|
||||
On MIPS the mips_cpu_intc_init() helper can be used to initialize the 8 CPU
|
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IRQs from a devicetree file and create a irq_domain for IRQ controller.
|
||||
|
||||
With the irq_domain in place we can describe how the 8 IRQs are wired to the
|
||||
platforms internal interrupt controller cascade.
|
||||
|
||||
Below is an example of a platform describing the cascade inside the devicetree
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and the code used to load it inside arch_init_irq().
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||||
|
||||
Required properties:
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- compatible : Should be "mti,cpu-interrupt-controller"
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||||
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Example devicetree:
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cpu-irq: cpu-irq@0 {
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#address-cells = <0>;
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interrupt-controller;
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#interrupt-cells = <1>;
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compatible = "mti,cpu-interrupt-controller";
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};
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intc: intc@200 {
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compatible = "ralink,rt2880-intc";
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reg = <0x200 0x100>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpu-irq>;
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interrupts = <2>;
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};
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Example platform irq.c:
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static struct of_device_id __initdata of_irq_ids[] = {
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{ .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init },
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{ .compatible = "ralink,rt2880-intc", .data = intc_of_init },
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{},
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};
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void __init arch_init_irq(void)
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{
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of_irq_init(of_irq_ids);
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}
|
|
@ -0,0 +1,16 @@
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|||
Lantiq SoC ASC serial controller
|
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|
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Required properties:
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- compatible : Should be "lantiq,asc"
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- reg : Address and length of the register set for the device
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- interrupts: the 3 (tx rx err) interrupt numbers. The interrupt specifier
|
||||
depends on the interrupt-parent interrupt controller.
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||||
|
||||
Example:
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|
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asc1: serial@E100C00 {
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compatible = "lantiq,asc";
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reg = <0xE100C00 0x400>;
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interrupt-parent = <&icu0>;
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interrupts = <112 113 114>;
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};
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|
@ -18,10 +18,10 @@ platforms += loongson1
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platforms += mti-malta
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platforms += mti-sead3
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platforms += netlogic
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platforms += pmc-sierra
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platforms += pmcs-msp71xx
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platforms += pnx833x
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platforms += pnx8550
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platforms += powertv
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platforms += ralink
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platforms += rb532
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platforms += sgi-ip22
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platforms += sgi-ip27
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|
|
|
@ -108,12 +108,14 @@ config ATH79
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config BCM47XX
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bool "Broadcom BCM47XX based boards"
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select ARCH_WANT_OPTIONAL_GPIOLIB
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select BOOT_RAW
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select CEVT_R4K
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select CSRC_R4K
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select DMA_NONCOHERENT
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select FW_CFE
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select HW_HAS_PCI
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select IRQ_CPU
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select NO_EXCEPT_FILL
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select SYS_HAS_EARLY_PRINTK
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|
@ -295,6 +297,7 @@ config MIPS_MALTA
|
|||
select BOOT_RAW
|
||||
select CEVT_R4K
|
||||
select CSRC_R4K
|
||||
select CSRC_GIC
|
||||
select DMA_NONCOHERENT
|
||||
select GENERIC_ISA_DMA
|
||||
select HAVE_PCSPKR_PLATFORM
|
||||
|
@ -354,6 +357,7 @@ config MIPS_SEAD3
|
|||
select USB_ARCH_HAS_EHCI
|
||||
select USB_EHCI_BIG_ENDIAN_DESC
|
||||
select USB_EHCI_BIG_ENDIAN_MMIO
|
||||
select USE_OF
|
||||
help
|
||||
This enables support for the MIPS Technologies SEAD3 evaluation
|
||||
board.
|
||||
|
@ -385,16 +389,6 @@ config NXP_STB225
|
|||
help
|
||||
Support for NXP Semiconductors STB225 Development Board.
|
||||
|
||||
config PNX8550_JBS
|
||||
bool "NXP PNX8550 based JBS board"
|
||||
select PNX8550
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config PNX8550_STB810
|
||||
bool "NXP PNX8550 based STB810 board"
|
||||
select PNX8550
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config PMC_MSP
|
||||
bool "PMC-Sierra MSP chipsets"
|
||||
select CEVT_R4K
|
||||
|
@ -434,6 +428,22 @@ config POWERTV
|
|||
help
|
||||
This enables support for the Cisco PowerTV Platform.
|
||||
|
||||
config RALINK
|
||||
bool "Ralink based machines"
|
||||
select CEVT_R4K
|
||||
select CSRC_R4K
|
||||
select BOOT_RAW
|
||||
select DMA_NONCOHERENT
|
||||
select IRQ_CPU
|
||||
select USE_OF
|
||||
select SYS_HAS_CPU_MIPS32_R1
|
||||
select SYS_HAS_CPU_MIPS32_R2
|
||||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
select SYS_HAS_EARLY_PRINTK
|
||||
select HAVE_MACH_CLKDEV
|
||||
select CLKDEV_LOOKUP
|
||||
|
||||
config SGI_IP22
|
||||
bool "SGI IP22 (Indy/Indigo2)"
|
||||
select FW_ARC
|
||||
|
@ -835,8 +845,9 @@ source "arch/mips/jazz/Kconfig"
|
|||
source "arch/mips/jz4740/Kconfig"
|
||||
source "arch/mips/lantiq/Kconfig"
|
||||
source "arch/mips/lasat/Kconfig"
|
||||
source "arch/mips/pmc-sierra/Kconfig"
|
||||
source "arch/mips/pmcs-msp71xx/Kconfig"
|
||||
source "arch/mips/powertv/Kconfig"
|
||||
source "arch/mips/ralink/Kconfig"
|
||||
source "arch/mips/sgi-ip27/Kconfig"
|
||||
source "arch/mips/sibyte/Kconfig"
|
||||
source "arch/mips/txx9/Kconfig"
|
||||
|
@ -917,6 +928,9 @@ config CSRC_POWERTV
|
|||
config CSRC_R4K
|
||||
bool
|
||||
|
||||
config CSRC_GIC
|
||||
bool
|
||||
|
||||
config CSRC_SB1250
|
||||
bool
|
||||
|
||||
|
@ -1103,19 +1117,6 @@ config SOC_PNX8335
|
|||
bool
|
||||
select SOC_PNX833X
|
||||
|
||||
config PNX8550
|
||||
bool
|
||||
select SOC_PNX8550
|
||||
|
||||
config SOC_PNX8550
|
||||
bool
|
||||
select DMA_NONCOHERENT
|
||||
select HW_HAS_PCI
|
||||
select SYS_HAS_CPU_MIPS32_R1
|
||||
select SYS_HAS_EARLY_PRINTK
|
||||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
select GENERIC_GPIO
|
||||
|
||||
config SWAP_IO_SPACE
|
||||
bool
|
||||
|
||||
|
|
|
@ -14,6 +14,18 @@ config ATH79_MACH_AP121
|
|||
Say 'Y' here if you want your kernel to support the
|
||||
Atheros AP121 reference board.
|
||||
|
||||
config ATH79_MACH_AP136
|
||||
bool "Atheros AP136 reference board"
|
||||
select SOC_QCA955X
|
||||
select ATH79_DEV_GPIO_BUTTONS
|
||||
select ATH79_DEV_LEDS_GPIO
|
||||
select ATH79_DEV_SPI
|
||||
select ATH79_DEV_USB
|
||||
select ATH79_DEV_WMAC
|
||||
help
|
||||
Say 'Y' here if you want your kernel to support the
|
||||
Atheros AP136 reference board.
|
||||
|
||||
config ATH79_MACH_AP81
|
||||
bool "Atheros AP81 reference board"
|
||||
select SOC_AR913X
|
||||
|
@ -88,6 +100,12 @@ config SOC_AR934X
|
|||
select PCI_AR724X if PCI
|
||||
def_bool n
|
||||
|
||||
config SOC_QCA955X
|
||||
select USB_ARCH_HAS_EHCI
|
||||
select HW_HAS_PCI
|
||||
select PCI_AR724X if PCI
|
||||
def_bool n
|
||||
|
||||
config PCI_AR724X
|
||||
def_bool n
|
||||
|
||||
|
@ -104,7 +122,7 @@ config ATH79_DEV_USB
|
|||
def_bool n
|
||||
|
||||
config ATH79_DEV_WMAC
|
||||
depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X)
|
||||
depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
|
||||
def_bool n
|
||||
|
||||
endif
|
||||
|
|
|
@ -27,6 +27,7 @@ obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wmac.o
|
|||
# Machines
|
||||
#
|
||||
obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o
|
||||
obj-$(CONFIG_ATH79_MACH_AP136) += mach-ap136.o
|
||||
obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o
|
||||
obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o
|
||||
obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o
|
||||
|
|
|
@ -295,6 +295,82 @@ static void __init ar934x_clocks_init(void)
|
|||
iounmap(dpll_base);
|
||||
}
|
||||
|
||||
static void __init qca955x_clocks_init(void)
|
||||
{
|
||||
u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
|
||||
u32 cpu_pll, ddr_pll;
|
||||
u32 bootstrap;
|
||||
|
||||
bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
|
||||
if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40)
|
||||
ath79_ref_clk.rate = 40 * 1000 * 1000;
|
||||
else
|
||||
ath79_ref_clk.rate = 25 * 1000 * 1000;
|
||||
|
||||
pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
|
||||
out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
|
||||
QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
|
||||
ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
|
||||
QCA955X_PLL_CPU_CONFIG_REFDIV_MASK;
|
||||
nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
|
||||
QCA955X_PLL_CPU_CONFIG_NINT_MASK;
|
||||
frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
|
||||
QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
|
||||
|
||||
cpu_pll = nint * ath79_ref_clk.rate / ref_div;
|
||||
cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6));
|
||||
cpu_pll /= (1 << out_div);
|
||||
|
||||
pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
|
||||
out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
|
||||
QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
|
||||
ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
|
||||
QCA955X_PLL_DDR_CONFIG_REFDIV_MASK;
|
||||
nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
|
||||
QCA955X_PLL_DDR_CONFIG_NINT_MASK;
|
||||
frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
|
||||
QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
|
||||
|
||||
ddr_pll = nint * ath79_ref_clk.rate / ref_div;
|
||||
ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10));
|
||||
ddr_pll /= (1 << out_div);
|
||||
|
||||
clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
|
||||
|
||||
postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
|
||||
QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
|
||||
|
||||
if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
|
||||
ath79_cpu_clk.rate = ath79_ref_clk.rate;
|
||||
else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
|
||||
ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
|
||||
else
|
||||
ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
|
||||
|
||||
postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
|
||||
QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
|
||||
|
||||
if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
|
||||
ath79_ddr_clk.rate = ath79_ref_clk.rate;
|
||||
else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
|
||||
ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
|
||||
else
|
||||
ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
|
||||
|
||||
postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
|
||||
QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
|
||||
|
||||
if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
|
||||
ath79_ahb_clk.rate = ath79_ref_clk.rate;
|
||||
else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
|
||||
ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
|
||||
else
|
||||
ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
|
||||
|
||||
ath79_wdt_clk.rate = ath79_ref_clk.rate;
|
||||
ath79_uart_clk.rate = ath79_ref_clk.rate;
|
||||
}
|
||||
|
||||
void __init ath79_clocks_init(void)
|
||||
{
|
||||
if (soc_is_ar71xx())
|
||||
|
@ -307,6 +383,8 @@ void __init ath79_clocks_init(void)
|
|||
ar933x_clocks_init();
|
||||
else if (soc_is_ar934x())
|
||||
ar934x_clocks_init();
|
||||
else if (soc_is_qca955x())
|
||||
qca955x_clocks_init();
|
||||
else
|
||||
BUG();
|
||||
|
||||
|
|
|
@ -72,6 +72,8 @@ void ath79_device_reset_set(u32 mask)
|
|||
reg = AR933X_RESET_REG_RESET_MODULE;
|
||||
else if (soc_is_ar934x())
|
||||
reg = AR934X_RESET_REG_RESET_MODULE;
|
||||
else if (soc_is_qca955x())
|
||||
reg = QCA955X_RESET_REG_RESET_MODULE;
|
||||
else
|
||||
BUG();
|
||||
|
||||
|
@ -98,6 +100,8 @@ void ath79_device_reset_clear(u32 mask)
|
|||
reg = AR933X_RESET_REG_RESET_MODULE;
|
||||
else if (soc_is_ar934x())
|
||||
reg = AR934X_RESET_REG_RESET_MODULE;
|
||||
else if (soc_is_qca955x())
|
||||
reg = QCA955X_RESET_REG_RESET_MODULE;
|
||||
else
|
||||
BUG();
|
||||
|
||||
|
|
|
@ -36,7 +36,7 @@ static struct resource ath79_uart_resources[] = {
|
|||
static struct plat_serial8250_port ath79_uart_data[] = {
|
||||
{
|
||||
.mapbase = AR71XX_UART_BASE,
|
||||
.irq = ATH79_MISC_IRQ_UART,
|
||||
.irq = ATH79_MISC_IRQ(3),
|
||||
.flags = AR71XX_UART_FLAGS,
|
||||
.iotype = UPIO_MEM32,
|
||||
.regshift = 2,
|
||||
|
@ -62,8 +62,8 @@ static struct resource ar933x_uart_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = ATH79_MISC_IRQ_UART,
|
||||
.end = ATH79_MISC_IRQ_UART,
|
||||
.start = ATH79_MISC_IRQ(3),
|
||||
.end = ATH79_MISC_IRQ(3),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
@ -90,7 +90,8 @@ void __init ath79_register_uart(void)
|
|||
if (soc_is_ar71xx() ||
|
||||
soc_is_ar724x() ||
|
||||
soc_is_ar913x() ||
|
||||
soc_is_ar934x()) {
|
||||
soc_is_ar934x() ||
|
||||
soc_is_qca955x()) {
|
||||
ath79_uart_data[0].uartclk = clk_get_rate(clk);
|
||||
platform_device_register(&ath79_uart_device);
|
||||
} else if (soc_is_ar933x()) {
|
||||
|
|
|
@ -25,29 +25,11 @@
|
|||
#include "common.h"
|
||||
#include "dev-usb.h"
|
||||
|
||||
static struct resource ath79_ohci_resources[2];
|
||||
|
||||
static u64 ath79_ohci_dmamask = DMA_BIT_MASK(32);
|
||||
static u64 ath79_usb_dmamask = DMA_BIT_MASK(32);
|
||||
|
||||
static struct usb_ohci_pdata ath79_ohci_pdata = {
|
||||
};
|
||||
|
||||
static struct platform_device ath79_ohci_device = {
|
||||
.name = "ohci-platform",
|
||||
.id = -1,
|
||||
.resource = ath79_ohci_resources,
|
||||
.num_resources = ARRAY_SIZE(ath79_ohci_resources),
|
||||
.dev = {
|
||||
.dma_mask = &ath79_ohci_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
.platform_data = &ath79_ohci_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource ath79_ehci_resources[2];
|
||||
|
||||
static u64 ath79_ehci_dmamask = DMA_BIT_MASK(32);
|
||||
|
||||
static struct usb_ehci_pdata ath79_ehci_pdata_v1 = {
|
||||
.has_synopsys_hc_bug = 1,
|
||||
};
|
||||
|
@ -57,22 +39,16 @@ static struct usb_ehci_pdata ath79_ehci_pdata_v2 = {
|
|||
.has_tt = 1,
|
||||
};
|
||||
|
||||
static struct platform_device ath79_ehci_device = {
|
||||
.name = "ehci-platform",
|
||||
.id = -1,
|
||||
.resource = ath79_ehci_resources,
|
||||
.num_resources = ARRAY_SIZE(ath79_ehci_resources),
|
||||
.dev = {
|
||||
.dma_mask = &ath79_ehci_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
};
|
||||
|
||||
static void __init ath79_usb_init_resource(struct resource res[2],
|
||||
unsigned long base,
|
||||
unsigned long size,
|
||||
int irq)
|
||||
static void __init ath79_usb_register(const char *name, int id,
|
||||
unsigned long base, unsigned long size,
|
||||
int irq, const void *data,
|
||||
size_t data_size)
|
||||
{
|
||||
struct resource res[2];
|
||||
struct platform_device *pdev;
|
||||
|
||||
memset(res, 0, sizeof(res));
|
||||
|
||||
res[0].flags = IORESOURCE_MEM;
|
||||
res[0].start = base;
|
||||
res[0].end = base + size - 1;
|
||||
|
@ -80,6 +56,19 @@ static void __init ath79_usb_init_resource(struct resource res[2],
|
|||
res[1].flags = IORESOURCE_IRQ;
|
||||
res[1].start = irq;
|
||||
res[1].end = irq;
|
||||
|
||||
pdev = platform_device_register_resndata(NULL, name, id,
|
||||
res, ARRAY_SIZE(res),
|
||||
data, data_size);
|
||||
|
||||
if (IS_ERR(pdev)) {
|
||||
pr_err("ath79: unable to register USB at %08lx, err=%d\n",
|
||||
base, (int) PTR_ERR(pdev));
|
||||
return;
|
||||
}
|
||||
|
||||
pdev->dev.dma_mask = &ath79_usb_dmamask;
|
||||
pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
|
||||
}
|
||||
|
||||
#define AR71XX_USB_RESET_MASK (AR71XX_RESET_USB_HOST | \
|
||||
|
@ -106,14 +95,15 @@ static void __init ath79_usb_setup(void)
|
|||
|
||||
mdelay(900);
|
||||
|
||||
ath79_usb_init_resource(ath79_ohci_resources, AR71XX_OHCI_BASE,
|
||||
AR71XX_OHCI_SIZE, ATH79_MISC_IRQ_OHCI);
|
||||
platform_device_register(&ath79_ohci_device);
|
||||
ath79_usb_register("ohci-platform", -1,
|
||||
AR71XX_OHCI_BASE, AR71XX_OHCI_SIZE,
|
||||
ATH79_MISC_IRQ(6),
|
||||
&ath79_ohci_pdata, sizeof(ath79_ohci_pdata));
|
||||
|
||||
ath79_usb_init_resource(ath79_ehci_resources, AR71XX_EHCI_BASE,
|
||||
AR71XX_EHCI_SIZE, ATH79_CPU_IRQ_USB);
|
||||
ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v1;
|
||||
platform_device_register(&ath79_ehci_device);
|
||||
ath79_usb_register("ehci-platform", -1,
|
||||
AR71XX_EHCI_BASE, AR71XX_EHCI_SIZE,
|
||||
ATH79_CPU_IRQ(3),
|
||||
&ath79_ehci_pdata_v1, sizeof(ath79_ehci_pdata_v1));
|
||||
}
|
||||
|
||||
static void __init ar7240_usb_setup(void)
|
||||
|
@ -135,9 +125,10 @@ static void __init ar7240_usb_setup(void)
|
|||
|
||||
iounmap(usb_ctrl_base);
|
||||
|
||||
ath79_usb_init_resource(ath79_ohci_resources, AR7240_OHCI_BASE,
|
||||
AR7240_OHCI_SIZE, ATH79_CPU_IRQ_USB);
|
||||
platform_device_register(&ath79_ohci_device);
|
||||
ath79_usb_register("ohci-platform", -1,
|
||||
AR7240_OHCI_BASE, AR7240_OHCI_SIZE,
|
||||
ATH79_CPU_IRQ(3),
|
||||
&ath79_ohci_pdata, sizeof(ath79_ohci_pdata));
|
||||
}
|
||||
|
||||
static void __init ar724x_usb_setup(void)
|
||||
|
@ -151,10 +142,10 @@ static void __init ar724x_usb_setup(void)
|
|||
ath79_device_reset_clear(AR724X_RESET_USB_PHY);
|
||||
mdelay(10);
|
||||
|
||||
ath79_usb_init_resource(ath79_ehci_resources, AR724X_EHCI_BASE,
|
||||
AR724X_EHCI_SIZE, ATH79_CPU_IRQ_USB);
|
||||
ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
|
||||
platform_device_register(&ath79_ehci_device);
|
||||
ath79_usb_register("ehci-platform", -1,
|
||||
AR724X_EHCI_BASE, AR724X_EHCI_SIZE,
|
||||
ATH79_CPU_IRQ(3),
|
||||
&ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
|
||||
}
|
||||
|
||||
static void __init ar913x_usb_setup(void)
|
||||
|
@ -168,10 +159,10 @@ static void __init ar913x_usb_setup(void)
|
|||
ath79_device_reset_clear(AR913X_RESET_USB_PHY);
|
||||
mdelay(10);
|
||||
|
||||
ath79_usb_init_resource(ath79_ehci_resources, AR913X_EHCI_BASE,
|
||||
AR913X_EHCI_SIZE, ATH79_CPU_IRQ_USB);
|
||||
ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
|
||||
platform_device_register(&ath79_ehci_device);
|
||||
ath79_usb_register("ehci-platform", -1,
|
||||
AR913X_EHCI_BASE, AR913X_EHCI_SIZE,
|
||||
ATH79_CPU_IRQ(3),
|
||||
&ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
|
||||
}
|
||||
|
||||
static void __init ar933x_usb_setup(void)
|
||||
|
@ -185,10 +176,10 @@ static void __init ar933x_usb_setup(void)
|
|||
ath79_device_reset_clear(AR933X_RESET_USB_PHY);
|
||||
mdelay(10);
|
||||
|
||||
ath79_usb_init_resource(ath79_ehci_resources, AR933X_EHCI_BASE,
|
||||
AR933X_EHCI_SIZE, ATH79_CPU_IRQ_USB);
|
||||
ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
|
||||
platform_device_register(&ath79_ehci_device);
|
||||
ath79_usb_register("ehci-platform", -1,
|
||||
AR933X_EHCI_BASE, AR933X_EHCI_SIZE,
|
||||
ATH79_CPU_IRQ(3),
|
||||
&ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
|
||||
}
|
||||
|
||||
static void __init ar934x_usb_setup(void)
|
||||
|
@ -211,10 +202,23 @@ static void __init ar934x_usb_setup(void)
|
|||
ath79_device_reset_clear(AR934X_RESET_USB_HOST);
|
||||
udelay(1000);
|
||||
|
||||
ath79_usb_init_resource(ath79_ehci_resources, AR934X_EHCI_BASE,
|
||||
AR934X_EHCI_SIZE, ATH79_CPU_IRQ_USB);
|
||||
ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
|
||||
platform_device_register(&ath79_ehci_device);
|
||||
ath79_usb_register("ehci-platform", -1,
|
||||
AR934X_EHCI_BASE, AR934X_EHCI_SIZE,
|
||||
ATH79_CPU_IRQ(3),
|
||||
&ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
|
||||
}
|
||||
|
||||
static void __init qca955x_usb_setup(void)
|
||||
{
|
||||
ath79_usb_register("ehci-platform", 0,
|
||||
QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE,
|
||||
ATH79_IP3_IRQ(0),
|
||||
&ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
|
||||
|
||||
ath79_usb_register("ehci-platform", 1,
|
||||
QCA955X_EHCI1_BASE, QCA955X_EHCI_SIZE,
|
||||
ATH79_IP3_IRQ(1),
|
||||
&ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
|
||||
}
|
||||
|
||||
void __init ath79_register_usb(void)
|
||||
|
@ -231,6 +235,8 @@ void __init ath79_register_usb(void)
|
|||
ar933x_usb_setup();
|
||||
else if (soc_is_ar934x())
|
||||
ar934x_usb_setup();
|
||||
else if (soc_is_qca955x())
|
||||
qca955x_usb_setup();
|
||||
else
|
||||
BUG();
|
||||
}
|
||||
|
|
|
@ -55,8 +55,8 @@ static void __init ar913x_wmac_setup(void)
|
|||
|
||||
ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
|
||||
ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
|
||||
ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2;
|
||||
ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2;
|
||||
ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2);
|
||||
ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2);
|
||||
}
|
||||
|
||||
|
||||
|
@ -83,8 +83,8 @@ static void __init ar933x_wmac_setup(void)
|
|||
|
||||
ath79_wmac_resources[0].start = AR933X_WMAC_BASE;
|
||||
ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1;
|
||||
ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2;
|
||||
ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2;
|
||||
ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2);
|
||||
ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2);
|
||||
|
||||
t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
|
||||
if (t & AR933X_BOOTSTRAP_REF_CLK_40)
|
||||
|
@ -107,7 +107,7 @@ static void ar934x_wmac_setup(void)
|
|||
ath79_wmac_resources[0].start = AR934X_WMAC_BASE;
|
||||
ath79_wmac_resources[0].end = AR934X_WMAC_BASE + AR934X_WMAC_SIZE - 1;
|
||||
ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
|
||||
ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
|
||||
ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
|
||||
|
||||
t = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
|
||||
if (t & AR934X_BOOTSTRAP_REF_CLK_40)
|
||||
|
@ -116,6 +116,24 @@ static void ar934x_wmac_setup(void)
|
|||
ath79_wmac_data.is_clk_25mhz = true;
|
||||
}
|
||||
|
||||
static void qca955x_wmac_setup(void)
|
||||
{
|
||||
u32 t;
|
||||
|
||||
ath79_wmac_device.name = "qca955x_wmac";
|
||||
|
||||
ath79_wmac_resources[0].start = QCA955X_WMAC_BASE;
|
||||
ath79_wmac_resources[0].end = QCA955X_WMAC_BASE + QCA955X_WMAC_SIZE - 1;
|
||||
ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
|
||||
ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
|
||||
|
||||
t = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
|
||||
if (t & QCA955X_BOOTSTRAP_REF_CLK_40)
|
||||
ath79_wmac_data.is_clk_25mhz = false;
|
||||
else
|
||||
ath79_wmac_data.is_clk_25mhz = true;
|
||||
}
|
||||
|
||||
void __init ath79_register_wmac(u8 *cal_data)
|
||||
{
|
||||
if (soc_is_ar913x())
|
||||
|
@ -124,6 +142,8 @@ void __init ath79_register_wmac(u8 *cal_data)
|
|||
ar933x_wmac_setup();
|
||||
else if (soc_is_ar934x())
|
||||
ar934x_wmac_setup();
|
||||
else if (soc_is_qca955x())
|
||||
qca955x_wmac_setup();
|
||||
else
|
||||
BUG();
|
||||
|
||||
|
|
|
@ -74,6 +74,8 @@ static void prom_putchar_init(void)
|
|||
case REV_ID_MAJOR_AR9341:
|
||||
case REV_ID_MAJOR_AR9342:
|
||||
case REV_ID_MAJOR_AR9344:
|
||||
case REV_ID_MAJOR_QCA9556:
|
||||
case REV_ID_MAJOR_QCA9558:
|
||||
_prom_putchar = prom_putchar_ar71xx;
|
||||
break;
|
||||
|
||||
|
|
|
@ -137,51 +137,47 @@ static struct gpio_chip ath79_gpio_chip = {
|
|||
.base = 0,
|
||||
};
|
||||
|
||||
void ath79_gpio_function_enable(u32 mask)
|
||||
static void __iomem *ath79_gpio_get_function_reg(void)
|
||||
{
|
||||
void __iomem *base = ath79_gpio_base;
|
||||
unsigned long flags;
|
||||
u32 reg = 0;
|
||||
|
||||
spin_lock_irqsave(&ath79_gpio_lock, flags);
|
||||
if (soc_is_ar71xx() ||
|
||||
soc_is_ar724x() ||
|
||||
soc_is_ar913x() ||
|
||||
soc_is_ar933x())
|
||||
reg = AR71XX_GPIO_REG_FUNC;
|
||||
else if (soc_is_ar934x())
|
||||
reg = AR934X_GPIO_REG_FUNC;
|
||||
else
|
||||
BUG();
|
||||
|
||||
__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) | mask,
|
||||
base + AR71XX_GPIO_REG_FUNC);
|
||||
/* flush write */
|
||||
__raw_readl(base + AR71XX_GPIO_REG_FUNC);
|
||||
|
||||
spin_unlock_irqrestore(&ath79_gpio_lock, flags);
|
||||
}
|
||||
|
||||
void ath79_gpio_function_disable(u32 mask)
|
||||
{
|
||||
void __iomem *base = ath79_gpio_base;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&ath79_gpio_lock, flags);
|
||||
|
||||
__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~mask,
|
||||
base + AR71XX_GPIO_REG_FUNC);
|
||||
/* flush write */
|
||||
__raw_readl(base + AR71XX_GPIO_REG_FUNC);
|
||||
|
||||
spin_unlock_irqrestore(&ath79_gpio_lock, flags);
|
||||
return ath79_gpio_base + reg;
|
||||
}
|
||||
|
||||
void ath79_gpio_function_setup(u32 set, u32 clear)
|
||||
{
|
||||
void __iomem *base = ath79_gpio_base;
|
||||
void __iomem *reg = ath79_gpio_get_function_reg();
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&ath79_gpio_lock, flags);
|
||||
|
||||
__raw_writel((__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~clear) | set,
|
||||
base + AR71XX_GPIO_REG_FUNC);
|
||||
__raw_writel((__raw_readl(reg) & ~clear) | set, reg);
|
||||
/* flush write */
|
||||
__raw_readl(base + AR71XX_GPIO_REG_FUNC);
|
||||
__raw_readl(reg);
|
||||
|
||||
spin_unlock_irqrestore(&ath79_gpio_lock, flags);
|
||||
}
|
||||
|
||||
void ath79_gpio_function_enable(u32 mask)
|
||||
{
|
||||
ath79_gpio_function_setup(mask, 0);
|
||||
}
|
||||
|
||||
void ath79_gpio_function_disable(u32 mask)
|
||||
{
|
||||
ath79_gpio_function_setup(0, mask);
|
||||
}
|
||||
|
||||
void __init ath79_gpio_init(void)
|
||||
{
|
||||
int err;
|
||||
|
@ -198,12 +194,14 @@ void __init ath79_gpio_init(void)
|
|||
ath79_gpio_count = AR933X_GPIO_COUNT;
|
||||
else if (soc_is_ar934x())
|
||||
ath79_gpio_count = AR934X_GPIO_COUNT;
|
||||
else if (soc_is_qca955x())
|
||||
ath79_gpio_count = QCA955X_GPIO_COUNT;
|
||||
else
|
||||
BUG();
|
||||
|
||||
ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
|
||||
ath79_gpio_chip.ngpio = ath79_gpio_count;
|
||||
if (soc_is_ar934x()) {
|
||||
if (soc_is_ar934x() || soc_is_qca955x()) {
|
||||
ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
|
||||
ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
|
||||
}
|
||||
|
|
|
@ -35,44 +35,17 @@ static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
|
|||
pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) &
|
||||
__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
|
||||
|
||||
if (pending & MISC_INT_UART)
|
||||
generic_handle_irq(ATH79_MISC_IRQ_UART);
|
||||
|
||||
else if (pending & MISC_INT_DMA)
|
||||
generic_handle_irq(ATH79_MISC_IRQ_DMA);
|
||||
|
||||
else if (pending & MISC_INT_PERFC)
|
||||
generic_handle_irq(ATH79_MISC_IRQ_PERFC);
|
||||
|
||||
else if (pending & MISC_INT_TIMER)
|
||||
generic_handle_irq(ATH79_MISC_IRQ_TIMER);
|
||||
|
||||
else if (pending & MISC_INT_TIMER2)
|
||||
generic_handle_irq(ATH79_MISC_IRQ_TIMER2);
|
||||
|
||||
else if (pending & MISC_INT_TIMER3)
|
||||
generic_handle_irq(ATH79_MISC_IRQ_TIMER3);
|
||||
|
||||
else if (pending & MISC_INT_TIMER4)
|
||||
generic_handle_irq(ATH79_MISC_IRQ_TIMER4);
|
||||
|
||||
else if (pending & MISC_INT_OHCI)
|
||||
generic_handle_irq(ATH79_MISC_IRQ_OHCI);
|
||||
|
||||
else if (pending & MISC_INT_ERROR)
|
||||
generic_handle_irq(ATH79_MISC_IRQ_ERROR);
|
||||
|
||||
else if (pending & MISC_INT_GPIO)
|
||||
generic_handle_irq(ATH79_MISC_IRQ_GPIO);
|
||||
|
||||
else if (pending & MISC_INT_WDOG)
|
||||
generic_handle_irq(ATH79_MISC_IRQ_WDOG);
|
||||
|
||||
else if (pending & MISC_INT_ETHSW)
|
||||
generic_handle_irq(ATH79_MISC_IRQ_ETHSW);
|
||||
|
||||
else
|
||||
if (!pending) {
|
||||
spurious_interrupt();
|
||||
return;
|
||||
}
|
||||
|
||||
while (pending) {
|
||||
int bit = __ffs(pending);
|
||||
|
||||
generic_handle_irq(ATH79_MISC_IRQ(bit));
|
||||
pending &= ~BIT(bit);
|
||||
}
|
||||
}
|
||||
|
||||
static void ar71xx_misc_irq_unmask(struct irq_data *d)
|
||||
|
@ -130,7 +103,10 @@ static void __init ath79_misc_irq_init(void)
|
|||
|
||||
if (soc_is_ar71xx() || soc_is_ar913x())
|
||||
ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
|
||||
else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x())
|
||||
else if (soc_is_ar724x() ||
|
||||
soc_is_ar933x() ||
|
||||
soc_is_ar934x() ||
|
||||
soc_is_qca955x())
|
||||
ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
|
||||
else
|
||||
BUG();
|
||||
|
@ -141,7 +117,7 @@ static void __init ath79_misc_irq_init(void)
|
|||
handle_level_irq);
|
||||
}
|
||||
|
||||
irq_set_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler);
|
||||
irq_set_chained_handler(ATH79_CPU_IRQ(6), ath79_misc_irq_handler);
|
||||
}
|
||||
|
||||
static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
|
||||
|
@ -174,7 +150,89 @@ static void ar934x_ip2_irq_init(void)
|
|||
irq_set_chip_and_handler(i, &dummy_irq_chip,
|
||||
handle_level_irq);
|
||||
|
||||
irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar934x_ip2_irq_dispatch);
|
||||
irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
|
||||
}
|
||||
|
||||
static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
u32 status;
|
||||
|
||||
disable_irq_nosync(irq);
|
||||
|
||||
status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
|
||||
status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL;
|
||||
|
||||
if (status == 0) {
|
||||
spurious_interrupt();
|
||||
goto enable;
|
||||
}
|
||||
|
||||
if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) {
|
||||
/* TODO: flush DDR? */
|
||||
generic_handle_irq(ATH79_IP2_IRQ(0));
|
||||
}
|
||||
|
||||
if (status & QCA955X_EXT_INT_WMAC_ALL) {
|
||||
/* TODO: flush DDR? */
|
||||
generic_handle_irq(ATH79_IP2_IRQ(1));
|
||||
}
|
||||
|
||||
enable:
|
||||
enable_irq(irq);
|
||||
}
|
||||
|
||||
static void qca955x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
u32 status;
|
||||
|
||||
disable_irq_nosync(irq);
|
||||
|
||||
status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
|
||||
status &= QCA955X_EXT_INT_PCIE_RC2_ALL |
|
||||
QCA955X_EXT_INT_USB1 |
|
||||
QCA955X_EXT_INT_USB2;
|
||||
|
||||
if (status == 0) {
|
||||
spurious_interrupt();
|
||||
goto enable;
|
||||
}
|
||||
|
||||
if (status & QCA955X_EXT_INT_USB1) {
|
||||
/* TODO: flush DDR? */
|
||||
generic_handle_irq(ATH79_IP3_IRQ(0));
|
||||
}
|
||||
|
||||
if (status & QCA955X_EXT_INT_USB2) {
|
||||
/* TODO: flush DDR? */
|
||||
generic_handle_irq(ATH79_IP3_IRQ(1));
|
||||
}
|
||||
|
||||
if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) {
|
||||
/* TODO: flush DDR? */
|
||||
generic_handle_irq(ATH79_IP3_IRQ(2));
|
||||
}
|
||||
|
||||
enable:
|
||||
enable_irq(irq);
|
||||
}
|
||||
|
||||
static void qca955x_irq_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = ATH79_IP2_IRQ_BASE;
|
||||
i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
|
||||
irq_set_chip_and_handler(i, &dummy_irq_chip,
|
||||
handle_level_irq);
|
||||
|
||||
irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
|
||||
|
||||
for (i = ATH79_IP3_IRQ_BASE;
|
||||
i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
|
||||
irq_set_chip_and_handler(i, &dummy_irq_chip,
|
||||
handle_level_irq);
|
||||
|
||||
irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
|
@ -184,22 +242,22 @@ asmlinkage void plat_irq_dispatch(void)
|
|||
pending = read_c0_status() & read_c0_cause() & ST0_IM;
|
||||
|
||||
if (pending & STATUSF_IP7)
|
||||
do_IRQ(ATH79_CPU_IRQ_TIMER);
|
||||
do_IRQ(ATH79_CPU_IRQ(7));
|
||||
|
||||
else if (pending & STATUSF_IP2)
|
||||
ath79_ip2_handler();
|
||||
|
||||
else if (pending & STATUSF_IP4)
|
||||
do_IRQ(ATH79_CPU_IRQ_GE0);
|
||||
do_IRQ(ATH79_CPU_IRQ(4));
|
||||
|
||||
else if (pending & STATUSF_IP5)
|
||||
do_IRQ(ATH79_CPU_IRQ_GE1);
|
||||
do_IRQ(ATH79_CPU_IRQ(5));
|
||||
|
||||
else if (pending & STATUSF_IP3)
|
||||
ath79_ip3_handler();
|
||||
|
||||
else if (pending & STATUSF_IP6)
|
||||
do_IRQ(ATH79_CPU_IRQ_MISC);
|
||||
do_IRQ(ATH79_CPU_IRQ(6));
|
||||
|
||||
else
|
||||
spurious_interrupt();
|
||||
|
@ -212,63 +270,69 @@ asmlinkage void plat_irq_dispatch(void)
|
|||
* Issue a flush in the handlers to ensure that the driver sees
|
||||
* the update.
|
||||
*/
|
||||
|
||||
static void ath79_default_ip2_handler(void)
|
||||
{
|
||||
do_IRQ(ATH79_CPU_IRQ(2));
|
||||
}
|
||||
|
||||
static void ath79_default_ip3_handler(void)
|
||||
{
|
||||
do_IRQ(ATH79_CPU_IRQ(3));
|
||||
}
|
||||
|
||||
static void ar71xx_ip2_handler(void)
|
||||
{
|
||||
ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI);
|
||||
do_IRQ(ATH79_CPU_IRQ_IP2);
|
||||
do_IRQ(ATH79_CPU_IRQ(2));
|
||||
}
|
||||
|
||||
static void ar724x_ip2_handler(void)
|
||||
{
|
||||
ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_PCIE);
|
||||
do_IRQ(ATH79_CPU_IRQ_IP2);
|
||||
do_IRQ(ATH79_CPU_IRQ(2));
|
||||
}
|
||||
|
||||
static void ar913x_ip2_handler(void)
|
||||
{
|
||||
ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_WMAC);
|
||||
do_IRQ(ATH79_CPU_IRQ_IP2);
|
||||
do_IRQ(ATH79_CPU_IRQ(2));
|
||||
}
|
||||
|
||||
static void ar933x_ip2_handler(void)
|
||||
{
|
||||
ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_WMAC);
|
||||
do_IRQ(ATH79_CPU_IRQ_IP2);
|
||||
}
|
||||
|
||||
static void ar934x_ip2_handler(void)
|
||||
{
|
||||
do_IRQ(ATH79_CPU_IRQ_IP2);
|
||||
do_IRQ(ATH79_CPU_IRQ(2));
|
||||
}
|
||||
|
||||
static void ar71xx_ip3_handler(void)
|
||||
{
|
||||
ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB);
|
||||
do_IRQ(ATH79_CPU_IRQ_USB);
|
||||
do_IRQ(ATH79_CPU_IRQ(3));
|
||||
}
|
||||
|
||||
static void ar724x_ip3_handler(void)
|
||||
{
|
||||
ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_USB);
|
||||
do_IRQ(ATH79_CPU_IRQ_USB);
|
||||
do_IRQ(ATH79_CPU_IRQ(3));
|
||||
}
|
||||
|
||||
static void ar913x_ip3_handler(void)
|
||||
{
|
||||
ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_USB);
|
||||
do_IRQ(ATH79_CPU_IRQ_USB);
|
||||
do_IRQ(ATH79_CPU_IRQ(3));
|
||||
}
|
||||
|
||||
static void ar933x_ip3_handler(void)
|
||||
{
|
||||
ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_USB);
|
||||
do_IRQ(ATH79_CPU_IRQ_USB);
|
||||
do_IRQ(ATH79_CPU_IRQ(3));
|
||||
}
|
||||
|
||||
static void ar934x_ip3_handler(void)
|
||||
{
|
||||
ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_USB);
|
||||
do_IRQ(ATH79_CPU_IRQ_USB);
|
||||
do_IRQ(ATH79_CPU_IRQ(3));
|
||||
}
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
|
@ -286,16 +350,21 @@ void __init arch_init_irq(void)
|
|||
ath79_ip2_handler = ar933x_ip2_handler;
|
||||
ath79_ip3_handler = ar933x_ip3_handler;
|
||||
} else if (soc_is_ar934x()) {
|
||||
ath79_ip2_handler = ar934x_ip2_handler;
|
||||
ath79_ip2_handler = ath79_default_ip2_handler;
|
||||
ath79_ip3_handler = ar934x_ip3_handler;
|
||||
} else if (soc_is_qca955x()) {
|
||||
ath79_ip2_handler = ath79_default_ip2_handler;
|
||||
ath79_ip3_handler = ath79_default_ip3_handler;
|
||||
} else {
|
||||
BUG();
|
||||
}
|
||||
|
||||
cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC;
|
||||
cp0_perfcount_irq = ATH79_MISC_IRQ(5);
|
||||
mips_cpu_irq_init();
|
||||
ath79_misc_irq_init();
|
||||
|
||||
if (soc_is_ar934x())
|
||||
ar934x_ip2_irq_init();
|
||||
else if (soc_is_qca955x())
|
||||
qca955x_irq_init();
|
||||
}
|
||||
|
|
|
@ -0,0 +1,156 @@
|
|||
/*
|
||||
* Qualcomm Atheros AP136 reference board support
|
||||
*
|
||||
* Copyright (c) 2012 Qualcomm Atheros
|
||||
* Copyright (c) 2012-2013 Gabor Juhos <juhosg@openwrt.org>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/pci.h>
|
||||
#include <linux/ath9k_platform.h>
|
||||
|
||||
#include "machtypes.h"
|
||||
#include "dev-gpio-buttons.h"
|
||||
#include "dev-leds-gpio.h"
|
||||
#include "dev-spi.h"
|
||||
#include "dev-usb.h"
|
||||
#include "dev-wmac.h"
|
||||
#include "pci.h"
|
||||
|
||||
#define AP136_GPIO_LED_STATUS_RED 14
|
||||
#define AP136_GPIO_LED_STATUS_GREEN 19
|
||||
#define AP136_GPIO_LED_USB 4
|
||||
#define AP136_GPIO_LED_WLAN_2G 13
|
||||
#define AP136_GPIO_LED_WLAN_5G 12
|
||||
#define AP136_GPIO_LED_WPS_RED 15
|
||||
#define AP136_GPIO_LED_WPS_GREEN 20
|
||||
|
||||
#define AP136_GPIO_BTN_WPS 16
|
||||
#define AP136_GPIO_BTN_RFKILL 21
|
||||
|
||||
#define AP136_KEYS_POLL_INTERVAL 20 /* msecs */
|
||||
#define AP136_KEYS_DEBOUNCE_INTERVAL (3 * AP136_KEYS_POLL_INTERVAL)
|
||||
|
||||
#define AP136_WMAC_CALDATA_OFFSET 0x1000
|
||||
#define AP136_PCIE_CALDATA_OFFSET 0x5000
|
||||
|
||||
static struct gpio_led ap136_leds_gpio[] __initdata = {
|
||||
{
|
||||
.name = "qca:green:status",
|
||||
.gpio = AP136_GPIO_LED_STATUS_GREEN,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "qca:red:status",
|
||||
.gpio = AP136_GPIO_LED_STATUS_RED,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "qca:green:wps",
|
||||
.gpio = AP136_GPIO_LED_WPS_GREEN,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "qca:red:wps",
|
||||
.gpio = AP136_GPIO_LED_WPS_RED,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "qca:red:wlan-2g",
|
||||
.gpio = AP136_GPIO_LED_WLAN_2G,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "qca:red:usb",
|
||||
.gpio = AP136_GPIO_LED_USB,
|
||||
.active_low = 1,
|
||||
}
|
||||
};
|
||||
|
||||
static struct gpio_keys_button ap136_gpio_keys[] __initdata = {
|
||||
{
|
||||
.desc = "WPS button",
|
||||
.type = EV_KEY,
|
||||
.code = KEY_WPS_BUTTON,
|
||||
.debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL,
|
||||
.gpio = AP136_GPIO_BTN_WPS,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.desc = "RFKILL button",
|
||||
.type = EV_KEY,
|
||||
.code = KEY_RFKILL,
|
||||
.debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL,
|
||||
.gpio = AP136_GPIO_BTN_RFKILL,
|
||||
.active_low = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct spi_board_info ap136_spi_info[] = {
|
||||
{
|
||||
.bus_num = 0,
|
||||
.chip_select = 0,
|
||||
.max_speed_hz = 25000000,
|
||||
.modalias = "mx25l6405d",
|
||||
}
|
||||
};
|
||||
|
||||
static struct ath79_spi_platform_data ap136_spi_data = {
|
||||
.bus_num = 0,
|
||||
.num_chipselect = 1,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
static struct ath9k_platform_data ap136_ath9k_data;
|
||||
|
||||
static int ap136_pci_plat_dev_init(struct pci_dev *dev)
|
||||
{
|
||||
if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
|
||||
dev->dev.platform_data = &ap136_ath9k_data;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init ap136_pci_init(u8 *eeprom)
|
||||
{
|
||||
memcpy(ap136_ath9k_data.eeprom_data, eeprom,
|
||||
sizeof(ap136_ath9k_data.eeprom_data));
|
||||
|
||||
ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
|
||||
ath79_register_pci();
|
||||
}
|
||||
#else
|
||||
static inline void ap136_pci_init(void) {}
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
static void __init ap136_setup(void)
|
||||
{
|
||||
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
|
||||
|
||||
ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
|
||||
ap136_leds_gpio);
|
||||
ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
|
||||
ARRAY_SIZE(ap136_gpio_keys),
|
||||
ap136_gpio_keys);
|
||||
ath79_register_spi(&ap136_spi_data, ap136_spi_info,
|
||||
ARRAY_SIZE(ap136_spi_info));
|
||||
ath79_register_usb();
|
||||
ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET);
|
||||
ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET);
|
||||
}
|
||||
|
||||
MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010",
|
||||
"Atheros AP136-010 reference board",
|
||||
ap136_setup);
|
|
@ -17,6 +17,7 @@
|
|||
enum ath79_mach_type {
|
||||
ATH79_MACH_GENERIC = 0,
|
||||
ATH79_MACH_AP121, /* Atheros AP121 reference board */
|
||||
ATH79_MACH_AP136_010, /* Atheros AP136-010 reference board */
|
||||
ATH79_MACH_AP81, /* Atheros AP81 reference board */
|
||||
ATH79_MACH_DB120, /* Atheros DB120 reference board */
|
||||
ATH79_MACH_PB44, /* Atheros PB44 reference board */
|
||||
|
|
|
@ -14,10 +14,11 @@
|
|||
|
||||
#include <linux/init.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/resource.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <asm/mach-ath79/ar71xx_regs.h>
|
||||
#include <asm/mach-ath79/ath79.h>
|
||||
#include <asm/mach-ath79/irq.h>
|
||||
#include <asm/mach-ath79/pci.h>
|
||||
#include "pci.h"
|
||||
|
||||
static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev);
|
||||
|
@ -48,6 +49,21 @@ static const struct ath79_pci_irq ar724x_pci_irq_map[] __initconst = {
|
|||
}
|
||||
};
|
||||
|
||||
static const struct ath79_pci_irq qca955x_pci_irq_map[] __initconst = {
|
||||
{
|
||||
.bus = 0,
|
||||
.slot = 0,
|
||||
.pin = 1,
|
||||
.irq = ATH79_PCI_IRQ(0),
|
||||
},
|
||||
{
|
||||
.bus = 1,
|
||||
.slot = 0,
|
||||
.pin = 1,
|
||||
.irq = ATH79_PCI_IRQ(1),
|
||||
},
|
||||
};
|
||||
|
||||
int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
|
||||
{
|
||||
int irq = -1;
|
||||
|
@ -63,6 +79,9 @@ int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
|
|||
soc_is_ar9344()) {
|
||||
ath79_pci_irq_map = ar724x_pci_irq_map;
|
||||
ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
|
||||
} else if (soc_is_qca955x()) {
|
||||
ath79_pci_irq_map = qca955x_pci_irq_map;
|
||||
ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
|
||||
} else {
|
||||
pr_crit("pci %s: invalid irq map\n",
|
||||
pci_name((struct pci_dev *) dev));
|
||||
|
@ -74,7 +93,9 @@ int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
|
|||
const struct ath79_pci_irq *entry;
|
||||
|
||||
entry = &ath79_pci_irq_map[i];
|
||||
if (entry->slot == slot && entry->pin == pin) {
|
||||
if (entry->bus == dev->bus->number &&
|
||||
entry->slot == slot &&
|
||||
entry->pin == pin) {
|
||||
irq = entry->irq;
|
||||
break;
|
||||
}
|
||||
|
@ -110,21 +131,143 @@ void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev))
|
|||
ath79_pci_plat_dev_init = func;
|
||||
}
|
||||
|
||||
static struct platform_device *
|
||||
ath79_register_pci_ar71xx(void)
|
||||
{
|
||||
struct platform_device *pdev;
|
||||
struct resource res[4];
|
||||
|
||||
memset(res, 0, sizeof(res));
|
||||
|
||||
res[0].name = "cfg_base";
|
||||
res[0].flags = IORESOURCE_MEM;
|
||||
res[0].start = AR71XX_PCI_CFG_BASE;
|
||||
res[0].end = AR71XX_PCI_CFG_BASE + AR71XX_PCI_CFG_SIZE - 1;
|
||||
|
||||
res[1].flags = IORESOURCE_IRQ;
|
||||
res[1].start = ATH79_CPU_IRQ(2);
|
||||
res[1].end = ATH79_CPU_IRQ(2);
|
||||
|
||||
res[2].name = "io_base";
|
||||
res[2].flags = IORESOURCE_IO;
|
||||
res[2].start = 0;
|
||||
res[2].end = 0;
|
||||
|
||||
res[3].name = "mem_base";
|
||||
res[3].flags = IORESOURCE_MEM;
|
||||
res[3].start = AR71XX_PCI_MEM_BASE;
|
||||
res[3].end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1;
|
||||
|
||||
pdev = platform_device_register_simple("ar71xx-pci", -1,
|
||||
res, ARRAY_SIZE(res));
|
||||
return pdev;
|
||||
}
|
||||
|
||||
static struct platform_device *
|
||||
ath79_register_pci_ar724x(int id,
|
||||
unsigned long cfg_base,
|
||||
unsigned long ctrl_base,
|
||||
unsigned long crp_base,
|
||||
unsigned long mem_base,
|
||||
unsigned long mem_size,
|
||||
unsigned long io_base,
|
||||
int irq)
|
||||
{
|
||||
struct platform_device *pdev;
|
||||
struct resource res[6];
|
||||
|
||||
memset(res, 0, sizeof(res));
|
||||
|
||||
res[0].name = "cfg_base";
|
||||
res[0].flags = IORESOURCE_MEM;
|
||||
res[0].start = cfg_base;
|
||||
res[0].end = cfg_base + AR724X_PCI_CFG_SIZE - 1;
|
||||
|
||||
res[1].name = "ctrl_base";
|
||||
res[1].flags = IORESOURCE_MEM;
|
||||
res[1].start = ctrl_base;
|
||||
res[1].end = ctrl_base + AR724X_PCI_CTRL_SIZE - 1;
|
||||
|
||||
res[2].flags = IORESOURCE_IRQ;
|
||||
res[2].start = irq;
|
||||
res[2].end = irq;
|
||||
|
||||
res[3].name = "mem_base";
|
||||
res[3].flags = IORESOURCE_MEM;
|
||||
res[3].start = mem_base;
|
||||
res[3].end = mem_base + mem_size - 1;
|
||||
|
||||
res[4].name = "io_base";
|
||||
res[4].flags = IORESOURCE_IO;
|
||||
res[4].start = io_base;
|
||||
res[4].end = io_base;
|
||||
|
||||
res[5].name = "crp_base";
|
||||
res[5].flags = IORESOURCE_MEM;
|
||||
res[5].start = crp_base;
|
||||
res[5].end = crp_base + AR724X_PCI_CRP_SIZE - 1;
|
||||
|
||||
pdev = platform_device_register_simple("ar724x-pci", id,
|
||||
res, ARRAY_SIZE(res));
|
||||
return pdev;
|
||||
}
|
||||
|
||||
int __init ath79_register_pci(void)
|
||||
{
|
||||
if (soc_is_ar71xx())
|
||||
return ar71xx_pcibios_init();
|
||||
struct platform_device *pdev = NULL;
|
||||
|
||||
if (soc_is_ar724x())
|
||||
return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2);
|
||||
|
||||
if (soc_is_ar9342() || soc_is_ar9344()) {
|
||||
if (soc_is_ar71xx()) {
|
||||
pdev = ath79_register_pci_ar71xx();
|
||||
} else if (soc_is_ar724x()) {
|
||||
pdev = ath79_register_pci_ar724x(-1,
|
||||
AR724X_PCI_CFG_BASE,
|
||||
AR724X_PCI_CTRL_BASE,
|
||||
AR724X_PCI_CRP_BASE,
|
||||
AR724X_PCI_MEM_BASE,
|
||||
AR724X_PCI_MEM_SIZE,
|
||||
0,
|
||||
ATH79_CPU_IRQ(2));
|
||||
} else if (soc_is_ar9342() ||
|
||||
soc_is_ar9344()) {
|
||||
u32 bootstrap;
|
||||
|
||||
bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
|
||||
if (bootstrap & AR934X_BOOTSTRAP_PCIE_RC)
|
||||
return ar724x_pcibios_init(ATH79_IP2_IRQ(0));
|
||||
}
|
||||
if ((bootstrap & AR934X_BOOTSTRAP_PCIE_RC) == 0)
|
||||
return -ENODEV;
|
||||
|
||||
pdev = ath79_register_pci_ar724x(-1,
|
||||
AR724X_PCI_CFG_BASE,
|
||||
AR724X_PCI_CTRL_BASE,
|
||||
AR724X_PCI_CRP_BASE,
|
||||
AR724X_PCI_MEM_BASE,
|
||||
AR724X_PCI_MEM_SIZE,
|
||||
0,
|
||||
ATH79_IP2_IRQ(0));
|
||||
} else if (soc_is_qca9558()) {
|
||||
pdev = ath79_register_pci_ar724x(0,
|
||||
QCA955X_PCI_CFG_BASE0,
|
||||
QCA955X_PCI_CTRL_BASE0,
|
||||
QCA955X_PCI_CRP_BASE0,
|
||||
QCA955X_PCI_MEM_BASE0,
|
||||
QCA955X_PCI_MEM_SIZE,
|
||||
0,
|
||||
ATH79_IP2_IRQ(0));
|
||||
|
||||
pdev = ath79_register_pci_ar724x(1,
|
||||
QCA955X_PCI_CFG_BASE1,
|
||||
QCA955X_PCI_CTRL_BASE1,
|
||||
QCA955X_PCI_CRP_BASE1,
|
||||
QCA955X_PCI_MEM_BASE1,
|
||||
QCA955X_PCI_MEM_SIZE,
|
||||
1,
|
||||
ATH79_IP3_IRQ(2));
|
||||
} else {
|
||||
/* No PCI support */
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (!pdev)
|
||||
pr_err("unable to register PCI controller device\n");
|
||||
|
||||
return pdev ? 0 : -ENODEV;
|
||||
}
|
||||
|
|
|
@ -14,6 +14,7 @@
|
|||
#define _ATH79_PCI_H
|
||||
|
||||
struct ath79_pci_irq {
|
||||
int bus;
|
||||
u8 slot;
|
||||
u8 pin;
|
||||
int irq;
|
||||
|
|
|
@ -164,12 +164,28 @@ static void __init ath79_detect_sys_type(void)
|
|||
rev = id & AR934X_REV_ID_REVISION_MASK;
|
||||
break;
|
||||
|
||||
case REV_ID_MAJOR_QCA9556:
|
||||
ath79_soc = ATH79_SOC_QCA9556;
|
||||
chip = "9556";
|
||||
rev = id & QCA955X_REV_ID_REVISION_MASK;
|
||||
break;
|
||||
|
||||
case REV_ID_MAJOR_QCA9558:
|
||||
ath79_soc = ATH79_SOC_QCA9558;
|
||||
chip = "9558";
|
||||
rev = id & QCA955X_REV_ID_REVISION_MASK;
|
||||
break;
|
||||
|
||||
default:
|
||||
panic("ath79: unknown SoC, id:0x%08x", id);
|
||||
}
|
||||
|
||||
ath79_soc_rev = rev;
|
||||
|
||||
if (soc_is_qca955x())
|
||||
sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
|
||||
chip, rev);
|
||||
else
|
||||
sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
|
||||
pr_info("SoC: %s\n", ath79_sys_type);
|
||||
}
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* Copyright (C) 2005 Broadcom Corporation
|
||||
* Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
|
||||
* Copyright (C) 2010-2011 Hauke Mehrtens <hauke@hauke-m.de>
|
||||
* Copyright (C) 2010-2012 Hauke Mehrtens <hauke@hauke-m.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
|
@ -18,83 +18,160 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/string.h>
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/mach-bcm47xx/nvram.h>
|
||||
#include <bcm47xx_nvram.h>
|
||||
#include <asm/mach-bcm47xx/bcm47xx.h>
|
||||
|
||||
static char nvram_buf[NVRAM_SPACE];
|
||||
|
||||
/* Probe for NVRAM header */
|
||||
static void early_nvram_init(void)
|
||||
static u32 find_nvram_size(u32 end)
|
||||
{
|
||||
#ifdef CONFIG_BCM47XX_SSB
|
||||
struct ssb_mipscore *mcore_ssb;
|
||||
#endif
|
||||
#ifdef CONFIG_BCM47XX_BCMA
|
||||
struct bcma_drv_cc *bcma_cc;
|
||||
#endif
|
||||
struct nvram_header *header;
|
||||
u32 nvram_sizes[] = {0x8000, 0xF000, 0x10000};
|
||||
int i;
|
||||
u32 base = 0;
|
||||
u32 lim = 0;
|
||||
u32 off;
|
||||
u32 *src, *dst;
|
||||
|
||||
switch (bcm47xx_bus_type) {
|
||||
#ifdef CONFIG_BCM47XX_SSB
|
||||
case BCM47XX_BUS_TYPE_SSB:
|
||||
mcore_ssb = &bcm47xx_bus.ssb.mipscore;
|
||||
base = mcore_ssb->pflash.window;
|
||||
lim = mcore_ssb->pflash.window_size;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_BCM47XX_BCMA
|
||||
case BCM47XX_BUS_TYPE_BCMA:
|
||||
bcma_cc = &bcm47xx_bus.bcma.bus.drv_cc;
|
||||
base = bcma_cc->pflash.window;
|
||||
lim = bcma_cc->pflash.window_size;
|
||||
break;
|
||||
#endif
|
||||
for (i = 0; i < ARRAY_SIZE(nvram_sizes); i++) {
|
||||
header = (struct nvram_header *)KSEG1ADDR(end - nvram_sizes[i]);
|
||||
if (header->magic == NVRAM_HEADER)
|
||||
return nvram_sizes[i];
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Probe for NVRAM header */
|
||||
static int nvram_find_and_copy(u32 base, u32 lim)
|
||||
{
|
||||
struct nvram_header *header;
|
||||
int i;
|
||||
u32 off;
|
||||
u32 *src, *dst;
|
||||
u32 size;
|
||||
|
||||
/* TODO: when nvram is on nand flash check for bad blocks first. */
|
||||
off = FLASH_MIN;
|
||||
while (off <= lim) {
|
||||
/* Windowed flash access */
|
||||
header = (struct nvram_header *)
|
||||
KSEG1ADDR(base + off - NVRAM_SPACE);
|
||||
if (header->magic == NVRAM_HEADER)
|
||||
size = find_nvram_size(base + off);
|
||||
if (size) {
|
||||
header = (struct nvram_header *)KSEG1ADDR(base + off -
|
||||
size);
|
||||
goto found;
|
||||
}
|
||||
off <<= 1;
|
||||
}
|
||||
|
||||
/* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
|
||||
header = (struct nvram_header *) KSEG1ADDR(base + 4096);
|
||||
if (header->magic == NVRAM_HEADER)
|
||||
if (header->magic == NVRAM_HEADER) {
|
||||
size = NVRAM_SPACE;
|
||||
goto found;
|
||||
}
|
||||
|
||||
header = (struct nvram_header *) KSEG1ADDR(base + 1024);
|
||||
if (header->magic == NVRAM_HEADER)
|
||||
if (header->magic == NVRAM_HEADER) {
|
||||
size = NVRAM_SPACE;
|
||||
goto found;
|
||||
}
|
||||
|
||||
return;
|
||||
pr_err("no nvram found\n");
|
||||
return -ENXIO;
|
||||
|
||||
found:
|
||||
|
||||
if (header->len > size)
|
||||
pr_err("The nvram size accoridng to the header seems to be bigger than the partition on flash\n");
|
||||
if (header->len > NVRAM_SPACE)
|
||||
pr_err("nvram on flash (%i bytes) is bigger than the reserved space in memory, will just copy the first %i bytes\n",
|
||||
header->len, NVRAM_SPACE);
|
||||
|
||||
src = (u32 *) header;
|
||||
dst = (u32 *) nvram_buf;
|
||||
for (i = 0; i < sizeof(struct nvram_header); i += 4)
|
||||
*dst++ = *src++;
|
||||
for (; i < header->len && i < NVRAM_SPACE; i += 4)
|
||||
for (; i < header->len && i < NVRAM_SPACE && i < size; i += 4)
|
||||
*dst++ = le32_to_cpu(*src++);
|
||||
memset(dst, 0x0, NVRAM_SPACE - i);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int nvram_getenv(char *name, char *val, size_t val_len)
|
||||
#ifdef CONFIG_BCM47XX_SSB
|
||||
static int nvram_init_ssb(void)
|
||||
{
|
||||
struct ssb_mipscore *mcore = &bcm47xx_bus.ssb.mipscore;
|
||||
u32 base;
|
||||
u32 lim;
|
||||
|
||||
if (mcore->pflash.present) {
|
||||
base = mcore->pflash.window;
|
||||
lim = mcore->pflash.window_size;
|
||||
} else {
|
||||
pr_err("Couldn't find supported flash memory\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
return nvram_find_and_copy(base, lim);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BCM47XX_BCMA
|
||||
static int nvram_init_bcma(void)
|
||||
{
|
||||
struct bcma_drv_cc *cc = &bcm47xx_bus.bcma.bus.drv_cc;
|
||||
u32 base;
|
||||
u32 lim;
|
||||
|
||||
#ifdef CONFIG_BCMA_NFLASH
|
||||
if (cc->nflash.boot) {
|
||||
base = BCMA_SOC_FLASH1;
|
||||
lim = BCMA_SOC_FLASH1_SZ;
|
||||
} else
|
||||
#endif
|
||||
if (cc->pflash.present) {
|
||||
base = cc->pflash.window;
|
||||
lim = cc->pflash.window_size;
|
||||
#ifdef CONFIG_BCMA_SFLASH
|
||||
} else if (cc->sflash.present) {
|
||||
base = cc->sflash.window;
|
||||
lim = cc->sflash.size;
|
||||
#endif
|
||||
} else {
|
||||
pr_err("Couldn't find supported flash memory\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
return nvram_find_and_copy(base, lim);
|
||||
}
|
||||
#endif
|
||||
|
||||
static int nvram_init(void)
|
||||
{
|
||||
switch (bcm47xx_bus_type) {
|
||||
#ifdef CONFIG_BCM47XX_SSB
|
||||
case BCM47XX_BUS_TYPE_SSB:
|
||||
return nvram_init_ssb();
|
||||
#endif
|
||||
#ifdef CONFIG_BCM47XX_BCMA
|
||||
case BCM47XX_BUS_TYPE_BCMA:
|
||||
return nvram_init_bcma();
|
||||
#endif
|
||||
}
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
int bcm47xx_nvram_getenv(char *name, char *val, size_t val_len)
|
||||
{
|
||||
char *var, *value, *end, *eq;
|
||||
int err;
|
||||
|
||||
if (!name)
|
||||
return NVRAM_ERR_INV_PARAM;
|
||||
return -EINVAL;
|
||||
|
||||
if (!nvram_buf[0])
|
||||
early_nvram_init();
|
||||
if (!nvram_buf[0]) {
|
||||
err = nvram_init();
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
|
||||
/* Look for name=value and return value */
|
||||
var = &nvram_buf[sizeof(struct nvram_header)];
|
||||
|
@ -110,6 +187,6 @@ int nvram_getenv(char *name, char *val, size_t val_len)
|
|||
return snprintf(val, val_len, "%s", value);
|
||||
}
|
||||
}
|
||||
return NVRAM_ERR_ENVNOTFOUND;
|
||||
return -ENOENT;
|
||||
}
|
||||
EXPORT_SYMBOL(nvram_getenv);
|
||||
EXPORT_SYMBOL(bcm47xx_nvram_getenv);
|
||||
|
|
|
@ -35,7 +35,7 @@
|
|||
#include <asm/reboot.h>
|
||||
#include <asm/time.h>
|
||||
#include <bcm47xx.h>
|
||||
#include <asm/mach-bcm47xx/nvram.h>
|
||||
#include <bcm47xx_nvram.h>
|
||||
|
||||
union bcm47xx_bus bcm47xx_bus;
|
||||
EXPORT_SYMBOL(bcm47xx_bus);
|
||||
|
@ -115,7 +115,7 @@ static int bcm47xx_get_invariants(struct ssb_bus *bus,
|
|||
memset(&iv->sprom, 0, sizeof(struct ssb_sprom));
|
||||
bcm47xx_fill_sprom(&iv->sprom, NULL, false);
|
||||
|
||||
if (nvram_getenv("cardbus", buf, sizeof(buf)) >= 0)
|
||||
if (bcm47xx_nvram_getenv("cardbus", buf, sizeof(buf)) >= 0)
|
||||
iv->has_cardbus_slot = !!simple_strtoul(buf, NULL, 10);
|
||||
|
||||
return 0;
|
||||
|
@ -138,7 +138,7 @@ static void __init bcm47xx_register_ssb(void)
|
|||
panic("Failed to initialize SSB bus (err %d)", err);
|
||||
|
||||
mcore = &bcm47xx_bus.ssb.mipscore;
|
||||
if (nvram_getenv("kernel_args", buf, sizeof(buf)) >= 0) {
|
||||
if (bcm47xx_nvram_getenv("kernel_args", buf, sizeof(buf)) >= 0) {
|
||||
if (strstr(buf, "console=ttyS1")) {
|
||||
struct ssb_serial_port port;
|
||||
|
||||
|
|
|
@ -27,7 +27,7 @@
|
|||
*/
|
||||
|
||||
#include <bcm47xx.h>
|
||||
#include <nvram.h>
|
||||
#include <bcm47xx_nvram.h>
|
||||
|
||||
static void create_key(const char *prefix, const char *postfix,
|
||||
const char *name, char *buf, int len)
|
||||
|
@ -50,10 +50,10 @@ static int get_nvram_var(const char *prefix, const char *postfix,
|
|||
|
||||
create_key(prefix, postfix, name, key, sizeof(key));
|
||||
|
||||
err = nvram_getenv(key, buf, len);
|
||||
if (fallback && err == NVRAM_ERR_ENVNOTFOUND && prefix) {
|
||||
err = bcm47xx_nvram_getenv(key, buf, len);
|
||||
if (fallback && err == -ENOENT && prefix) {
|
||||
create_key(NULL, postfix, name, key, sizeof(key));
|
||||
err = nvram_getenv(key, buf, len);
|
||||
err = bcm47xx_nvram_getenv(key, buf, len);
|
||||
}
|
||||
return err;
|
||||
}
|
||||
|
@ -71,7 +71,7 @@ static void nvram_read_ ## type (const char *prefix, \
|
|||
fallback); \
|
||||
if (err < 0) \
|
||||
return; \
|
||||
err = kstrto ## type (buf, 0, &var); \
|
||||
err = kstrto ## type(strim(buf), 0, &var); \
|
||||
if (err) { \
|
||||
pr_warn("can not parse nvram name %s%s%s with value %s got %i\n", \
|
||||
prefix, name, postfix, buf, err); \
|
||||
|
@ -99,7 +99,7 @@ static void nvram_read_u32_2(const char *prefix, const char *name,
|
|||
err = get_nvram_var(prefix, NULL, name, buf, sizeof(buf), fallback);
|
||||
if (err < 0)
|
||||
return;
|
||||
err = kstrtou32(buf, 0, &val);
|
||||
err = kstrtou32(strim(buf), 0, &val);
|
||||
if (err) {
|
||||
pr_warn("can not parse nvram name %s%s with value %s got %i\n",
|
||||
prefix, name, buf, err);
|
||||
|
@ -120,7 +120,7 @@ static void nvram_read_leddc(const char *prefix, const char *name,
|
|||
err = get_nvram_var(prefix, NULL, name, buf, sizeof(buf), fallback);
|
||||
if (err < 0)
|
||||
return;
|
||||
err = kstrtou32(buf, 0, &val);
|
||||
err = kstrtou32(strim(buf), 0, &val);
|
||||
if (err) {
|
||||
pr_warn("can not parse nvram name %s%s with value %s got %i\n",
|
||||
prefix, name, buf, err);
|
||||
|
@ -144,7 +144,7 @@ static void nvram_read_macaddr(const char *prefix, const char *name,
|
|||
if (err < 0)
|
||||
return;
|
||||
|
||||
nvram_parse_macaddr(buf, *val);
|
||||
bcm47xx_nvram_parse_macaddr(buf, *val);
|
||||
}
|
||||
|
||||
static void nvram_read_alpha2(const char *prefix, const char *name,
|
||||
|
@ -652,12 +652,10 @@ static void bcm47xx_fill_sprom_ethernet(struct ssb_sprom *sprom,
|
|||
static void bcm47xx_fill_board_data(struct ssb_sprom *sprom, const char *prefix,
|
||||
bool fallback)
|
||||
{
|
||||
nvram_read_u16(prefix, NULL, "boardrev", &sprom->board_rev, 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "boardrev", &sprom->board_rev, 0, true);
|
||||
nvram_read_u16(prefix, NULL, "boardnum", &sprom->board_num, 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "boardtype", &sprom->board_type, 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "boardtype", &sprom->board_type, 0, true);
|
||||
nvram_read_u32_2(prefix, "boardflags", &sprom->boardflags_lo,
|
||||
&sprom->boardflags_hi, fallback);
|
||||
nvram_read_u32_2(prefix, "boardflags2", &sprom->boardflags2_lo,
|
||||
|
|
|
@ -10,7 +10,7 @@
|
|||
#include <bcm63xx_io.h>
|
||||
#include <bcm63xx_regs.h>
|
||||
|
||||
static void __init wait_xfered(void)
|
||||
static void wait_xfered(void)
|
||||
{
|
||||
unsigned int val;
|
||||
|
||||
|
@ -22,7 +22,7 @@ static void __init wait_xfered(void)
|
|||
} while (1);
|
||||
}
|
||||
|
||||
void __init prom_putchar(char c)
|
||||
void prom_putchar(char c)
|
||||
{
|
||||
wait_xfered();
|
||||
bcm_uart0_writel(c, UART_FIFO_REG);
|
||||
|
|
|
@ -94,4 +94,13 @@ config SWIOTLB
|
|||
select NEED_SG_DMA_LENGTH
|
||||
|
||||
|
||||
config OCTEON_ILM
|
||||
tristate "Module to measure interrupt latency using Octeon CIU Timer"
|
||||
help
|
||||
This driver is a module to measure interrupt latency using the
|
||||
the CIU Timers on Octeon.
|
||||
|
||||
To compile this driver as a module, choose M here. The module
|
||||
will be called octeon-ilm
|
||||
|
||||
endif # CPU_CAVIUM_OCTEON
|
||||
|
|
|
@ -18,6 +18,7 @@ obj-y += octeon-memcpy.o
|
|||
obj-y += executive/
|
||||
|
||||
obj-$(CONFIG_SMP) += smp.o
|
||||
obj-$(CONFIG_OCTEON_ILM) += oct_ilm.o
|
||||
|
||||
DTS_FILES = octeon_3xxx.dts octeon_68xx.dts
|
||||
DTB_FILES = $(patsubst %.dts, %.dtb, $(DTS_FILES))
|
||||
|
|
|
@ -0,0 +1,206 @@
|
|||
#include <linux/fs.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <asm/octeon/octeon.h>
|
||||
#include <asm/octeon/cvmx-ciu-defs.h>
|
||||
#include <asm/octeon/cvmx.h>
|
||||
#include <linux/debugfs.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/seq_file.h>
|
||||
|
||||
#define TIMER_NUM 3
|
||||
|
||||
static bool reset_stats;
|
||||
|
||||
struct latency_info {
|
||||
u64 io_interval;
|
||||
u64 cpu_interval;
|
||||
u64 timer_start1;
|
||||
u64 timer_start2;
|
||||
u64 max_latency;
|
||||
u64 min_latency;
|
||||
u64 latency_sum;
|
||||
u64 average_latency;
|
||||
u64 interrupt_cnt;
|
||||
};
|
||||
|
||||
static struct latency_info li;
|
||||
static struct dentry *dir;
|
||||
|
||||
static int show_latency(struct seq_file *m, void *v)
|
||||
{
|
||||
u64 cpuclk, avg, max, min;
|
||||
struct latency_info curr_li = li;
|
||||
|
||||
cpuclk = octeon_get_clock_rate();
|
||||
|
||||
max = (curr_li.max_latency * 1000000000) / cpuclk;
|
||||
min = (curr_li.min_latency * 1000000000) / cpuclk;
|
||||
avg = (curr_li.latency_sum * 1000000000) / (cpuclk * curr_li.interrupt_cnt);
|
||||
|
||||
seq_printf(m, "cnt: %10lld, avg: %7lld ns, max: %7lld ns, min: %7lld ns\n",
|
||||
curr_li.interrupt_cnt, avg, max, min);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int oct_ilm_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
return single_open(file, show_latency, NULL);
|
||||
}
|
||||
|
||||
static const struct file_operations oct_ilm_ops = {
|
||||
.open = oct_ilm_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
};
|
||||
|
||||
static int reset_statistics(void *data, u64 value)
|
||||
{
|
||||
reset_stats = true;
|
||||
return 0;
|
||||
}
|
||||
|
||||
DEFINE_SIMPLE_ATTRIBUTE(reset_statistics_ops, NULL, reset_statistics, "%llu\n");
|
||||
|
||||
static int init_debufs(void)
|
||||
{
|
||||
struct dentry *show_dentry;
|
||||
dir = debugfs_create_dir("oct_ilm", 0);
|
||||
if (!dir) {
|
||||
pr_err("oct_ilm: failed to create debugfs entry oct_ilm\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
show_dentry = debugfs_create_file("statistics", 0222, dir, NULL,
|
||||
&oct_ilm_ops);
|
||||
if (!show_dentry) {
|
||||
pr_err("oct_ilm: failed to create debugfs entry oct_ilm/statistics\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
show_dentry = debugfs_create_file("reset", 0222, dir, NULL,
|
||||
&reset_statistics_ops);
|
||||
if (!show_dentry) {
|
||||
pr_err("oct_ilm: failed to create debugfs entry oct_ilm/reset\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
static void init_latency_info(struct latency_info *li, int startup)
|
||||
{
|
||||
/* interval in milli seconds after which the interrupt will
|
||||
* be triggered
|
||||
*/
|
||||
int interval = 1;
|
||||
|
||||
if (startup) {
|
||||
/* Calculating by the amounts io clock and cpu clock would
|
||||
* increment in interval amount of ms
|
||||
*/
|
||||
li->io_interval = (octeon_get_io_clock_rate() * interval) / 1000;
|
||||
li->cpu_interval = (octeon_get_clock_rate() * interval) / 1000;
|
||||
}
|
||||
li->timer_start1 = 0;
|
||||
li->timer_start2 = 0;
|
||||
li->max_latency = 0;
|
||||
li->min_latency = (u64)-1;
|
||||
li->latency_sum = 0;
|
||||
li->interrupt_cnt = 0;
|
||||
}
|
||||
|
||||
|
||||
static void start_timer(int timer, u64 interval)
|
||||
{
|
||||
union cvmx_ciu_timx timx;
|
||||
unsigned long flags;
|
||||
|
||||
timx.u64 = 0;
|
||||
timx.s.one_shot = 1;
|
||||
timx.s.len = interval;
|
||||
raw_local_irq_save(flags);
|
||||
li.timer_start1 = read_c0_cvmcount();
|
||||
cvmx_write_csr(CVMX_CIU_TIMX(timer), timx.u64);
|
||||
/* Read it back to force wait until register is written. */
|
||||
timx.u64 = cvmx_read_csr(CVMX_CIU_TIMX(timer));
|
||||
li.timer_start2 = read_c0_cvmcount();
|
||||
raw_local_irq_restore(flags);
|
||||
}
|
||||
|
||||
|
||||
static irqreturn_t cvm_oct_ciu_timer_interrupt(int cpl, void *dev_id)
|
||||
{
|
||||
u64 last_latency;
|
||||
u64 last_int_cnt;
|
||||
|
||||
if (reset_stats) {
|
||||
init_latency_info(&li, 0);
|
||||
reset_stats = false;
|
||||
} else {
|
||||
last_int_cnt = read_c0_cvmcount();
|
||||
last_latency = last_int_cnt - (li.timer_start1 + li.cpu_interval);
|
||||
li.interrupt_cnt++;
|
||||
li.latency_sum += last_latency;
|
||||
if (last_latency > li.max_latency)
|
||||
li.max_latency = last_latency;
|
||||
if (last_latency < li.min_latency)
|
||||
li.min_latency = last_latency;
|
||||
}
|
||||
start_timer(TIMER_NUM, li.io_interval);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void disable_timer(int timer)
|
||||
{
|
||||
union cvmx_ciu_timx timx;
|
||||
|
||||
timx.s.one_shot = 0;
|
||||
timx.s.len = 0;
|
||||
cvmx_write_csr(CVMX_CIU_TIMX(timer), timx.u64);
|
||||
/* Read it back to force immediate write of timer register*/
|
||||
timx.u64 = cvmx_read_csr(CVMX_CIU_TIMX(timer));
|
||||
}
|
||||
|
||||
static __init int oct_ilm_module_init(void)
|
||||
{
|
||||
int rc;
|
||||
int irq = OCTEON_IRQ_TIMER0 + TIMER_NUM;
|
||||
|
||||
rc = init_debufs();
|
||||
if (rc) {
|
||||
WARN(1, "Could not create debugfs entries");
|
||||
return rc;
|
||||
}
|
||||
|
||||
rc = request_irq(irq, cvm_oct_ciu_timer_interrupt, IRQF_NO_THREAD,
|
||||
"oct_ilm", 0);
|
||||
if (rc) {
|
||||
WARN(1, "Could not acquire IRQ %d", irq);
|
||||
goto err_irq;
|
||||
}
|
||||
|
||||
init_latency_info(&li, 1);
|
||||
start_timer(TIMER_NUM, li.io_interval);
|
||||
|
||||
return 0;
|
||||
err_irq:
|
||||
debugfs_remove_recursive(dir);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static __exit void oct_ilm_module_exit(void)
|
||||
{
|
||||
disable_timer(TIMER_NUM);
|
||||
if (dir)
|
||||
debugfs_remove_recursive(dir);
|
||||
free_irq(OCTEON_IRQ_TIMER0 + TIMER_NUM, 0);
|
||||
}
|
||||
|
||||
module_exit(oct_ilm_module_exit);
|
||||
module_init(oct_ilm_module_init);
|
||||
MODULE_AUTHOR("Venkat Subbiah, Cavium");
|
||||
MODULE_DESCRIPTION("Measures interrupt latency on Octeon chips.");
|
||||
MODULE_LICENSE("GPL");
|
|
@ -1,5 +1,6 @@
|
|||
CONFIG_ATH79=y
|
||||
CONFIG_ATH79_MACH_AP121=y
|
||||
CONFIG_ATH79_MACH_AP136=y
|
||||
CONFIG_ATH79_MACH_AP81=y
|
||||
CONFIG_ATH79_MACH_DB120=y
|
||||
CONFIG_ATH79_MACH_PB44=y
|
||||
|
|
|
@ -1,98 +0,0 @@
|
|||
CONFIG_PNX8550_JBS=y
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
|
||||
CONFIG_EXPERT=y
|
||||
# CONFIG_SYSCTL_SYSCALL is not set
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_XFRM_MIGRATE=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
CONFIG_TCP_MD5SIG=y
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=8192
|
||||
CONFIG_SGI_IOC4=m
|
||||
CONFIG_IDE=y
|
||||
CONFIG_BLK_DEV_IDECD=m
|
||||
CONFIG_IDE_GENERIC=y
|
||||
CONFIG_BLK_DEV_OFFBOARD=y
|
||||
CONFIG_BLK_DEV_GENERIC=y
|
||||
CONFIG_BLK_DEV_HPT366=y
|
||||
CONFIG_BLK_DEV_IT8213=m
|
||||
CONFIG_BLK_DEV_TC86C001=m
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SCSI_TGT=m
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_SCSI_CONSTANTS=y
|
||||
CONFIG_SCSI_SCAN_ASYNC=y
|
||||
CONFIG_SCSI_FC_ATTRS=y
|
||||
CONFIG_ISCSI_TCP=m
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_NET_ETHERNET=y
|
||||
CONFIG_NET_PCI=y
|
||||
CONFIG_8139TOO=y
|
||||
# CONFIG_8139TOO_PIO is not set
|
||||
CONFIG_8139TOO_TUNE_TWISTER=y
|
||||
CONFIG_8139TOO_8129=y
|
||||
CONFIG_CHELSIO_T3=m
|
||||
CONFIG_NETXEN_NIC=m
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_SERIO_I8042 is not set
|
||||
# CONFIG_SERIO_SERPORT is not set
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
CONFIG_SERIAL_PNX8XXX=y
|
||||
CONFIG_SERIAL_PNX8XXX_CONSOLE=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
# CONFIG_VGA_CONSOLE is not set
|
||||
# CONFIG_HID is not set
|
||||
# CONFIG_USB_HID is not set
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_MON=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_STORAGE_DATAFAB=y
|
||||
CONFIG_USB_STORAGE_FREECOM=y
|
||||
CONFIG_USB_STORAGE_ISD200=y
|
||||
CONFIG_USB_STORAGE_USBAT=y
|
||||
CONFIG_USB_STORAGE_SDDR09=y
|
||||
CONFIG_USB_STORAGE_SDDR55=y
|
||||
CONFIG_USB_STORAGE_JUMPSHOT=y
|
||||
CONFIG_EXT2_FS=y
|
||||
# CONFIG_DNOTIFY is not set
|
||||
CONFIG_MSDOS_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_NFSD=m
|
||||
CONFIG_DLM=m
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_DEBUG_SLAB=y
|
||||
CONFIG_DEBUG_MUTEXES=y
|
||||
CONFIG_CMDLINE_BOOL=y
|
||||
CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp"
|
||||
CONFIG_CRYPTO_CBC=m
|
||||
CONFIG_CRYPTO_ECB=m
|
||||
CONFIG_CRYPTO_LRW=m
|
||||
CONFIG_CRYPTO_PCBC=m
|
||||
CONFIG_CRYPTO_XCBC=m
|
||||
CONFIG_CRYPTO_CAMELLIA=m
|
||||
CONFIG_CRYPTO_FCRYPT=m
|
||||
CONFIG_CRC_CCITT=m
|
|
@ -1,92 +0,0 @@
|
|||
CONFIG_PNX8550_STB810=y
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
|
||||
CONFIG_EXPERT=y
|
||||
# CONFIG_SYSCTL_SYSCALL is not set
|
||||
# CONFIG_HOTPLUG is not set
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_XFRM_MIGRATE=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=8192
|
||||
CONFIG_IDE=y
|
||||
CONFIG_BLK_DEV_IDECD=m
|
||||
CONFIG_IDE_GENERIC=y
|
||||
CONFIG_BLK_DEV_OFFBOARD=y
|
||||
CONFIG_BLK_DEV_GENERIC=y
|
||||
CONFIG_BLK_DEV_HPT366=y
|
||||
CONFIG_BLK_DEV_IT8213=m
|
||||
CONFIG_BLK_DEV_TC86C001=m
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SCSI_TGT=m
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_SCSI_CONSTANTS=y
|
||||
CONFIG_SCSI_SCAN_ASYNC=y
|
||||
CONFIG_ISCSI_TCP=m
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_NET_ETHERNET=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_NET_PCI=y
|
||||
CONFIG_NATSEMI=y
|
||||
CONFIG_CHELSIO_T3=m
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_SERIO_I8042 is not set
|
||||
# CONFIG_SERIO_SERPORT is not set
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
# CONFIG_VGA_CONSOLE is not set
|
||||
# CONFIG_HID is not set
|
||||
# CONFIG_USB_HID is not set
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_MON=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_STORAGE_DATAFAB=y
|
||||
CONFIG_USB_STORAGE_FREECOM=y
|
||||
CONFIG_USB_STORAGE_ISD200=y
|
||||
CONFIG_USB_STORAGE_USBAT=y
|
||||
CONFIG_USB_STORAGE_SDDR09=y
|
||||
CONFIG_USB_STORAGE_SDDR55=y
|
||||
CONFIG_USB_STORAGE_JUMPSHOT=y
|
||||
CONFIG_EXT2_FS=y
|
||||
# CONFIG_DNOTIFY is not set
|
||||
CONFIG_MSDOS_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_NFSD=m
|
||||
CONFIG_DLM=m
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_HEADERS_CHECK=y
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_DEBUG_SLAB=y
|
||||
CONFIG_CMDLINE_BOOL=y
|
||||
CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp"
|
||||
CONFIG_CRYPTO_CBC=m
|
||||
CONFIG_CRYPTO_ECB=m
|
||||
CONFIG_CRYPTO_LRW=m
|
||||
CONFIG_CRYPTO_PCBC=m
|
||||
CONFIG_CRYPTO_XCBC=m
|
||||
CONFIG_CRYPTO_CAMELLIA=m
|
||||
CONFIG_CRYPTO_FCRYPT=m
|
||||
CONFIG_CRC_CCITT=m
|
|
@ -0,0 +1,167 @@
|
|||
CONFIG_RALINK=y
|
||||
CONFIG_DTB_RT305X_EVAL=y
|
||||
CONFIG_CPU_MIPS32_R2=y
|
||||
# CONFIG_COMPACTION is not set
|
||||
# CONFIG_CROSS_MEMORY_ATTACH is not set
|
||||
CONFIG_HZ_100=y
|
||||
# CONFIG_SECCOMP is not set
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
# CONFIG_LOCALVERSION_AUTO is not set
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
CONFIG_INITRAMFS_ROOT_UID=1000
|
||||
CONFIG_INITRAMFS_ROOT_GID=1000
|
||||
# CONFIG_RD_GZIP is not set
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
# CONFIG_AIO is not set
|
||||
CONFIG_EMBEDDED=y
|
||||
# CONFIG_VM_EVENT_COUNTERS is not set
|
||||
# CONFIG_SLUB_DEBUG is not set
|
||||
# CONFIG_COMPAT_BRK is not set
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
# CONFIG_COREDUMP is not set
|
||||
# CONFIG_SUSPEND is not set
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_IP_ADVANCED_ROUTER=y
|
||||
CONFIG_IP_MULTIPLE_TABLES=y
|
||||
CONFIG_IP_ROUTE_MULTIPATH=y
|
||||
CONFIG_IP_ROUTE_VERBOSE=y
|
||||
CONFIG_IP_MROUTE=y
|
||||
CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
|
||||
CONFIG_ARPD=y
|
||||
CONFIG_SYN_COOKIES=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
# CONFIG_INET_DIAG is not set
|
||||
CONFIG_TCP_CONG_ADVANCED=y
|
||||
# CONFIG_TCP_CONG_BIC is not set
|
||||
# CONFIG_TCP_CONG_WESTWOOD is not set
|
||||
# CONFIG_TCP_CONG_HTCP is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_NETFILTER=y
|
||||
# CONFIG_BRIDGE_NETFILTER is not set
|
||||
CONFIG_NF_CONNTRACK=m
|
||||
CONFIG_NF_CONNTRACK_FTP=m
|
||||
CONFIG_NF_CONNTRACK_IRC=m
|
||||
CONFIG_NETFILTER_XT_TARGET_CT=m
|
||||
CONFIG_NETFILTER_XT_TARGET_LOG=m
|
||||
CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
|
||||
CONFIG_NETFILTER_XT_MATCH_COMMENT=m
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
|
||||
CONFIG_NETFILTER_XT_MATCH_LIMIT=m
|
||||
CONFIG_NETFILTER_XT_MATCH_MAC=m
|
||||
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
|
||||
CONFIG_NETFILTER_XT_MATCH_STATE=m
|
||||
CONFIG_NF_CONNTRACK_IPV4=m
|
||||
# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
|
||||
CONFIG_IP_NF_IPTABLES=m
|
||||
CONFIG_IP_NF_FILTER=m
|
||||
CONFIG_IP_NF_TARGET_REJECT=m
|
||||
CONFIG_IP_NF_MANGLE=m
|
||||
CONFIG_IP_NF_RAW=m
|
||||
CONFIG_BRIDGE=y
|
||||
# CONFIG_BRIDGE_IGMP_SNOOPING is not set
|
||||
CONFIG_VLAN_8021Q=y
|
||||
CONFIG_NET_SCHED=y
|
||||
CONFIG_HAMRADIO=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
# CONFIG_FIRMWARE_IN_KERNEL is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_CFI_AMDSTD=y
|
||||
CONFIG_MTD_COMPLEX_MAPPINGS=y
|
||||
CONFIG_MTD_PHYSMAP=y
|
||||
CONFIG_MTD_PHYSMAP_OF=y
|
||||
CONFIG_MTD_M25P80=y
|
||||
CONFIG_EEPROM_93CX6=m
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_NETDEVICES=y
|
||||
# CONFIG_NET_VENDOR_WIZNET is not set
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PPP=m
|
||||
CONFIG_PPP_FILTER=y
|
||||
CONFIG_PPP_MULTILINK=y
|
||||
CONFIG_PPPOE=m
|
||||
CONFIG_PPP_ASYNC=m
|
||||
CONFIG_ISDN=y
|
||||
CONFIG_INPUT=m
|
||||
CONFIG_INPUT_POLLDEV=m
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
# CONFIG_KEYBOARD_ATKBD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
CONFIG_INPUT_MISC=y
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_VT is not set
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
# CONFIG_DEVKMEM is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
CONFIG_SPI=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_WATCHDOG=y
|
||||
# CONFIG_HID is not set
|
||||
# CONFIG_USB_HID is not set
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_STORAGE_DEBUG=y
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
CONFIG_LEDS_TRIGGERS=y
|
||||
CONFIG_LEDS_TRIGGER_TIMER=y
|
||||
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
|
||||
CONFIG_STAGING=y
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
# CONFIG_DNOTIFY is not set
|
||||
# CONFIG_PROC_PAGE_MONITOR is not set
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_TMPFS_XATTR=y
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_JFFS2_SUMMARY=y
|
||||
CONFIG_JFFS2_FS_XATTR=y
|
||||
# CONFIG_JFFS2_FS_POSIX_ACL is not set
|
||||
# CONFIG_JFFS2_FS_SECURITY is not set
|
||||
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
|
||||
# CONFIG_JFFS2_ZLIB is not set
|
||||
CONFIG_SQUASHFS=y
|
||||
# CONFIG_SQUASHFS_ZLIB is not set
|
||||
CONFIG_SQUASHFS_XZ=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
# CONFIG_ENABLE_MUST_CHECK is not set
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_STRIP_ASM_SYMS=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
# CONFIG_FTRACE is not set
|
||||
CONFIG_CMDLINE_BOOL=y
|
||||
CONFIG_CRYPTO_MANAGER=m
|
||||
CONFIG_CRYPTO_ARC4=m
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
CONFIG_CRC_ITU_T=m
|
||||
CONFIG_CRC32_SARWATE=y
|
||||
# CONFIG_XZ_DEC_X86 is not set
|
||||
# CONFIG_XZ_DEC_POWERPC is not set
|
||||
# CONFIG_XZ_DEC_IA64 is not set
|
||||
# CONFIG_XZ_DEC_ARM is not set
|
||||
# CONFIG_XZ_DEC_ARMTHUMB is not set
|
||||
# CONFIG_XZ_DEC_SPARC is not set
|
||||
CONFIG_AVERAGE=y
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 1995, 2003 by Ralf Baechle
|
||||
* Copyright (C) 1999 Silicon Graphics, Inc.
|
||||
*/
|
||||
#ifndef __ASM_BREAK_H
|
||||
#define __ASM_BREAK_H
|
||||
|
||||
#ifdef __UAPI_ASM_BREAK_H
|
||||
#error "Error: Do not directly include <uapi/asm/break.h>"
|
||||
#endif
|
||||
#include <uapi/asm/break.h>
|
||||
|
||||
/*
|
||||
* Break codes used internally to the kernel.
|
||||
*/
|
||||
#define BRK_KDB 513 /* Used in KDB_ENTER() */
|
||||
#define BRK_MEMU 514 /* Used by FPU emulator */
|
||||
#define BRK_KPROBE_BP 515 /* Kprobe break */
|
||||
#define BRK_KPROBE_SSTEPBP 516 /* Kprobe single step software implementation */
|
||||
#define BRK_MULOVF 1023 /* Multiply overflow */
|
||||
|
||||
#endif /* __ASM_BREAK_H */
|
|
@ -98,6 +98,9 @@
|
|||
#ifndef cpu_has_rixi
|
||||
#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI)
|
||||
#endif
|
||||
#ifndef cpu_has_mmips
|
||||
#define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS)
|
||||
#endif
|
||||
#ifndef cpu_has_vtag_icache
|
||||
#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
|
||||
#endif
|
||||
|
@ -130,6 +133,19 @@
|
|||
#endif
|
||||
#endif
|
||||
|
||||
# define cpu_has_mips_1 (cpu_data[0].isa_level & MIPS_CPU_ISA_I)
|
||||
#ifndef cpu_has_mips_2
|
||||
# define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II)
|
||||
#endif
|
||||
#ifndef cpu_has_mips_3
|
||||
# define cpu_has_mips_3 (cpu_data[0].isa_level & MIPS_CPU_ISA_III)
|
||||
#endif
|
||||
#ifndef cpu_has_mips_4
|
||||
# define cpu_has_mips_4 (cpu_data[0].isa_level & MIPS_CPU_ISA_IV)
|
||||
#endif
|
||||
#ifndef cpu_has_mips_5
|
||||
# define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V)
|
||||
#endif
|
||||
# ifndef cpu_has_mips32r1
|
||||
# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
|
||||
# endif
|
||||
|
@ -260,4 +276,8 @@
|
|||
#define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI)
|
||||
#endif
|
||||
|
||||
#ifndef cpu_has_vz
|
||||
#define cpu_has_vz (cpu_data[0].ases & MIPS_ASE_VZ)
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_CPU_FEATURES_H */
|
||||
|
|
|
@ -96,6 +96,7 @@
|
|||
#define PRID_IMP_1004K 0x9900
|
||||
#define PRID_IMP_1074K 0x9a00
|
||||
#define PRID_IMP_M14KC 0x9c00
|
||||
#define PRID_IMP_M14KEC 0x9e00
|
||||
|
||||
/*
|
||||
* These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
|
||||
|
@ -264,6 +265,7 @@ enum cpu_type_enum {
|
|||
CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
|
||||
CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
|
||||
CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
|
||||
CPU_M14KEC,
|
||||
|
||||
/*
|
||||
* MIPS64 class processors
|
||||
|
@ -322,6 +324,7 @@ enum cpu_type_enum {
|
|||
#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */
|
||||
#define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */
|
||||
#define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */
|
||||
#define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */
|
||||
|
||||
/*
|
||||
* CPU ASE encodings
|
||||
|
@ -333,6 +336,6 @@ enum cpu_type_enum {
|
|||
#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */
|
||||
#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */
|
||||
#define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */
|
||||
|
||||
#define MIPS_ASE_VZ 0x00000080 /* Virtualization ASE */
|
||||
|
||||
#endif /* _ASM_CPU_H */
|
||||
|
|
|
@ -359,6 +359,7 @@ struct gic_shared_intr_map {
|
|||
/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
|
||||
#define GIC_PIN_TO_VEC_OFFSET (1)
|
||||
|
||||
extern int gic_present;
|
||||
extern unsigned long _gic_base;
|
||||
extern unsigned int gic_irq_base;
|
||||
extern unsigned int gic_irq_flags[];
|
||||
|
|
|
@ -141,7 +141,7 @@ do { \
|
|||
|
||||
#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
|
||||
defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \
|
||||
defined(CONFIG_CPU_R5500)
|
||||
defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_XLR)
|
||||
|
||||
/*
|
||||
* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
|
||||
|
|
|
@ -11,353 +11,7 @@
|
|||
#ifndef _ASM_INST_H
|
||||
#define _ASM_INST_H
|
||||
|
||||
/*
|
||||
* Major opcodes; before MIPS IV cop1x was called cop3.
|
||||
*/
|
||||
enum major_op {
|
||||
spec_op, bcond_op, j_op, jal_op,
|
||||
beq_op, bne_op, blez_op, bgtz_op,
|
||||
addi_op, addiu_op, slti_op, sltiu_op,
|
||||
andi_op, ori_op, xori_op, lui_op,
|
||||
cop0_op, cop1_op, cop2_op, cop1x_op,
|
||||
beql_op, bnel_op, blezl_op, bgtzl_op,
|
||||
daddi_op, daddiu_op, ldl_op, ldr_op,
|
||||
spec2_op, jalx_op, mdmx_op, spec3_op,
|
||||
lb_op, lh_op, lwl_op, lw_op,
|
||||
lbu_op, lhu_op, lwr_op, lwu_op,
|
||||
sb_op, sh_op, swl_op, sw_op,
|
||||
sdl_op, sdr_op, swr_op, cache_op,
|
||||
ll_op, lwc1_op, lwc2_op, pref_op,
|
||||
lld_op, ldc1_op, ldc2_op, ld_op,
|
||||
sc_op, swc1_op, swc2_op, major_3b_op,
|
||||
scd_op, sdc1_op, sdc2_op, sd_op
|
||||
};
|
||||
|
||||
/*
|
||||
* func field of spec opcode.
|
||||
*/
|
||||
enum spec_op {
|
||||
sll_op, movc_op, srl_op, sra_op,
|
||||
sllv_op, pmon_op, srlv_op, srav_op,
|
||||
jr_op, jalr_op, movz_op, movn_op,
|
||||
syscall_op, break_op, spim_op, sync_op,
|
||||
mfhi_op, mthi_op, mflo_op, mtlo_op,
|
||||
dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
|
||||
mult_op, multu_op, div_op, divu_op,
|
||||
dmult_op, dmultu_op, ddiv_op, ddivu_op,
|
||||
add_op, addu_op, sub_op, subu_op,
|
||||
and_op, or_op, xor_op, nor_op,
|
||||
spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
|
||||
dadd_op, daddu_op, dsub_op, dsubu_op,
|
||||
tge_op, tgeu_op, tlt_op, tltu_op,
|
||||
teq_op, spec5_unused_op, tne_op, spec6_unused_op,
|
||||
dsll_op, spec7_unused_op, dsrl_op, dsra_op,
|
||||
dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
|
||||
};
|
||||
|
||||
/*
|
||||
* func field of spec2 opcode.
|
||||
*/
|
||||
enum spec2_op {
|
||||
madd_op, maddu_op, mul_op, spec2_3_unused_op,
|
||||
msub_op, msubu_op, /* more unused ops */
|
||||
clz_op = 0x20, clo_op,
|
||||
dclz_op = 0x24, dclo_op,
|
||||
sdbpp_op = 0x3f
|
||||
};
|
||||
|
||||
/*
|
||||
* func field of spec3 opcode.
|
||||
*/
|
||||
enum spec3_op {
|
||||
ext_op, dextm_op, dextu_op, dext_op,
|
||||
ins_op, dinsm_op, dinsu_op, dins_op,
|
||||
lx_op = 0x0a,
|
||||
bshfl_op = 0x20,
|
||||
dbshfl_op = 0x24,
|
||||
rdhwr_op = 0x3b
|
||||
};
|
||||
|
||||
/*
|
||||
* rt field of bcond opcodes.
|
||||
*/
|
||||
enum rt_op {
|
||||
bltz_op, bgez_op, bltzl_op, bgezl_op,
|
||||
spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
|
||||
tgei_op, tgeiu_op, tlti_op, tltiu_op,
|
||||
teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
|
||||
bltzal_op, bgezal_op, bltzall_op, bgezall_op,
|
||||
rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
|
||||
rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
|
||||
bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f
|
||||
};
|
||||
|
||||
/*
|
||||
* rs field of cop opcodes.
|
||||
*/
|
||||
enum cop_op {
|
||||
mfc_op = 0x00, dmfc_op = 0x01,
|
||||
cfc_op = 0x02, mtc_op = 0x04,
|
||||
dmtc_op = 0x05, ctc_op = 0x06,
|
||||
bc_op = 0x08, cop_op = 0x10,
|
||||
copm_op = 0x18
|
||||
};
|
||||
|
||||
/*
|
||||
* rt field of cop.bc_op opcodes
|
||||
*/
|
||||
enum bcop_op {
|
||||
bcf_op, bct_op, bcfl_op, bctl_op
|
||||
};
|
||||
|
||||
/*
|
||||
* func field of cop0 coi opcodes.
|
||||
*/
|
||||
enum cop0_coi_func {
|
||||
tlbr_op = 0x01, tlbwi_op = 0x02,
|
||||
tlbwr_op = 0x06, tlbp_op = 0x08,
|
||||
rfe_op = 0x10, eret_op = 0x18
|
||||
};
|
||||
|
||||
/*
|
||||
* func field of cop0 com opcodes.
|
||||
*/
|
||||
enum cop0_com_func {
|
||||
tlbr1_op = 0x01, tlbw_op = 0x02,
|
||||
tlbp1_op = 0x08, dctr_op = 0x09,
|
||||
dctw_op = 0x0a
|
||||
};
|
||||
|
||||
/*
|
||||
* fmt field of cop1 opcodes.
|
||||
*/
|
||||
enum cop1_fmt {
|
||||
s_fmt, d_fmt, e_fmt, q_fmt,
|
||||
w_fmt, l_fmt
|
||||
};
|
||||
|
||||
/*
|
||||
* func field of cop1 instructions using d, s or w format.
|
||||
*/
|
||||
enum cop1_sdw_func {
|
||||
fadd_op = 0x00, fsub_op = 0x01,
|
||||
fmul_op = 0x02, fdiv_op = 0x03,
|
||||
fsqrt_op = 0x04, fabs_op = 0x05,
|
||||
fmov_op = 0x06, fneg_op = 0x07,
|
||||
froundl_op = 0x08, ftruncl_op = 0x09,
|
||||
fceill_op = 0x0a, ffloorl_op = 0x0b,
|
||||
fround_op = 0x0c, ftrunc_op = 0x0d,
|
||||
fceil_op = 0x0e, ffloor_op = 0x0f,
|
||||
fmovc_op = 0x11, fmovz_op = 0x12,
|
||||
fmovn_op = 0x13, frecip_op = 0x15,
|
||||
frsqrt_op = 0x16, fcvts_op = 0x20,
|
||||
fcvtd_op = 0x21, fcvte_op = 0x22,
|
||||
fcvtw_op = 0x24, fcvtl_op = 0x25,
|
||||
fcmp_op = 0x30
|
||||
};
|
||||
|
||||
/*
|
||||
* func field of cop1x opcodes (MIPS IV).
|
||||
*/
|
||||
enum cop1x_func {
|
||||
lwxc1_op = 0x00, ldxc1_op = 0x01,
|
||||
pfetch_op = 0x07, swxc1_op = 0x08,
|
||||
sdxc1_op = 0x09, madd_s_op = 0x20,
|
||||
madd_d_op = 0x21, madd_e_op = 0x22,
|
||||
msub_s_op = 0x28, msub_d_op = 0x29,
|
||||
msub_e_op = 0x2a, nmadd_s_op = 0x30,
|
||||
nmadd_d_op = 0x31, nmadd_e_op = 0x32,
|
||||
nmsub_s_op = 0x38, nmsub_d_op = 0x39,
|
||||
nmsub_e_op = 0x3a
|
||||
};
|
||||
|
||||
/*
|
||||
* func field for mad opcodes (MIPS IV).
|
||||
*/
|
||||
enum mad_func {
|
||||
madd_fp_op = 0x08, msub_fp_op = 0x0a,
|
||||
nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e
|
||||
};
|
||||
|
||||
/*
|
||||
* func field for special3 lx opcodes (Cavium Octeon).
|
||||
*/
|
||||
enum lx_func {
|
||||
lwx_op = 0x00,
|
||||
lhx_op = 0x04,
|
||||
lbux_op = 0x06,
|
||||
ldx_op = 0x08,
|
||||
lwux_op = 0x10,
|
||||
lhux_op = 0x14,
|
||||
lbx_op = 0x16,
|
||||
};
|
||||
|
||||
/*
|
||||
* Damn ... bitfields depend from byteorder :-(
|
||||
*/
|
||||
#ifdef __MIPSEB__
|
||||
struct j_format { /* Jump format */
|
||||
unsigned int opcode : 6;
|
||||
unsigned int target : 26;
|
||||
};
|
||||
|
||||
struct i_format { /* Immediate format (addi, lw, ...) */
|
||||
unsigned int opcode : 6;
|
||||
unsigned int rs : 5;
|
||||
unsigned int rt : 5;
|
||||
signed int simmediate : 16;
|
||||
};
|
||||
|
||||
struct u_format { /* Unsigned immediate format (ori, xori, ...) */
|
||||
unsigned int opcode : 6;
|
||||
unsigned int rs : 5;
|
||||
unsigned int rt : 5;
|
||||
unsigned int uimmediate : 16;
|
||||
};
|
||||
|
||||
struct c_format { /* Cache (>= R6000) format */
|
||||
unsigned int opcode : 6;
|
||||
unsigned int rs : 5;
|
||||
unsigned int c_op : 3;
|
||||
unsigned int cache : 2;
|
||||
unsigned int simmediate : 16;
|
||||
};
|
||||
|
||||
struct r_format { /* Register format */
|
||||
unsigned int opcode : 6;
|
||||
unsigned int rs : 5;
|
||||
unsigned int rt : 5;
|
||||
unsigned int rd : 5;
|
||||
unsigned int re : 5;
|
||||
unsigned int func : 6;
|
||||
};
|
||||
|
||||
struct p_format { /* Performance counter format (R10000) */
|
||||
unsigned int opcode : 6;
|
||||
unsigned int rs : 5;
|
||||
unsigned int rt : 5;
|
||||
unsigned int rd : 5;
|
||||
unsigned int re : 5;
|
||||
unsigned int func : 6;
|
||||
};
|
||||
|
||||
struct f_format { /* FPU register format */
|
||||
unsigned int opcode : 6;
|
||||
unsigned int : 1;
|
||||
unsigned int fmt : 4;
|
||||
unsigned int rt : 5;
|
||||
unsigned int rd : 5;
|
||||
unsigned int re : 5;
|
||||
unsigned int func : 6;
|
||||
};
|
||||
|
||||
struct ma_format { /* FPU multiply and add format (MIPS IV) */
|
||||
unsigned int opcode : 6;
|
||||
unsigned int fr : 5;
|
||||
unsigned int ft : 5;
|
||||
unsigned int fs : 5;
|
||||
unsigned int fd : 5;
|
||||
unsigned int func : 4;
|
||||
unsigned int fmt : 2;
|
||||
};
|
||||
|
||||
struct b_format { /* BREAK and SYSCALL */
|
||||
unsigned int opcode:6;
|
||||
unsigned int code:20;
|
||||
unsigned int func:6;
|
||||
};
|
||||
|
||||
#elif defined(__MIPSEL__)
|
||||
|
||||
struct j_format { /* Jump format */
|
||||
unsigned int target : 26;
|
||||
unsigned int opcode : 6;
|
||||
};
|
||||
|
||||
struct i_format { /* Immediate format */
|
||||
signed int simmediate : 16;
|
||||
unsigned int rt : 5;
|
||||
unsigned int rs : 5;
|
||||
unsigned int opcode : 6;
|
||||
};
|
||||
|
||||
struct u_format { /* Unsigned immediate format */
|
||||
unsigned int uimmediate : 16;
|
||||
unsigned int rt : 5;
|
||||
unsigned int rs : 5;
|
||||
unsigned int opcode : 6;
|
||||
};
|
||||
|
||||
struct c_format { /* Cache (>= R6000) format */
|
||||
unsigned int simmediate : 16;
|
||||
unsigned int cache : 2;
|
||||
unsigned int c_op : 3;
|
||||
unsigned int rs : 5;
|
||||
unsigned int opcode : 6;
|
||||
};
|
||||
|
||||
struct r_format { /* Register format */
|
||||
unsigned int func : 6;
|
||||
unsigned int re : 5;
|
||||
unsigned int rd : 5;
|
||||
unsigned int rt : 5;
|
||||
unsigned int rs : 5;
|
||||
unsigned int opcode : 6;
|
||||
};
|
||||
|
||||
struct p_format { /* Performance counter format (R10000) */
|
||||
unsigned int func : 6;
|
||||
unsigned int re : 5;
|
||||
unsigned int rd : 5;
|
||||
unsigned int rt : 5;
|
||||
unsigned int rs : 5;
|
||||
unsigned int opcode : 6;
|
||||
};
|
||||
|
||||
struct f_format { /* FPU register format */
|
||||
unsigned int func : 6;
|
||||
unsigned int re : 5;
|
||||
unsigned int rd : 5;
|
||||
unsigned int rt : 5;
|
||||
unsigned int fmt : 4;
|
||||
unsigned int : 1;
|
||||
unsigned int opcode : 6;
|
||||
};
|
||||
|
||||
struct ma_format { /* FPU multiply and add format (MIPS IV) */
|
||||
unsigned int fmt : 2;
|
||||
unsigned int func : 4;
|
||||
unsigned int fd : 5;
|
||||
unsigned int fs : 5;
|
||||
unsigned int ft : 5;
|
||||
unsigned int fr : 5;
|
||||
unsigned int opcode : 6;
|
||||
};
|
||||
|
||||
struct b_format { /* BREAK and SYSCALL */
|
||||
unsigned int func:6;
|
||||
unsigned int code:20;
|
||||
unsigned int opcode:6;
|
||||
};
|
||||
|
||||
#else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */
|
||||
#error "MIPS but neither __MIPSEL__ nor __MIPSEB__?"
|
||||
#endif
|
||||
|
||||
union mips_instruction {
|
||||
unsigned int word;
|
||||
unsigned short halfword[2];
|
||||
unsigned char byte[4];
|
||||
struct j_format j_format;
|
||||
struct i_format i_format;
|
||||
struct u_format u_format;
|
||||
struct c_format c_format;
|
||||
struct r_format r_format;
|
||||
struct p_format p_format;
|
||||
struct f_format f_format;
|
||||
struct ma_format ma_format;
|
||||
struct b_format b_format;
|
||||
};
|
||||
#include <uapi/asm/inst.h>
|
||||
|
||||
/* HACHACHAHCAHC ... */
|
||||
|
||||
|
|
|
@ -17,4 +17,10 @@ extern void mips_cpu_irq_init(void);
|
|||
extern void rm7k_cpu_irq_init(void);
|
||||
extern void rm9k_cpu_irq_init(void);
|
||||
|
||||
#ifdef CONFIG_IRQ_DOMAIN
|
||||
struct device_node;
|
||||
extern int mips_cpu_intc_init(struct device_node *of_node,
|
||||
struct device_node *parent);
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_IRQ_CPU_H */
|
||||
|
|
|
@ -41,11 +41,37 @@
|
|||
#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
|
||||
#define AR71XX_RESET_SIZE 0x100
|
||||
|
||||
#define AR71XX_PCI_MEM_BASE 0x10000000
|
||||
#define AR71XX_PCI_MEM_SIZE 0x07000000
|
||||
|
||||
#define AR71XX_PCI_WIN0_OFFS 0x10000000
|
||||
#define AR71XX_PCI_WIN1_OFFS 0x11000000
|
||||
#define AR71XX_PCI_WIN2_OFFS 0x12000000
|
||||
#define AR71XX_PCI_WIN3_OFFS 0x13000000
|
||||
#define AR71XX_PCI_WIN4_OFFS 0x14000000
|
||||
#define AR71XX_PCI_WIN5_OFFS 0x15000000
|
||||
#define AR71XX_PCI_WIN6_OFFS 0x16000000
|
||||
#define AR71XX_PCI_WIN7_OFFS 0x07000000
|
||||
|
||||
#define AR71XX_PCI_CFG_BASE \
|
||||
(AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
|
||||
#define AR71XX_PCI_CFG_SIZE 0x100
|
||||
|
||||
#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
|
||||
#define AR7240_USB_CTRL_SIZE 0x100
|
||||
#define AR7240_OHCI_BASE 0x1b000000
|
||||
#define AR7240_OHCI_SIZE 0x1000
|
||||
|
||||
#define AR724X_PCI_MEM_BASE 0x10000000
|
||||
#define AR724X_PCI_MEM_SIZE 0x04000000
|
||||
|
||||
#define AR724X_PCI_CFG_BASE 0x14000000
|
||||
#define AR724X_PCI_CFG_SIZE 0x1000
|
||||
#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000)
|
||||
#define AR724X_PCI_CRP_SIZE 0x1000
|
||||
#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000)
|
||||
#define AR724X_PCI_CTRL_SIZE 0x100
|
||||
|
||||
#define AR724X_EHCI_BASE 0x1b000000
|
||||
#define AR724X_EHCI_SIZE 0x1000
|
||||
|
||||
|
@ -68,6 +94,25 @@
|
|||
#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
|
||||
#define AR934X_SRIF_SIZE 0x1000
|
||||
|
||||
#define QCA955X_PCI_MEM_BASE0 0x10000000
|
||||
#define QCA955X_PCI_MEM_BASE1 0x12000000
|
||||
#define QCA955X_PCI_MEM_SIZE 0x02000000
|
||||
#define QCA955X_PCI_CFG_BASE0 0x14000000
|
||||
#define QCA955X_PCI_CFG_BASE1 0x16000000
|
||||
#define QCA955X_PCI_CFG_SIZE 0x1000
|
||||
#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
|
||||
#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
|
||||
#define QCA955X_PCI_CRP_SIZE 0x1000
|
||||
#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
|
||||
#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
|
||||
#define QCA955X_PCI_CTRL_SIZE 0x100
|
||||
|
||||
#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
|
||||
#define QCA955X_WMAC_SIZE 0x20000
|
||||
#define QCA955X_EHCI0_BASE 0x1b000000
|
||||
#define QCA955X_EHCI1_BASE 0x1b400000
|
||||
#define QCA955X_EHCI_SIZE 0x1000
|
||||
|
||||
/*
|
||||
* DDR_CTRL block
|
||||
*/
|
||||
|
@ -199,6 +244,41 @@
|
|||
#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
|
||||
#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
|
||||
|
||||
#define QCA955X_PLL_CPU_CONFIG_REG 0x00
|
||||
#define QCA955X_PLL_DDR_CONFIG_REG 0x04
|
||||
#define QCA955X_PLL_CLK_CTRL_REG 0x08
|
||||
|
||||
#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
|
||||
#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
|
||||
#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6
|
||||
#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f
|
||||
#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
|
||||
#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
|
||||
#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
|
||||
#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
|
||||
|
||||
#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
|
||||
#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
|
||||
#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10
|
||||
#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f
|
||||
#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
|
||||
#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
|
||||
#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
|
||||
#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
|
||||
|
||||
#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
|
||||
#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
|
||||
#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
|
||||
#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
|
||||
#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
|
||||
#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
|
||||
#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
|
||||
#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
|
||||
#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
|
||||
#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
|
||||
#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
|
||||
#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
|
||||
|
||||
/*
|
||||
* USB_CONFIG block
|
||||
*/
|
||||
|
@ -238,6 +318,10 @@
|
|||
#define AR934X_RESET_REG_BOOTSTRAP 0xb0
|
||||
#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
|
||||
|
||||
#define QCA955X_RESET_REG_RESET_MODULE 0x1c
|
||||
#define QCA955X_RESET_REG_BOOTSTRAP 0xb0
|
||||
#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
|
||||
|
||||
#define MISC_INT_ETHSW BIT(12)
|
||||
#define MISC_INT_TIMER4 BIT(10)
|
||||
#define MISC_INT_TIMER3 BIT(9)
|
||||
|
@ -315,6 +399,8 @@
|
|||
#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
|
||||
#define AR934X_BOOTSTRAP_DDR1 BIT(0)
|
||||
|
||||
#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
|
||||
|
||||
#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
|
||||
#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
|
||||
#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
|
||||
|
@ -333,6 +419,37 @@
|
|||
AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
|
||||
AR934X_PCIE_WMAC_INT_PCIE_RC3)
|
||||
|
||||
#define QCA955X_EXT_INT_WMAC_MISC BIT(0)
|
||||
#define QCA955X_EXT_INT_WMAC_TX BIT(1)
|
||||
#define QCA955X_EXT_INT_WMAC_RXLP BIT(2)
|
||||
#define QCA955X_EXT_INT_WMAC_RXHP BIT(3)
|
||||
#define QCA955X_EXT_INT_PCIE_RC1 BIT(4)
|
||||
#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5)
|
||||
#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6)
|
||||
#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7)
|
||||
#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8)
|
||||
#define QCA955X_EXT_INT_PCIE_RC2 BIT(12)
|
||||
#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13)
|
||||
#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14)
|
||||
#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15)
|
||||
#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16)
|
||||
#define QCA955X_EXT_INT_USB1 BIT(24)
|
||||
#define QCA955X_EXT_INT_USB2 BIT(28)
|
||||
|
||||
#define QCA955X_EXT_INT_WMAC_ALL \
|
||||
(QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \
|
||||
QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP)
|
||||
|
||||
#define QCA955X_EXT_INT_PCIE_RC1_ALL \
|
||||
(QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \
|
||||
QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \
|
||||
QCA955X_EXT_INT_PCIE_RC1_INT3)
|
||||
|
||||
#define QCA955X_EXT_INT_PCIE_RC2_ALL \
|
||||
(QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \
|
||||
QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
|
||||
QCA955X_EXT_INT_PCIE_RC2_INT3)
|
||||
|
||||
#define REV_ID_MAJOR_MASK 0xfff0
|
||||
#define REV_ID_MAJOR_AR71XX 0x00a0
|
||||
#define REV_ID_MAJOR_AR913X 0x00b0
|
||||
|
@ -344,6 +461,8 @@
|
|||
#define REV_ID_MAJOR_AR9341 0x0120
|
||||
#define REV_ID_MAJOR_AR9342 0x1120
|
||||
#define REV_ID_MAJOR_AR9344 0x2120
|
||||
#define REV_ID_MAJOR_QCA9556 0x0130
|
||||
#define REV_ID_MAJOR_QCA9558 0x1130
|
||||
|
||||
#define AR71XX_REV_ID_MINOR_MASK 0x3
|
||||
#define AR71XX_REV_ID_MINOR_AR7130 0x0
|
||||
|
@ -364,6 +483,8 @@
|
|||
|
||||
#define AR934X_REV_ID_REVISION_MASK 0xf
|
||||
|
||||
#define QCA955X_REV_ID_REVISION_MASK 0xf
|
||||
|
||||
/*
|
||||
* SPI block
|
||||
*/
|
||||
|
@ -401,12 +522,15 @@
|
|||
#define AR71XX_GPIO_REG_INT_ENABLE 0x24
|
||||
#define AR71XX_GPIO_REG_FUNC 0x28
|
||||
|
||||
#define AR934X_GPIO_REG_FUNC 0x6c
|
||||
|
||||
#define AR71XX_GPIO_COUNT 16
|
||||
#define AR7240_GPIO_COUNT 18
|
||||
#define AR7241_GPIO_COUNT 20
|
||||
#define AR913X_GPIO_COUNT 22
|
||||
#define AR933X_GPIO_COUNT 30
|
||||
#define AR934X_GPIO_COUNT 23
|
||||
#define QCA955X_GPIO_COUNT 24
|
||||
|
||||
/*
|
||||
* SRIF block
|
||||
|
|
|
@ -32,6 +32,8 @@ enum ath79_soc_type {
|
|||
ATH79_SOC_AR9341,
|
||||
ATH79_SOC_AR9342,
|
||||
ATH79_SOC_AR9344,
|
||||
ATH79_SOC_QCA9556,
|
||||
ATH79_SOC_QCA9558,
|
||||
};
|
||||
|
||||
extern enum ath79_soc_type ath79_soc;
|
||||
|
@ -98,6 +100,21 @@ static inline int soc_is_ar934x(void)
|
|||
return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
|
||||
}
|
||||
|
||||
static inline int soc_is_qca9556(void)
|
||||
{
|
||||
return ath79_soc == ATH79_SOC_QCA9556;
|
||||
}
|
||||
|
||||
static inline int soc_is_qca9558(void)
|
||||
{
|
||||
return ath79_soc == ATH79_SOC_QCA9558;
|
||||
}
|
||||
|
||||
static inline int soc_is_qca955x(void)
|
||||
{
|
||||
return soc_is_qca9556() || soc_is_qca9558();
|
||||
}
|
||||
|
||||
extern void __iomem *ath79_ddr_base;
|
||||
extern void __iomem *ath79_pll_base;
|
||||
extern void __iomem *ath79_reset_base;
|
||||
|
|
|
@ -10,10 +10,13 @@
|
|||
#define __ASM_MACH_ATH79_IRQ_H
|
||||
|
||||
#define MIPS_CPU_IRQ_BASE 0
|
||||
#define NR_IRQS 48
|
||||
#define NR_IRQS 51
|
||||
|
||||
#define ATH79_CPU_IRQ(_x) (MIPS_CPU_IRQ_BASE + (_x))
|
||||
|
||||
#define ATH79_MISC_IRQ_BASE 8
|
||||
#define ATH79_MISC_IRQ_COUNT 32
|
||||
#define ATH79_MISC_IRQ(_x) (ATH79_MISC_IRQ_BASE + (_x))
|
||||
|
||||
#define ATH79_PCI_IRQ_BASE (ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT)
|
||||
#define ATH79_PCI_IRQ_COUNT 6
|
||||
|
@ -23,25 +26,9 @@
|
|||
#define ATH79_IP2_IRQ_COUNT 2
|
||||
#define ATH79_IP2_IRQ(_x) (ATH79_IP2_IRQ_BASE + (_x))
|
||||
|
||||
#define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2)
|
||||
#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3)
|
||||
#define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4)
|
||||
#define ATH79_CPU_IRQ_GE1 (MIPS_CPU_IRQ_BASE + 5)
|
||||
#define ATH79_CPU_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6)
|
||||
#define ATH79_CPU_IRQ_TIMER (MIPS_CPU_IRQ_BASE + 7)
|
||||
|
||||
#define ATH79_MISC_IRQ_TIMER (ATH79_MISC_IRQ_BASE + 0)
|
||||
#define ATH79_MISC_IRQ_ERROR (ATH79_MISC_IRQ_BASE + 1)
|
||||
#define ATH79_MISC_IRQ_GPIO (ATH79_MISC_IRQ_BASE + 2)
|
||||
#define ATH79_MISC_IRQ_UART (ATH79_MISC_IRQ_BASE + 3)
|
||||
#define ATH79_MISC_IRQ_WDOG (ATH79_MISC_IRQ_BASE + 4)
|
||||
#define ATH79_MISC_IRQ_PERFC (ATH79_MISC_IRQ_BASE + 5)
|
||||
#define ATH79_MISC_IRQ_OHCI (ATH79_MISC_IRQ_BASE + 6)
|
||||
#define ATH79_MISC_IRQ_DMA (ATH79_MISC_IRQ_BASE + 7)
|
||||
#define ATH79_MISC_IRQ_TIMER2 (ATH79_MISC_IRQ_BASE + 8)
|
||||
#define ATH79_MISC_IRQ_TIMER3 (ATH79_MISC_IRQ_BASE + 9)
|
||||
#define ATH79_MISC_IRQ_TIMER4 (ATH79_MISC_IRQ_BASE + 10)
|
||||
#define ATH79_MISC_IRQ_ETHSW (ATH79_MISC_IRQ_BASE + 12)
|
||||
#define ATH79_IP3_IRQ_BASE (ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT)
|
||||
#define ATH79_IP3_IRQ_COUNT 3
|
||||
#define ATH79_IP3_IRQ(_x) (ATH79_IP3_IRQ_BASE + (_x))
|
||||
|
||||
#include_next <irq.h>
|
||||
|
||||
|
|
|
@ -1,28 +0,0 @@
|
|||
/*
|
||||
* Atheros AR71XX/AR724X PCI support
|
||||
*
|
||||
* Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
|
||||
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_MACH_ATH79_PCI_H
|
||||
#define __ASM_MACH_ATH79_PCI_H
|
||||
|
||||
#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR71XX)
|
||||
int ar71xx_pcibios_init(void);
|
||||
#else
|
||||
static inline int ar71xx_pcibios_init(void) { return 0; }
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCI_AR724X)
|
||||
int ar724x_pcibios_init(int irq);
|
||||
#else
|
||||
static inline int ar724x_pcibios_init(int irq) { return 0; }
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_MACH_ATH79_PCI_H */
|
|
@ -8,8 +8,8 @@
|
|||
* option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __NVRAM_H
|
||||
#define __NVRAM_H
|
||||
#ifndef __BCM47XX_NVRAM_H
|
||||
#define __BCM47XX_NVRAM_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/kernel.h>
|
||||
|
@ -32,12 +32,9 @@ struct nvram_header {
|
|||
#define NVRAM_MAX_VALUE_LEN 255
|
||||
#define NVRAM_MAX_PARAM_LEN 64
|
||||
|
||||
#define NVRAM_ERR_INV_PARAM -8
|
||||
#define NVRAM_ERR_ENVNOTFOUND -9
|
||||
extern int bcm47xx_nvram_getenv(char *name, char *val, size_t val_len);
|
||||
|
||||
extern int nvram_getenv(char *name, char *val, size_t val_len);
|
||||
|
||||
static inline void nvram_parse_macaddr(char *buf, u8 macaddr[6])
|
||||
static inline void bcm47xx_nvram_parse_macaddr(char *buf, u8 macaddr[6])
|
||||
{
|
||||
if (strchr(buf, ':'))
|
||||
sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0],
|
||||
|
@ -51,4 +48,4 @@ static inline void nvram_parse_macaddr(char *buf, u8 macaddr[6])
|
|||
printk(KERN_WARNING "Can not parse mac address: %s\n", buf);
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif /* __BCM47XX_NVRAM_H */
|
|
@ -34,6 +34,7 @@ extern spinlock_t ebu_lock;
|
|||
extern void ltq_disable_irq(struct irq_data *data);
|
||||
extern void ltq_mask_and_ack_irq(struct irq_data *data);
|
||||
extern void ltq_enable_irq(struct irq_data *data);
|
||||
extern int ltq_eiu_get_irq(int exin);
|
||||
|
||||
/* clock handling */
|
||||
extern int clk_activate(struct clk *clk);
|
||||
|
@ -41,6 +42,7 @@ extern void clk_deactivate(struct clk *clk);
|
|||
extern struct clk *clk_get_cpu(void);
|
||||
extern struct clk *clk_get_fpi(void);
|
||||
extern struct clk *clk_get_io(void);
|
||||
extern struct clk *clk_get_ppe(void);
|
||||
|
||||
/* find out what bootsource we have */
|
||||
extern unsigned char ltq_boot_select(void);
|
||||
|
|
|
@ -1,43 +0,0 @@
|
|||
/*
|
||||
*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* Clock module specific definitions
|
||||
*
|
||||
* Author: source@mvista.com
|
||||
*
|
||||
* This program is free software; you can distribute it and/or modify it
|
||||
* under the terms of the GNU General Public License (Version 2) as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef __PNX8550_CM_H
|
||||
#define __PNX8550_CM_H
|
||||
|
||||
#define PNX8550_CM_BASE 0xBBE47000
|
||||
|
||||
#define PNX8550_CM_PLL0_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x000)
|
||||
#define PNX8550_CM_PLL1_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x004)
|
||||
#define PNX8550_CM_PLL2_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x008)
|
||||
#define PNX8550_CM_PLL3_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x00C)
|
||||
|
||||
// Table not complete.....
|
||||
|
||||
#define PNX8550_CM_PLL_BLOCKED_MASK 0x80000000
|
||||
#define PNX8550_CM_PLL_LOCK_MASK 0x40000000
|
||||
#define PNX8550_CM_PLL_CURRENT_ADJ_MASK 0x3c000000
|
||||
#define PNX8550_CM_PLL_N_MASK 0x01ff0000
|
||||
#define PNX8550_CM_PLL_M_MASK 0x00003f00
|
||||
#define PNX8550_CM_PLL_P_MASK 0x0000000c
|
||||
#define PNX8550_CM_PLL_PD_MASK 0x00000002
|
||||
|
||||
|
||||
#endif
|
|
@ -1,86 +0,0 @@
|
|||
/*
|
||||
*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* PNX8550 global definitions
|
||||
*
|
||||
* Author: source@mvista.com
|
||||
*
|
||||
* This program is free software; you can distribute it and/or modify it
|
||||
* under the terms of the GNU General Public License (Version 2) as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef __PNX8550_GLB_H
|
||||
#define __PNX8550_GLB_H
|
||||
|
||||
#define PNX8550_GLB1_BASE 0xBBE63000
|
||||
#define PNX8550_GLB2_BASE 0xBBE4d000
|
||||
#define PNX8550_RESET_BASE 0xBBE60000
|
||||
|
||||
/* PCI Inta Output Enable Registers */
|
||||
#define PNX8550_GLB2_ENAB_INTA_O *(volatile unsigned long *)(PNX8550_GLB2_BASE + 0x050)
|
||||
|
||||
/* Bit 1:Enable DAC Powerdown
|
||||
0:DACs are enabled and are working normally
|
||||
1:DACs are powerdown
|
||||
*/
|
||||
#define PNX8550_GLB_DAC_PD 0x2
|
||||
/* Bit 0:Enable of PCI inta output
|
||||
0 = Disable PCI inta output
|
||||
1 = Enable PCI inta output
|
||||
*/
|
||||
#define PNX8550_GLB_ENABLE_INTA_O 0x1
|
||||
|
||||
/* PCI Direct Mappings */
|
||||
#define PNX8550_PCIMEM 0x12000000
|
||||
#define PNX8550_PCIMEM_SIZE 0x08000000
|
||||
#define PNX8550_PCIIO 0x1c000000
|
||||
#define PNX8550_PCIIO_SIZE 0x02000000 /* 32M */
|
||||
|
||||
#define PNX8550_PORT_BASE KSEG1
|
||||
|
||||
// GPIO def
|
||||
#define PNX8550_GPIO_BASE 0x1Be00000
|
||||
|
||||
#define PNX8550_GPIO_DIRQ0 (PNX8550_GPIO_BASE + 0x104500)
|
||||
#define PNX8550_GPIO_MC1 (PNX8550_GPIO_BASE + 0x104004)
|
||||
#define PNX8550_GPIO_MC_31_BIT 30
|
||||
#define PNX8550_GPIO_MC_30_BIT 28
|
||||
#define PNX8550_GPIO_MC_29_BIT 26
|
||||
#define PNX8550_GPIO_MC_28_BIT 24
|
||||
#define PNX8550_GPIO_MC_27_BIT 22
|
||||
#define PNX8550_GPIO_MC_26_BIT 20
|
||||
#define PNX8550_GPIO_MC_25_BIT 18
|
||||
#define PNX8550_GPIO_MC_24_BIT 16
|
||||
#define PNX8550_GPIO_MC_23_BIT 14
|
||||
#define PNX8550_GPIO_MC_22_BIT 12
|
||||
#define PNX8550_GPIO_MC_21_BIT 10
|
||||
#define PNX8550_GPIO_MC_20_BIT 8
|
||||
#define PNX8550_GPIO_MC_19_BIT 6
|
||||
#define PNX8550_GPIO_MC_18_BIT 4
|
||||
#define PNX8550_GPIO_MC_17_BIT 2
|
||||
#define PNX8550_GPIO_MC_16_BIT 0
|
||||
|
||||
#define PNX8550_GPIO_MODE_PRIMOP 0x1
|
||||
#define PNX8550_GPIO_MODE_NO_OPENDR 0x2
|
||||
#define PNX8550_GPIO_MODE_OPENDR 0x3
|
||||
|
||||
// RESET module
|
||||
#define PNX8550_RST_CTL *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x0)
|
||||
#define PNX8550_RST_CAUSE *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x4)
|
||||
#define PNX8550_RST_EN_WATCHDOG *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x8)
|
||||
|
||||
#define PNX8550_RST_REL_MIPS_RST_N 0x8
|
||||
#define PNX8550_RST_DO_SW_RST 0x4
|
||||
#define PNX8550_RST_REL_SYS_RST_OUT 0x2
|
||||
#define PNX8550_RST_ASSERT_SYS_RST_OUT 0x1
|
||||
#endif
|
|
@ -1,140 +0,0 @@
|
|||
/*
|
||||
*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* Interrupt specific definitions
|
||||
*
|
||||
* Author: source@mvista.com
|
||||
*
|
||||
* This program is free software; you can distribute it and/or modify it
|
||||
* under the terms of the GNU General Public License (Version 2) as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef __PNX8550_INT_H
|
||||
#define __PNX8550_INT_H
|
||||
|
||||
#define PNX8550_GIC_BASE 0xBBE3E000
|
||||
|
||||
#define PNX8550_GIC_PRIMASK_0 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x000)
|
||||
#define PNX8550_GIC_PRIMASK_1 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x004)
|
||||
#define PNX8550_GIC_VECTOR_0 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x100)
|
||||
#define PNX8550_GIC_VECTOR_1 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x104)
|
||||
#define PNX8550_GIC_PEND_1_31 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x200)
|
||||
#define PNX8550_GIC_PEND_32_63 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x204)
|
||||
#define PNX8550_GIC_PEND_64_70 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x208)
|
||||
#define PNX8550_GIC_FEATURES *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x300)
|
||||
#define PNX8550_GIC_REQ(x) *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x400 + (x)*4)
|
||||
#define PNX8550_GIC_MOD_ID *(volatile unsigned long *)(PNX8550_GIC_BASE + 0xFFC)
|
||||
|
||||
// cp0 is two software + six hw exceptions
|
||||
#define PNX8550_INT_CP0_TOTINT 8
|
||||
#define PNX8550_INT_CP0_MIN 0
|
||||
#define PNX8550_INT_CP0_MAX (PNX8550_INT_CP0_MIN + PNX8550_INT_CP0_TOTINT - 1)
|
||||
|
||||
#define MIPS_CPU_GIC_IRQ 2
|
||||
#define MIPS_CPU_TIMER_IRQ 7
|
||||
|
||||
// GIC are 71 exceptions connected to cp0's first hardware exception
|
||||
#define PNX8550_INT_GIC_TOTINT 71
|
||||
#define PNX8550_INT_GIC_MIN (PNX8550_INT_CP0_MAX+1)
|
||||
#define PNX8550_INT_GIC_MAX (PNX8550_INT_GIC_MIN + PNX8550_INT_GIC_TOTINT - 1)
|
||||
|
||||
#define PNX8550_INT_UNDEF (PNX8550_INT_GIC_MIN+0)
|
||||
#define PNX8550_INT_IPC_TARGET0_MIPS (PNX8550_INT_GIC_MIN+1)
|
||||
#define PNX8550_INT_IPC_TARGET1_TM32_1 (PNX8550_INT_GIC_MIN+2)
|
||||
#define PNX8550_INT_IPC_TARGET1_TM32_2 (PNX8550_INT_GIC_MIN+3)
|
||||
#define PNX8550_INT_RESERVED_4 (PNX8550_INT_GIC_MIN+4)
|
||||
#define PNX8550_INT_USB (PNX8550_INT_GIC_MIN+5)
|
||||
#define PNX8550_INT_GPIO_EQ1 (PNX8550_INT_GIC_MIN+6)
|
||||
#define PNX8550_INT_GPIO_EQ2 (PNX8550_INT_GIC_MIN+7)
|
||||
#define PNX8550_INT_GPIO_EQ3 (PNX8550_INT_GIC_MIN+8)
|
||||
#define PNX8550_INT_GPIO_EQ4 (PNX8550_INT_GIC_MIN+9)
|
||||
|
||||
#define PNX8550_INT_GPIO_EQ5 (PNX8550_INT_GIC_MIN+10)
|
||||
#define PNX8550_INT_GPIO_EQ6 (PNX8550_INT_GIC_MIN+11)
|
||||
#define PNX8550_INT_RESERVED_12 (PNX8550_INT_GIC_MIN+12)
|
||||
#define PNX8550_INT_QVCP1 (PNX8550_INT_GIC_MIN+13)
|
||||
#define PNX8550_INT_QVCP2 (PNX8550_INT_GIC_MIN+14)
|
||||
#define PNX8550_INT_I2C1 (PNX8550_INT_GIC_MIN+15)
|
||||
#define PNX8550_INT_I2C2 (PNX8550_INT_GIC_MIN+16)
|
||||
#define PNX8550_INT_ISO_UART1 (PNX8550_INT_GIC_MIN+17)
|
||||
#define PNX8550_INT_ISO_UART2 (PNX8550_INT_GIC_MIN+18)
|
||||
#define PNX8550_INT_UART1 (PNX8550_INT_GIC_MIN+19)
|
||||
|
||||
#define PNX8550_INT_UART2 (PNX8550_INT_GIC_MIN+20)
|
||||
#define PNX8550_INT_QNTR (PNX8550_INT_GIC_MIN+21)
|
||||
#define PNX8550_INT_RESERVED22 (PNX8550_INT_GIC_MIN+22)
|
||||
#define PNX8550_INT_T_DSC (PNX8550_INT_GIC_MIN+23)
|
||||
#define PNX8550_INT_M_DSC (PNX8550_INT_GIC_MIN+24)
|
||||
#define PNX8550_INT_RESERVED25 (PNX8550_INT_GIC_MIN+25)
|
||||
#define PNX8550_INT_2D_DRAW_ENG (PNX8550_INT_GIC_MIN+26)
|
||||
#define PNX8550_INT_MEM_BASED_SCALAR1 (PNX8550_INT_GIC_MIN+27)
|
||||
#define PNX8550_INT_VIDEO_MPEG (PNX8550_INT_GIC_MIN+28)
|
||||
#define PNX8550_INT_VIDEO_INPUT_P1 (PNX8550_INT_GIC_MIN+29)
|
||||
|
||||
#define PNX8550_INT_VIDEO_INPUT_P2 (PNX8550_INT_GIC_MIN+30)
|
||||
#define PNX8550_INT_SPDI1 (PNX8550_INT_GIC_MIN+31)
|
||||
#define PNX8550_INT_SPDO (PNX8550_INT_GIC_MIN+32)
|
||||
#define PNX8550_INT_AUDIO_INPUT1 (PNX8550_INT_GIC_MIN+33)
|
||||
#define PNX8550_INT_AUDIO_OUTPUT1 (PNX8550_INT_GIC_MIN+34)
|
||||
#define PNX8550_INT_AUDIO_INPUT2 (PNX8550_INT_GIC_MIN+35)
|
||||
#define PNX8550_INT_AUDIO_OUTPUT2 (PNX8550_INT_GIC_MIN+36)
|
||||
#define PNX8550_INT_MEMBASED_SCALAR2 (PNX8550_INT_GIC_MIN+37)
|
||||
#define PNX8550_INT_VPK (PNX8550_INT_GIC_MIN+38)
|
||||
#define PNX8550_INT_MPEG1_MIPS (PNX8550_INT_GIC_MIN+39)
|
||||
|
||||
#define PNX8550_INT_MPEG1_TM (PNX8550_INT_GIC_MIN+40)
|
||||
#define PNX8550_INT_MPEG2_MIPS (PNX8550_INT_GIC_MIN+41)
|
||||
#define PNX8550_INT_MPEG2_TM (PNX8550_INT_GIC_MIN+42)
|
||||
#define PNX8550_INT_TS_DMA (PNX8550_INT_GIC_MIN+43)
|
||||
#define PNX8550_INT_EDMA (PNX8550_INT_GIC_MIN+44)
|
||||
#define PNX8550_INT_TM_DEBUG1 (PNX8550_INT_GIC_MIN+45)
|
||||
#define PNX8550_INT_TM_DEBUG2 (PNX8550_INT_GIC_MIN+46)
|
||||
#define PNX8550_INT_PCI_INTA (PNX8550_INT_GIC_MIN+47)
|
||||
#define PNX8550_INT_CLOCK_MODULE (PNX8550_INT_GIC_MIN+48)
|
||||
#define PNX8550_INT_PCI_XIO_INTA_PCI (PNX8550_INT_GIC_MIN+49)
|
||||
|
||||
#define PNX8550_INT_PCI_XIO_INTB_DMA (PNX8550_INT_GIC_MIN+50)
|
||||
#define PNX8550_INT_PCI_XIO_INTC_GPPM (PNX8550_INT_GIC_MIN+51)
|
||||
#define PNX8550_INT_PCI_XIO_INTD_GPXIO (PNX8550_INT_GIC_MIN+52)
|
||||
#define PNX8550_INT_DVD_CSS (PNX8550_INT_GIC_MIN+53)
|
||||
#define PNX8550_INT_VLD (PNX8550_INT_GIC_MIN+54)
|
||||
#define PNX8550_INT_GPIO_TSU_7_0 (PNX8550_INT_GIC_MIN+55)
|
||||
#define PNX8550_INT_GPIO_TSU_15_8 (PNX8550_INT_GIC_MIN+56)
|
||||
#define PNX8550_INT_GPIO_CTU_IR (PNX8550_INT_GIC_MIN+57)
|
||||
#define PNX8550_INT_GPIO0 (PNX8550_INT_GIC_MIN+58)
|
||||
#define PNX8550_INT_GPIO1 (PNX8550_INT_GIC_MIN+59)
|
||||
|
||||
#define PNX8550_INT_GPIO2 (PNX8550_INT_GIC_MIN+60)
|
||||
#define PNX8550_INT_GPIO3 (PNX8550_INT_GIC_MIN+61)
|
||||
#define PNX8550_INT_GPIO4 (PNX8550_INT_GIC_MIN+62)
|
||||
#define PNX8550_INT_GPIO5 (PNX8550_INT_GIC_MIN+63)
|
||||
#define PNX8550_INT_GPIO6 (PNX8550_INT_GIC_MIN+64)
|
||||
#define PNX8550_INT_GPIO7 (PNX8550_INT_GIC_MIN+65)
|
||||
#define PNX8550_INT_PMAN_SECURITY (PNX8550_INT_GIC_MIN+66)
|
||||
#define PNX8550_INT_I2C3 (PNX8550_INT_GIC_MIN+67)
|
||||
#define PNX8550_INT_RESERVED_68 (PNX8550_INT_GIC_MIN+68)
|
||||
#define PNX8550_INT_SPDI2 (PNX8550_INT_GIC_MIN+69)
|
||||
|
||||
#define PNX8550_INT_I2C4 (PNX8550_INT_GIC_MIN+70)
|
||||
|
||||
// Timer are 3 exceptions connected to cp0's 7th hardware exception
|
||||
#define PNX8550_INT_TIMER_TOTINT 3
|
||||
#define PNX8550_INT_TIMER_MIN (PNX8550_INT_GIC_MAX+1)
|
||||
#define PNX8550_INT_TIMER_MAX (PNX8550_INT_TIMER_MIN + PNX8550_INT_TIMER_TOTINT - 1)
|
||||
|
||||
#define PNX8550_INT_TIMER1 (PNX8550_INT_TIMER_MIN+0)
|
||||
#define PNX8550_INT_TIMER2 (PNX8550_INT_TIMER_MIN+1)
|
||||
#define PNX8550_INT_TIMER3 (PNX8550_INT_TIMER_MIN+2)
|
||||
#define PNX8550_INT_WATCHDOG PNX8550_INT_TIMER3
|
||||
|
||||
#endif
|
|
@ -1,262 +0,0 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2005 Embedded Alley Solutions, Inc
|
||||
*/
|
||||
#ifndef __ASM_MACH_KERNEL_ENTRY_INIT_H
|
||||
#define __ASM_MACH_KERNEL_ENTRY_INIT_H
|
||||
|
||||
#include <asm/cacheops.h>
|
||||
#include <asm/addrspace.h>
|
||||
|
||||
#define CO_CONFIGPR_VALID 0x3F1F41FF /* valid bits to write to ConfigPR */
|
||||
#define HAZARD_CP0 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;
|
||||
#define CACHE_OPC 0xBC000000 /* MIPS cache instruction opcode */
|
||||
#define ICACHE_LINE_SIZE 32 /* Instruction cache line size bytes */
|
||||
#define DCACHE_LINE_SIZE 32 /* Data cache line size in bytes */
|
||||
|
||||
#define ICACHE_SET_COUNT 256 /* Instruction cache set count */
|
||||
#define DCACHE_SET_COUNT 128 /* Data cache set count */
|
||||
|
||||
#define ICACHE_SET_SIZE (ICACHE_SET_COUNT * ICACHE_LINE_SIZE)
|
||||
#define DCACHE_SET_SIZE (DCACHE_SET_COUNT * DCACHE_LINE_SIZE)
|
||||
|
||||
.macro kernel_entry_setup
|
||||
.set push
|
||||
.set noreorder
|
||||
/*
|
||||
* PNX8550 entry point, when running a non compressed
|
||||
* kernel. When loading a zImage, the head.S code in
|
||||
* arch/mips/zboot/pnx8550 will init the caches and,
|
||||
* decompress the kernel, and branch to kernel_entry.
|
||||
*/
|
||||
cache_begin: li t0, (1<<28)
|
||||
mtc0 t0, CP0_STATUS /* cp0 usable */
|
||||
HAZARD_CP0
|
||||
|
||||
mtc0 zero, CP0_CAUSE
|
||||
HAZARD_CP0
|
||||
|
||||
|
||||
/* Set static virtual to phys address translation and TLB disabled */
|
||||
mfc0 t0, CP0_CONFIG, 7
|
||||
HAZARD_CP0
|
||||
|
||||
and t0, ~((1<<19) | (1<<20)) /* TLB/MAP cleared */
|
||||
mtc0 t0, CP0_CONFIG, 7
|
||||
HAZARD_CP0
|
||||
|
||||
/* CPU boots with kseg0 cache algo set to 0x2 -- uncached */
|
||||
|
||||
init_icache
|
||||
nop
|
||||
init_dcache
|
||||
nop
|
||||
|
||||
cachePr4450ICReset
|
||||
nop
|
||||
|
||||
cachePr4450DCReset
|
||||
nop
|
||||
|
||||
/* read ConfigPR into t0 */
|
||||
mfc0 t0, CP0_CONFIG, 7
|
||||
HAZARD_CP0
|
||||
|
||||
/* enable the TLB */
|
||||
or t0, (1<<19)
|
||||
|
||||
/* disable the ICACHE: at least 10x slower */
|
||||
/* or t0, (1<<26) */
|
||||
|
||||
/* disable the DCACHE; CONFIG_CPU_HAS_LLSC should not be set */
|
||||
/* or t0, (1<<27) */
|
||||
|
||||
and t0, CO_CONFIGPR_VALID
|
||||
|
||||
/* enable TLB. */
|
||||
mtc0 t0, CP0_CONFIG, 7
|
||||
HAZARD_CP0
|
||||
cache_end:
|
||||
/* Setup CMEM_0 to MMIO address space, 2MB */
|
||||
lui t0, 0x1BE0
|
||||
addi t0, t0, 0x3
|
||||
mtc0 $8, $22, 4
|
||||
nop
|
||||
|
||||
/* Setup CMEM_1, 128MB */
|
||||
lui t0, 0x1000
|
||||
addi t0, t0, 0xf
|
||||
mtc0 $8, $22, 5
|
||||
nop
|
||||
|
||||
|
||||
/* Setup CMEM_2, 32MB */
|
||||
lui t0, 0x1C00
|
||||
addi t0, t0, 0xb
|
||||
mtc0 $8, $22, 6
|
||||
nop
|
||||
|
||||
/* Setup CMEM_3, 0MB */
|
||||
lui t0, 0x0
|
||||
addi t0, t0, 0x0
|
||||
mtc0 $8, $22, 7
|
||||
nop
|
||||
|
||||
/* Enable cache */
|
||||
mfc0 t0, CP0_CONFIG
|
||||
HAZARD_CP0
|
||||
and t0, t0, 0xFFFFFFF8
|
||||
or t0, t0, 3
|
||||
mtc0 t0, CP0_CONFIG
|
||||
HAZARD_CP0
|
||||
.set pop
|
||||
.endm
|
||||
|
||||
.macro init_icache
|
||||
.set push
|
||||
.set noreorder
|
||||
|
||||
/* Get Cache Configuration */
|
||||
mfc0 t3, CP0_CONFIG, 1
|
||||
HAZARD_CP0
|
||||
|
||||
/* get cache Line size */
|
||||
|
||||
srl t1, t3, 19 /* C0_CONFIGPR_IL_SHIFT */
|
||||
andi t1, t1, 0x7 /* C0_CONFIGPR_IL_MASK */
|
||||
beq t1, zero, pr4450_instr_cache_invalidated /* if zero instruction cache is absent */
|
||||
nop
|
||||
addiu t0, t1, 1
|
||||
ori t1, zero, 1
|
||||
sllv t1, t1, t0
|
||||
|
||||
/* get max cache Index */
|
||||
srl t2, t3, 22 /* C0_CONFIGPR_IS_SHIFT */
|
||||
andi t2, t2, 0x7 /* C0_CONFIGPR_IS_MASK */
|
||||
addiu t0, t2, 6
|
||||
ori t2, zero, 1
|
||||
sllv t2, t2, t0
|
||||
|
||||
/* get max cache way */
|
||||
srl t3, t3, 16 /* C0_CONFIGPR_IA_SHIFT */
|
||||
andi t3, t3, 0x7 /* C0_CONFIGPR_IA_MASK */
|
||||
addiu t3, t3, 1
|
||||
|
||||
/* total no of cache lines */
|
||||
multu t2, t3 /* max index * max way */
|
||||
mflo t2
|
||||
addiu t2, t2, -1
|
||||
|
||||
move t0, zero
|
||||
pr4450_next_instruction_cache_set:
|
||||
cache Index_Invalidate_I, 0(t0)
|
||||
addu t0, t0, t1 /* add bytes in a line */
|
||||
bne t2, zero, pr4450_next_instruction_cache_set
|
||||
addiu t2, t2, -1 /* reduce no of lines to invalidate by one */
|
||||
pr4450_instr_cache_invalidated:
|
||||
.set pop
|
||||
.endm
|
||||
|
||||
.macro init_dcache
|
||||
.set push
|
||||
.set noreorder
|
||||
move t1, zero
|
||||
|
||||
/* Store Tag Information */
|
||||
mtc0 zero, CP0_TAGLO, 0
|
||||
HAZARD_CP0
|
||||
|
||||
mtc0 zero, CP0_TAGHI, 0
|
||||
HAZARD_CP0
|
||||
|
||||
/* Cache size is 16384 = 512 lines x 32 bytes per line */
|
||||
or t2, zero, (128*4)-1 /* 512 lines */
|
||||
/* Invalidate all lines */
|
||||
2:
|
||||
cache Index_Store_Tag_D, 0(t1)
|
||||
addiu t2, t2, -1
|
||||
bne t2, zero, 2b
|
||||
addiu t1, t1, 32 /* 32 bytes in a line */
|
||||
.set pop
|
||||
.endm
|
||||
|
||||
.macro cachePr4450ICReset
|
||||
.set push
|
||||
.set noreorder
|
||||
|
||||
/* Save CP0 status reg on entry; */
|
||||
/* disable interrupts during cache reset */
|
||||
mfc0 t0, CP0_STATUS /* T0 = interrupt status on entry */
|
||||
HAZARD_CP0
|
||||
|
||||
mtc0 zero, CP0_STATUS /* disable CPU interrupts */
|
||||
HAZARD_CP0
|
||||
|
||||
or t1, zero, zero /* T1 = starting cache index (0) */
|
||||
ori t2, zero, (256 - 1) /* T2 = inst cache set cnt - 1 */
|
||||
|
||||
icache_invd_loop:
|
||||
/* 9 == register t1 */
|
||||
.word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
|
||||
(0 * ICACHE_SET_SIZE) /* invalidate inst cache WAY0 */
|
||||
.word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
|
||||
(1 * ICACHE_SET_SIZE) /* invalidate inst cache WAY1 */
|
||||
|
||||
addiu t1, t1, ICACHE_LINE_SIZE /* T1 = next cache line index */
|
||||
bne t2, zero, icache_invd_loop /* T2 = 0 if all sets invalidated */
|
||||
addiu t2, t2, -1 /* decrement T2 set cnt (delay slot) */
|
||||
|
||||
/* Initialize the latches in the instruction cache tag */
|
||||
/* that drive the way selection tri-state bus drivers, by doing a */
|
||||
/* dummy load while the instruction cache is still disabled. */
|
||||
/* TODO: Is this needed ? */
|
||||
la t1, KSEG0 /* T1 = cached memory base address */
|
||||
lw zero, 0x0000(t1) /* (dummy read of first memory word) */
|
||||
|
||||
mtc0 t0, CP0_STATUS /* restore interrupt status on entry */
|
||||
HAZARD_CP0
|
||||
.set pop
|
||||
.endm
|
||||
|
||||
.macro cachePr4450DCReset
|
||||
.set push
|
||||
.set noreorder
|
||||
mfc0 t0, CP0_STATUS /* T0 = interrupt status on entry */
|
||||
HAZARD_CP0
|
||||
mtc0 zero, CP0_STATUS /* disable CPU interrupts */
|
||||
HAZARD_CP0
|
||||
|
||||
/* Writeback/invalidate entire data cache sets/ways/lines */
|
||||
or t1, zero, zero /* T1 = starting cache index (0) */
|
||||
ori t2, zero, (DCACHE_SET_COUNT - 1) /* T2 = data cache set cnt - 1 */
|
||||
|
||||
dcache_wbinvd_loop:
|
||||
/* 9 == register t1 */
|
||||
.word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
|
||||
(0 * DCACHE_SET_SIZE) /* writeback/invalidate WAY0 */
|
||||
.word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
|
||||
(1 * DCACHE_SET_SIZE) /* writeback/invalidate WAY1 */
|
||||
.word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
|
||||
(2 * DCACHE_SET_SIZE) /* writeback/invalidate WAY2 */
|
||||
.word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
|
||||
(3 * DCACHE_SET_SIZE) /* writeback/invalidate WAY3 */
|
||||
|
||||
addiu t1, t1, DCACHE_LINE_SIZE /* T1 = next data cache line index */
|
||||
bne t2, zero, dcache_wbinvd_loop /* T2 = 0 when wbinvd entire cache */
|
||||
addiu t2, t2, -1 /* decrement T2 set cnt (delay slot) */
|
||||
|
||||
/* Initialize the latches in the data cache tag that drive the way
|
||||
selection tri-state bus drivers, by doing a dummy load while the
|
||||
data cache is still in the disabled mode. TODO: Is this needed ? */
|
||||
la t1, KSEG0 /* T1 = cached memory base address */
|
||||
lw zero, 0x0000(t1) /* (dummy read of first memory word) */
|
||||
|
||||
mtc0 t0, CP0_STATUS /* restore interrupt status on entry */
|
||||
HAZARD_CP0
|
||||
.set pop
|
||||
.endm
|
||||
|
||||
#endif /* __ASM_MACH_KERNEL_ENTRY_INIT_H */
|
|
@ -1,121 +0,0 @@
|
|||
#ifndef __PNX8550_NAND_H
|
||||
#define __PNX8550_NAND_H
|
||||
|
||||
#define PNX8550_NAND_BASE_ADDR 0x10000000
|
||||
#define PNX8550_PCIXIO_BASE 0xBBE40000
|
||||
|
||||
#define PNX8550_DMA_EXT_ADDR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x800)
|
||||
#define PNX8550_DMA_INT_ADDR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x804)
|
||||
#define PNX8550_DMA_TRANS_SIZE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x808)
|
||||
#define PNX8550_DMA_CTRL *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x80c)
|
||||
#define PNX8550_XIO_SEL0 *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x814)
|
||||
#define PNX8550_GPXIO_ADDR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x820)
|
||||
#define PNX8550_GPXIO_WR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x824)
|
||||
#define PNX8550_GPXIO_RD *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x828)
|
||||
#define PNX8550_GPXIO_CTRL *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x82C)
|
||||
#define PNX8550_XIO_FLASH_CTRL *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x830)
|
||||
#define PNX8550_GPXIO_INT_STATUS *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb0)
|
||||
#define PNX8550_GPXIO_INT_ENABLE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb4)
|
||||
#define PNX8550_GPXIO_INT_CLEAR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb8)
|
||||
#define PNX8550_DMA_INT_STATUS *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd0)
|
||||
#define PNX8550_DMA_INT_ENABLE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd4)
|
||||
#define PNX8550_DMA_INT_CLEAR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd8)
|
||||
|
||||
#define PNX8550_XIO_SEL0_EN_16BIT 0x00800000
|
||||
#define PNX8550_XIO_SEL0_USE_ACK 0x00400000
|
||||
#define PNX8550_XIO_SEL0_REN_HIGH 0x00100000
|
||||
#define PNX8550_XIO_SEL0_REN_LOW 0x00040000
|
||||
#define PNX8550_XIO_SEL0_WEN_HIGH 0x00010000
|
||||
#define PNX8550_XIO_SEL0_WEN_LOW 0x00004000
|
||||
#define PNX8550_XIO_SEL0_WAIT 0x00000200
|
||||
#define PNX8550_XIO_SEL0_OFFSET 0x00000020
|
||||
#define PNX8550_XIO_SEL0_TYPE_68360 0x00000000
|
||||
#define PNX8550_XIO_SEL0_TYPE_NOR 0x00000008
|
||||
#define PNX8550_XIO_SEL0_TYPE_NAND 0x00000010
|
||||
#define PNX8550_XIO_SEL0_TYPE_IDE 0x00000018
|
||||
#define PNX8550_XIO_SEL0_SIZE_8MB 0x00000000
|
||||
#define PNX8550_XIO_SEL0_SIZE_16MB 0x00000002
|
||||
#define PNX8550_XIO_SEL0_SIZE_32MB 0x00000004
|
||||
#define PNX8550_XIO_SEL0_SIZE_64MB 0x00000006
|
||||
#define PNX8550_XIO_SEL0_ENAB 0x00000001
|
||||
|
||||
#define PNX8550_SEL0_DEFAULT ((PNX8550_XIO_SEL0_EN_16BIT) | \
|
||||
(PNX8550_XIO_SEL0_REN_HIGH*0)| \
|
||||
(PNX8550_XIO_SEL0_REN_LOW*2) | \
|
||||
(PNX8550_XIO_SEL0_WEN_HIGH*0)| \
|
||||
(PNX8550_XIO_SEL0_WEN_LOW*2) | \
|
||||
(PNX8550_XIO_SEL0_WAIT*4) | \
|
||||
(PNX8550_XIO_SEL0_OFFSET*0) | \
|
||||
(PNX8550_XIO_SEL0_TYPE_NAND) | \
|
||||
(PNX8550_XIO_SEL0_SIZE_32MB) | \
|
||||
(PNX8550_XIO_SEL0_ENAB))
|
||||
|
||||
#define PNX8550_GPXIO_PENDING 0x00000200
|
||||
#define PNX8550_GPXIO_DONE 0x00000100
|
||||
#define PNX8550_GPXIO_CLR_DONE 0x00000080
|
||||
#define PNX8550_GPXIO_INIT 0x00000040
|
||||
#define PNX8550_GPXIO_READ_CMD 0x00000010
|
||||
#define PNX8550_GPXIO_BEN 0x0000000F
|
||||
|
||||
#define PNX8550_XIO_FLASH_64MB 0x00200000
|
||||
#define PNX8550_XIO_FLASH_INC_DATA 0x00100000
|
||||
#define PNX8550_XIO_FLASH_CMD_PH 0x000C0000
|
||||
#define PNX8550_XIO_FLASH_CMD_PH2 0x00080000
|
||||
#define PNX8550_XIO_FLASH_CMD_PH1 0x00040000
|
||||
#define PNX8550_XIO_FLASH_CMD_PH0 0x00000000
|
||||
#define PNX8550_XIO_FLASH_ADR_PH 0x00030000
|
||||
#define PNX8550_XIO_FLASH_ADR_PH3 0x00030000
|
||||
#define PNX8550_XIO_FLASH_ADR_PH2 0x00020000
|
||||
#define PNX8550_XIO_FLASH_ADR_PH1 0x00010000
|
||||
#define PNX8550_XIO_FLASH_ADR_PH0 0x00000000
|
||||
#define PNX8550_XIO_FLASH_CMD_B(x) ((x<<8) & 0x0000FF00)
|
||||
#define PNX8550_XIO_FLASH_CMD_A(x) (x & 0x000000FF)
|
||||
|
||||
#define PNX8550_XIO_INT_ACK 0x00004000
|
||||
#define PNX8550_XIO_INT_COMPL 0x00002000
|
||||
#define PNX8550_XIO_INT_NONSUP 0x00000200
|
||||
#define PNX8550_XIO_INT_ABORT 0x00000004
|
||||
|
||||
#define PNX8550_DMA_CTRL_SINGLE_DATA 0x00000400
|
||||
#define PNX8550_DMA_CTRL_SND2XIO 0x00000200
|
||||
#define PNX8550_DMA_CTRL_FIX_ADDR 0x00000100
|
||||
#define PNX8550_DMA_CTRL_BURST_8 0x00000000
|
||||
#define PNX8550_DMA_CTRL_BURST_16 0x00000020
|
||||
#define PNX8550_DMA_CTRL_BURST_32 0x00000040
|
||||
#define PNX8550_DMA_CTRL_BURST_64 0x00000060
|
||||
#define PNX8550_DMA_CTRL_BURST_128 0x00000080
|
||||
#define PNX8550_DMA_CTRL_BURST_256 0x000000A0
|
||||
#define PNX8550_DMA_CTRL_BURST_512 0x000000C0
|
||||
#define PNX8550_DMA_CTRL_BURST_NORES 0x000000E0
|
||||
#define PNX8550_DMA_CTRL_INIT_DMA 0x00000010
|
||||
#define PNX8550_DMA_CTRL_CMD_TYPE 0x0000000F
|
||||
|
||||
/* see PCI system arch, page 100 for the full list: */
|
||||
#define PNX8550_DMA_CTRL_PCI_CMD_READ 0x00000006
|
||||
#define PNX8550_DMA_CTRL_PCI_CMD_WRITE 0x00000007
|
||||
|
||||
#define PNX8550_DMA_INT_STAT_ACK_DONE (1<<14)
|
||||
#define PNX8550_DMA_INT_STAT_DMA_DONE (1<<12)
|
||||
#define PNX8550_DMA_INT_STAT_DMA_ERR (1<<9)
|
||||
#define PNX8550_DMA_INT_STAT_PERR5 (1<<5)
|
||||
#define PNX8550_DMA_INT_STAT_PERR4 (1<<4)
|
||||
#define PNX8550_DMA_INT_STAT_M_ABORT (1<<2)
|
||||
#define PNX8550_DMA_INT_STAT_T_ABORT (1<<1)
|
||||
|
||||
#define PNX8550_DMA_INT_EN_ACK_DONE (1<<14)
|
||||
#define PNX8550_DMA_INT_EN_DMA_DONE (1<<12)
|
||||
#define PNX8550_DMA_INT_EN_DMA_ERR (1<<9)
|
||||
#define PNX8550_DMA_INT_EN_PERR5 (1<<5)
|
||||
#define PNX8550_DMA_INT_EN_PERR4 (1<<4)
|
||||
#define PNX8550_DMA_INT_EN_M_ABORT (1<<2)
|
||||
#define PNX8550_DMA_INT_EN_T_ABORT (1<<1)
|
||||
|
||||
#define PNX8550_DMA_INT_CLR_ACK_DONE (1<<14)
|
||||
#define PNX8550_DMA_INT_CLR_DMA_DONE (1<<12)
|
||||
#define PNX8550_DMA_INT_CLR_DMA_ERR (1<<9)
|
||||
#define PNX8550_DMA_INT_CLR_PERR5 (1<<5)
|
||||
#define PNX8550_DMA_INT_CLR_PERR4 (1<<4)
|
||||
#define PNX8550_DMA_INT_CLR_M_ABORT (1<<2)
|
||||
#define PNX8550_DMA_INT_CLR_T_ABORT (1<<1)
|
||||
|
||||
#endif
|
|
@ -1,185 +0,0 @@
|
|||
/*
|
||||
*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* PCI specific definitions
|
||||
*
|
||||
* Author: source@mvista.com
|
||||
*
|
||||
* This program is free software; you can distribute it and/or modify it
|
||||
* under the terms of the GNU General Public License (Version 2) as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef __PNX8550_PCI_H
|
||||
#define __PNX8550_PCI_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
#define PCI_ACCESS_READ 0
|
||||
#define PCI_ACCESS_WRITE 1
|
||||
|
||||
#define PCI_CMD_IOR 0x20
|
||||
#define PCI_CMD_IOW 0x30
|
||||
#define PCI_CMD_CONFIG_READ 0xa0
|
||||
#define PCI_CMD_CONFIG_WRITE 0xb0
|
||||
|
||||
#define PCI_IO_TIMEOUT 1000
|
||||
#define PCI_IO_RETRY 5
|
||||
/* Timeout for IO and CFG accesses.
|
||||
This is in 1/1024 th of a jiffie(=10ms)
|
||||
i.e. approx 10us */
|
||||
#define PCI_IO_JIFFIES_TIMEOUT 40
|
||||
#define PCI_IO_JIFFIES_SHIFT 10
|
||||
|
||||
#define PCI_BYTE_ENABLE_MASK 0x0000000f
|
||||
#define PCI_CFG_BUS_SHIFT 16
|
||||
#define PCI_CFG_FUNC_SHIFT 8
|
||||
#define PCI_CFG_REG_SHIFT 2
|
||||
|
||||
#define PCI_BASE 0x1be00000
|
||||
#define PCI_SETUP 0x00040010
|
||||
#define PCI_DIS_REQGNT (1<<30)
|
||||
#define PCI_DIS_REQGNTA (1<<29)
|
||||
#define PCI_DIS_REQGNTB (1<<28)
|
||||
#define PCI_D2_SUPPORT (1<<27)
|
||||
#define PCI_D1_SUPPORT (1<<26)
|
||||
#define PCI_EN_TA (1<<24)
|
||||
#define PCI_EN_PCI2MMI (1<<23)
|
||||
#define PCI_EN_XIO (1<<22)
|
||||
#define PCI_BASE18_PREF (1<<21)
|
||||
#define SIZE_16M 0x3
|
||||
#define SIZE_32M 0x4
|
||||
#define SIZE_64M 0x5
|
||||
#define SIZE_128M 0x6
|
||||
#define PCI_SETUP_BASE18_SIZE(X) (X<<18)
|
||||
#define PCI_SETUP_BASE18_EN (1<<17)
|
||||
#define PCI_SETUP_BASE14_PREF (1<<16)
|
||||
#define PCI_SETUP_BASE14_SIZE(X) (X<<12)
|
||||
#define PCI_SETUP_BASE14_EN (1<<11)
|
||||
#define PCI_SETUP_BASE10_PREF (1<<10)
|
||||
#define PCI_SETUP_BASE10_SIZE(X) (X<<7)
|
||||
#define PCI_SETUP_CFGMANAGE_EN (1<<1)
|
||||
#define PCI_SETUP_PCIARB_EN (1<<0)
|
||||
|
||||
#define PCI_CTRL 0x040014
|
||||
#define PCI_SWPB_DCS_PCI (1<<16)
|
||||
#define PCI_SWPB_PCI_PCI (1<<15)
|
||||
#define PCI_SWPB_PCI_DCS (1<<14)
|
||||
#define PCI_REG_WR_POST (1<<13)
|
||||
#define PCI_XIO_WR_POST (1<<12)
|
||||
#define PCI_PCI2_WR_POST (1<<13)
|
||||
#define PCI_PCI1_WR_POST (1<<12)
|
||||
#define PCI_SERR_SEEN (1<<11)
|
||||
#define PCI_B10_SPEC_RD (1<<6)
|
||||
#define PCI_B14_SPEC_RD (1<<5)
|
||||
#define PCI_B18_SPEC_RD (1<<4)
|
||||
#define PCI_B10_NOSUBWORD (1<<3)
|
||||
#define PCI_B14_NOSUBWORD (1<<2)
|
||||
#define PCI_B18_NOSUBWORD (1<<1)
|
||||
#define PCI_RETRY_TMREN (1<<0)
|
||||
|
||||
#define PCI_BASE1_LO 0x040018
|
||||
#define PCI_BASE1_HI 0x04001C
|
||||
#define PCI_BASE2_LO 0x040020
|
||||
#define PCI_BASE2_HI 0x040024
|
||||
#define PCI_RDLIFETIM 0x040028
|
||||
#define PCI_GPPM_ADDR 0x04002C
|
||||
#define PCI_GPPM_WDAT 0x040030
|
||||
#define PCI_GPPM_RDAT 0x040034
|
||||
#define PCI_GPPM_CTRL 0x040038
|
||||
#define GPPM_DONE (1<<10)
|
||||
#define INIT_PCI_CYCLE (1<<9)
|
||||
#define GPPM_CMD(X) (((X)&0xf)<<4)
|
||||
#define GPPM_BYTEEN(X) ((X)&0xf)
|
||||
#define PCI_UNLOCKREG 0x04003C
|
||||
#define UNLOCK_SSID(X) (((X)&0xff)<<8)
|
||||
#define UNLOCK_SETUP(X) (((X)&0xff)<<0)
|
||||
#define UNLOCK_MAGIC 0xCA
|
||||
#define PCI_DEV_VEND_ID 0x040040
|
||||
#define DEVICE_ID(X) (((X)>>16)&0xffff)
|
||||
#define VENDOR_ID(X) (((X)&0xffff))
|
||||
#define PCI_CFG_CMDSTAT 0x040044
|
||||
#define PCI_CFG_STATUS(X) (((X)>>16)&0xffff)
|
||||
#define PCI_CFG_COMMAND(X) ((X)&0xffff)
|
||||
#define PCI_CLASS_REV 0x040048
|
||||
#define PCI_CLASSCODE(X) (((X)>>8)&0xffffff)
|
||||
#define PCI_REVID(X) ((X)&0xff)
|
||||
#define PCI_LAT_TMR 0x04004c
|
||||
#define PCI_BASE10 0x040050
|
||||
#define PCI_BASE14 0x040054
|
||||
#define PCI_BASE18 0x040058
|
||||
#define PCI_SUBSYS_ID 0x04006c
|
||||
#define PCI_CAP_PTR 0x040074
|
||||
#define PCI_CFG_MISC 0x04007c
|
||||
#define PCI_PMC 0x040080
|
||||
#define PCI_PWR_STATE 0x040084
|
||||
#define PCI_IO 0x040088
|
||||
#define PCI_SLVTUNING 0x04008C
|
||||
#define PCI_DMATUNING 0x040090
|
||||
#define PCI_DMAEADDR 0x040800
|
||||
#define PCI_DMAIADDR 0x040804
|
||||
#define PCI_DMALEN 0x040808
|
||||
#define PCI_DMACTRL 0x04080C
|
||||
#define PCI_XIOCTRL 0x040810
|
||||
#define PCI_SEL0PROF 0x040814
|
||||
#define PCI_SEL1PROF 0x040818
|
||||
#define PCI_SEL2PROF 0x04081C
|
||||
#define PCI_GPXIOADDR 0x040820
|
||||
#define PCI_NANDCTRLS 0x400830
|
||||
#define PCI_SEL3PROF 0x040834
|
||||
#define PCI_SEL4PROF 0x040838
|
||||
#define PCI_GPXIO_STAT 0x040FB0
|
||||
#define PCI_GPXIO_IMASK 0x040FB4
|
||||
#define PCI_GPXIO_ICLR 0x040FB8
|
||||
#define PCI_GPXIO_ISET 0x040FBC
|
||||
#define PCI_GPPM_STATUS 0x040FC0
|
||||
#define GPPM_DONE (1<<10)
|
||||
#define GPPM_ERR (1<<9)
|
||||
#define GPPM_MPAR_ERR (1<<8)
|
||||
#define GPPM_PAR_ERR (1<<7)
|
||||
#define GPPM_R_MABORT (1<<2)
|
||||
#define GPPM_R_TABORT (1<<1)
|
||||
#define PCI_GPPM_IMASK 0x040FC4
|
||||
#define PCI_GPPM_ICLR 0x040FC8
|
||||
#define PCI_GPPM_ISET 0x040FCC
|
||||
#define PCI_DMA_STATUS 0x040FD0
|
||||
#define PCI_DMA_IMASK 0x040FD4
|
||||
#define PCI_DMA_ICLR 0x040FD8
|
||||
#define PCI_DMA_ISET 0x040FDC
|
||||
#define PCI_ISTATUS 0x040FE0
|
||||
#define PCI_IMASK 0x040FE4
|
||||
#define PCI_ICLR 0x040FE8
|
||||
#define PCI_ISET 0x040FEC
|
||||
#define PCI_MOD_ID 0x040FFC
|
||||
|
||||
/*
|
||||
* PCI configuration cycle AD bus definition
|
||||
*/
|
||||
/* Type 0 */
|
||||
#define PCI_CFG_TYPE0_REG_SHF 0
|
||||
#define PCI_CFG_TYPE0_FUNC_SHF 8
|
||||
|
||||
/* Type 1 */
|
||||
#define PCI_CFG_TYPE1_REG_SHF 0
|
||||
#define PCI_CFG_TYPE1_FUNC_SHF 8
|
||||
#define PCI_CFG_TYPE1_DEV_SHF 11
|
||||
#define PCI_CFG_TYPE1_BUS_SHF 16
|
||||
|
||||
/*
|
||||
* Ethernet device DP83816 definition
|
||||
*/
|
||||
#define DP83816_IRQ_ETHER 66
|
||||
|
||||
#endif
|
|
@ -1,30 +0,0 @@
|
|||
#ifndef __IP3106_UART_H
|
||||
#define __IP3106_UART_H
|
||||
|
||||
#include <int.h>
|
||||
|
||||
/* early macros for kgdb use. fixme: clean this up */
|
||||
|
||||
#define UART_BASE 0xbbe4a000 /* PNX8550 */
|
||||
|
||||
#define PNX8550_UART_PORT0 (UART_BASE)
|
||||
#define PNX8550_UART_PORT1 (UART_BASE + 0x1000)
|
||||
|
||||
#define PNX8550_UART_INT(x) (PNX8550_INT_GIC_MIN+19+x)
|
||||
#define IRQ_TO_UART(x) (x-PNX8550_INT_GIC_MIN-19)
|
||||
|
||||
/* early macros needed for prom/kgdb */
|
||||
|
||||
#define ip3106_lcr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x000)
|
||||
#define ip3106_mcr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x004)
|
||||
#define ip3106_baud(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x008)
|
||||
#define ip3106_cfg(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x00C)
|
||||
#define ip3106_fifo(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x028)
|
||||
#define ip3106_istat(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE0)
|
||||
#define ip3106_ien(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE4)
|
||||
#define ip3106_iclr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE8)
|
||||
#define ip3106_iset(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFEC)
|
||||
#define ip3106_pd(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFF4)
|
||||
#define ip3106_mid(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFFC)
|
||||
|
||||
#endif
|
|
@ -1,32 +0,0 @@
|
|||
/*
|
||||
*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* USB specific definitions
|
||||
*
|
||||
* Author: source@mvista.com
|
||||
*
|
||||
* This program is free software; you can distribute it and/or modify it
|
||||
* under the terms of the GNU General Public License (Version 2) as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef __PNX8550_USB_H
|
||||
#define __PNX8550_USB_H
|
||||
|
||||
/*
|
||||
* USB Host controller
|
||||
*/
|
||||
|
||||
#define PNX8550_USB_OHCI_OP_BASE 0x1be48000
|
||||
#define PNX8550_USB_OHCI_OP_LEN 0x1000
|
||||
|
||||
#endif
|
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* Ralink SoC register definitions
|
||||
*
|
||||
* Copyright (C) 2013 John Crispin <blogic@openwrt.org>
|
||||
* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
|
||||
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _RALINK_REGS_H_
|
||||
#define _RALINK_REGS_H_
|
||||
|
||||
extern __iomem void *rt_sysc_membase;
|
||||
extern __iomem void *rt_memc_membase;
|
||||
|
||||
static inline void rt_sysc_w32(u32 val, unsigned reg)
|
||||
{
|
||||
__raw_writel(val, rt_sysc_membase + reg);
|
||||
}
|
||||
|
||||
static inline u32 rt_sysc_r32(unsigned reg)
|
||||
{
|
||||
return __raw_readl(rt_sysc_membase + reg);
|
||||
}
|
||||
|
||||
static inline void rt_memc_w32(u32 val, unsigned reg)
|
||||
{
|
||||
__raw_writel(val, rt_memc_membase + reg);
|
||||
}
|
||||
|
||||
static inline u32 rt_memc_r32(unsigned reg)
|
||||
{
|
||||
return __raw_readl(rt_memc_membase + reg);
|
||||
}
|
||||
|
||||
#endif /* _RALINK_REGS_H_ */
|
|
@ -0,0 +1,139 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*
|
||||
* Parts of this file are based on Ralink's 2.6.21 BSP
|
||||
*
|
||||
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
* Copyright (C) 2013 John Crispin <blogic@openwrt.org>
|
||||
*/
|
||||
|
||||
#ifndef _RT305X_REGS_H_
|
||||
#define _RT305X_REGS_H_
|
||||
|
||||
enum rt305x_soc_type {
|
||||
RT305X_SOC_UNKNOWN = 0,
|
||||
RT305X_SOC_RT3050,
|
||||
RT305X_SOC_RT3052,
|
||||
RT305X_SOC_RT3350,
|
||||
RT305X_SOC_RT3352,
|
||||
RT305X_SOC_RT5350,
|
||||
};
|
||||
|
||||
extern enum rt305x_soc_type rt305x_soc;
|
||||
|
||||
static inline int soc_is_rt3050(void)
|
||||
{
|
||||
return rt305x_soc == RT305X_SOC_RT3050;
|
||||
}
|
||||
|
||||
static inline int soc_is_rt3052(void)
|
||||
{
|
||||
return rt305x_soc == RT305X_SOC_RT3052;
|
||||
}
|
||||
|
||||
static inline int soc_is_rt305x(void)
|
||||
{
|
||||
return soc_is_rt3050() || soc_is_rt3052();
|
||||
}
|
||||
|
||||
static inline int soc_is_rt3350(void)
|
||||
{
|
||||
return rt305x_soc == RT305X_SOC_RT3350;
|
||||
}
|
||||
|
||||
static inline int soc_is_rt3352(void)
|
||||
{
|
||||
return rt305x_soc == RT305X_SOC_RT3352;
|
||||
}
|
||||
|
||||
static inline int soc_is_rt5350(void)
|
||||
{
|
||||
return rt305x_soc == RT305X_SOC_RT5350;
|
||||
}
|
||||
|
||||
#define RT305X_SYSC_BASE 0x10000000
|
||||
|
||||
#define SYSC_REG_CHIP_NAME0 0x00
|
||||
#define SYSC_REG_CHIP_NAME1 0x04
|
||||
#define SYSC_REG_CHIP_ID 0x0c
|
||||
#define SYSC_REG_SYSTEM_CONFIG 0x10
|
||||
|
||||
#define RT3052_CHIP_NAME0 0x30335452
|
||||
#define RT3052_CHIP_NAME1 0x20203235
|
||||
|
||||
#define RT3350_CHIP_NAME0 0x33335452
|
||||
#define RT3350_CHIP_NAME1 0x20203035
|
||||
|
||||
#define RT3352_CHIP_NAME0 0x33335452
|
||||
#define RT3352_CHIP_NAME1 0x20203235
|
||||
|
||||
#define RT5350_CHIP_NAME0 0x33355452
|
||||
#define RT5350_CHIP_NAME1 0x20203035
|
||||
|
||||
#define CHIP_ID_ID_MASK 0xff
|
||||
#define CHIP_ID_ID_SHIFT 8
|
||||
#define CHIP_ID_REV_MASK 0xff
|
||||
|
||||
#define RT305X_SYSCFG_CPUCLK_SHIFT 18
|
||||
#define RT305X_SYSCFG_CPUCLK_MASK 0x1
|
||||
#define RT305X_SYSCFG_CPUCLK_LOW 0x0
|
||||
#define RT305X_SYSCFG_CPUCLK_HIGH 0x1
|
||||
|
||||
#define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT 2
|
||||
#define RT305X_SYSCFG_CPUCLK_MASK 0x1
|
||||
#define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 0x1
|
||||
|
||||
#define RT3352_SYSCFG0_CPUCLK_SHIFT 8
|
||||
#define RT3352_SYSCFG0_CPUCLK_MASK 0x1
|
||||
#define RT3352_SYSCFG0_CPUCLK_LOW 0x0
|
||||
#define RT3352_SYSCFG0_CPUCLK_HIGH 0x1
|
||||
|
||||
#define RT5350_SYSCFG0_CPUCLK_SHIFT 8
|
||||
#define RT5350_SYSCFG0_CPUCLK_MASK 0x3
|
||||
#define RT5350_SYSCFG0_CPUCLK_360 0x0
|
||||
#define RT5350_SYSCFG0_CPUCLK_320 0x2
|
||||
#define RT5350_SYSCFG0_CPUCLK_300 0x3
|
||||
|
||||
/* multi function gpio pins */
|
||||
#define RT305X_GPIO_I2C_SD 1
|
||||
#define RT305X_GPIO_I2C_SCLK 2
|
||||
#define RT305X_GPIO_SPI_EN 3
|
||||
#define RT305X_GPIO_SPI_CLK 4
|
||||
/* GPIO 7-14 is shared between UART0, PCM and I2S interfaces */
|
||||
#define RT305X_GPIO_7 7
|
||||
#define RT305X_GPIO_10 10
|
||||
#define RT305X_GPIO_14 14
|
||||
#define RT305X_GPIO_UART1_TXD 15
|
||||
#define RT305X_GPIO_UART1_RXD 16
|
||||
#define RT305X_GPIO_JTAG_TDO 17
|
||||
#define RT305X_GPIO_JTAG_TDI 18
|
||||
#define RT305X_GPIO_MDIO_MDC 22
|
||||
#define RT305X_GPIO_MDIO_MDIO 23
|
||||
#define RT305X_GPIO_SDRAM_MD16 24
|
||||
#define RT305X_GPIO_SDRAM_MD31 39
|
||||
#define RT305X_GPIO_GE0_TXD0 40
|
||||
#define RT305X_GPIO_GE0_RXCLK 51
|
||||
|
||||
#define RT305X_GPIO_MODE_I2C BIT(0)
|
||||
#define RT305X_GPIO_MODE_SPI BIT(1)
|
||||
#define RT305X_GPIO_MODE_UART0_SHIFT 2
|
||||
#define RT305X_GPIO_MODE_UART0_MASK 0x7
|
||||
#define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
|
||||
#define RT305X_GPIO_MODE_UARTF 0x0
|
||||
#define RT305X_GPIO_MODE_PCM_UARTF 0x1
|
||||
#define RT305X_GPIO_MODE_PCM_I2S 0x2
|
||||
#define RT305X_GPIO_MODE_I2S_UARTF 0x3
|
||||
#define RT305X_GPIO_MODE_PCM_GPIO 0x4
|
||||
#define RT305X_GPIO_MODE_GPIO_UARTF 0x5
|
||||
#define RT305X_GPIO_MODE_GPIO_I2S 0x6
|
||||
#define RT305X_GPIO_MODE_GPIO 0x7
|
||||
#define RT305X_GPIO_MODE_UART1 BIT(5)
|
||||
#define RT305X_GPIO_MODE_JTAG BIT(6)
|
||||
#define RT305X_GPIO_MODE_MDIO BIT(7)
|
||||
#define RT305X_GPIO_MODE_SDRAM BIT(8)
|
||||
#define RT305X_GPIO_MODE_RGMII BIT(9)
|
||||
|
||||
#endif
|
|
@ -5,8 +5,8 @@
|
|||
*
|
||||
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
|
||||
*/
|
||||
#ifndef __ASM_MIPS_MACH_PNX8550_WAR_H
|
||||
#define __ASM_MIPS_MACH_PNX8550_WAR_H
|
||||
#ifndef __ASM_MACH_RALINK_WAR_H
|
||||
#define __ASM_MACH_RALINK_WAR_H
|
||||
|
||||
#define R4600_V1_INDEX_ICACHEOP_WAR 0
|
||||
#define R4600_V1_HIT_CACHEOP_WAR 0
|
||||
|
@ -17,8 +17,9 @@
|
|||
#define MIPS4K_ICACHE_REFILL_WAR 0
|
||||
#define MIPS_CACHE_SYNC_WAR 0
|
||||
#define TX49XX_ICACHE_INDEX_INV_WAR 0
|
||||
#define RM9000_CDEX_SMP_WAR 0
|
||||
#define ICACHE_REFILLS_WORKAROUND_WAR 0
|
||||
#define R10000_LLSC_WAR 0
|
||||
#define MIPS34K_MISSED_ITLB_WAR 0
|
||||
|
||||
#endif /* __ASM_MIPS_MACH_PNX8550_WAR_H */
|
||||
#endif /* __ASM_MACH_RALINK_WAR_H */
|
|
@ -1,21 +1,14 @@
|
|||
/*
|
||||
* Carsten Langgaard, carstenl@mips.com
|
||||
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can distribute it and/or modify it
|
||||
* under the terms of the GNU General Public License (Version 2) as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
|
||||
*
|
||||
* Defines of the MIPS boards specific address-MAP, registers, etc.
|
||||
*
|
||||
* Copyright (C) 2000,2012 MIPS Technologies, Inc.
|
||||
* All rights reserved.
|
||||
* Authors: Carsten Langgaard <carstenl@mips.com>
|
||||
* Steven J. Hill <sjhill@mips.com>
|
||||
*/
|
||||
#ifndef __ASM_MIPS_BOARDS_GENERIC_H
|
||||
#define __ASM_MIPS_BOARDS_GENERIC_H
|
||||
|
@ -30,13 +23,6 @@
|
|||
#define ASCII_DISPLAY_WORD_BASE 0x1f000410
|
||||
#define ASCII_DISPLAY_POS_BASE 0x1f000418
|
||||
|
||||
|
||||
/*
|
||||
* Yamon Prom print address.
|
||||
*/
|
||||
#define YAMON_PROM_PRINT_ADDR 0x1fc00504
|
||||
|
||||
|
||||
/*
|
||||
* Reset register.
|
||||
*/
|
||||
|
@ -87,6 +73,10 @@
|
|||
|
||||
extern int mips_revision_sconid;
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
extern struct boot_param_header __dtb_start;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
extern void mips_pcibios_init(void);
|
||||
#else
|
||||
|
|
|
@ -595,6 +595,8 @@
|
|||
#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
|
||||
#define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
|
||||
#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
|
||||
#define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
|
||||
#define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
|
||||
|
||||
#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
|
||||
#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
|
||||
|
@ -1143,17 +1145,151 @@ do { \
|
|||
* Macros to access the floating point coprocessor control registers
|
||||
*/
|
||||
#define read_32bit_cp1_register(source) \
|
||||
({ int __res; \
|
||||
({ \
|
||||
int __res; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
".set\tpush\n\t" \
|
||||
".set\treorder\n\t" \
|
||||
/* gas fails to assemble cfc1 for some archs (octeon).*/ \
|
||||
".set\tmips1\n\t" \
|
||||
"cfc1\t%0,"STR(source)"\n\t" \
|
||||
".set\tpop" \
|
||||
" .set push \n" \
|
||||
" .set reorder \n" \
|
||||
" # gas fails to assemble cfc1 for some archs, \n" \
|
||||
" # like Octeon. \n" \
|
||||
" .set mips1 \n" \
|
||||
" cfc1 %0,"STR(source)" \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (__res)); \
|
||||
__res;})
|
||||
__res; \
|
||||
})
|
||||
|
||||
#ifdef HAVE_AS_DSP
|
||||
#define rddsp(mask) \
|
||||
({ \
|
||||
unsigned int __dspctl; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
" rddsp %0, %x1 \n" \
|
||||
: "=r" (__dspctl) \
|
||||
: "i" (mask)); \
|
||||
__dspctl; \
|
||||
})
|
||||
|
||||
#define wrdsp(val, mask) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" wrdsp %0, %x1 \n" \
|
||||
: \
|
||||
: "r" (val), "i" (mask)); \
|
||||
} while (0)
|
||||
|
||||
#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
|
||||
#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
|
||||
#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
|
||||
#define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
|
||||
|
||||
#define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
|
||||
#define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
|
||||
#define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
|
||||
#define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
|
||||
|
||||
#define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
|
||||
#define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
|
||||
#define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
|
||||
#define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
|
||||
|
||||
#define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
|
||||
#define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
|
||||
#define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
|
||||
#define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
|
||||
|
||||
#else
|
||||
|
||||
#ifdef CONFIG_CPU_MICROMIPS
|
||||
#define rddsp(mask) \
|
||||
({ \
|
||||
unsigned int __res; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" # rddsp $1, %x1 \n" \
|
||||
" .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \
|
||||
" .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \
|
||||
" move %0, $1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (__res) \
|
||||
: "i" (mask)); \
|
||||
__res; \
|
||||
})
|
||||
|
||||
#define wrdsp(val, mask) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" move $1, %0 \n" \
|
||||
" # wrdsp $1, %x1 \n" \
|
||||
" .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \
|
||||
" .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (val), "i" (mask)); \
|
||||
} while (0)
|
||||
|
||||
#define _umips_dsp_mfxxx(ins) \
|
||||
({ \
|
||||
unsigned long __treg; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" .hword 0x0001 \n" \
|
||||
" .hword %x1 \n" \
|
||||
" move %0, $1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (__treg) \
|
||||
: "i" (ins)); \
|
||||
__treg; \
|
||||
})
|
||||
|
||||
#define _umips_dsp_mtxxx(val, ins) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" move $1, %0 \n" \
|
||||
" .hword 0x0001 \n" \
|
||||
" .hword %x1 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (val), "i" (ins)); \
|
||||
} while (0)
|
||||
|
||||
#define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
|
||||
#define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
|
||||
|
||||
#define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
|
||||
#define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
|
||||
|
||||
#define mflo0() _umips_dsp_mflo(0)
|
||||
#define mflo1() _umips_dsp_mflo(1)
|
||||
#define mflo2() _umips_dsp_mflo(2)
|
||||
#define mflo3() _umips_dsp_mflo(3)
|
||||
|
||||
#define mfhi0() _umips_dsp_mfhi(0)
|
||||
#define mfhi1() _umips_dsp_mfhi(1)
|
||||
#define mfhi2() _umips_dsp_mfhi(2)
|
||||
#define mfhi3() _umips_dsp_mfhi(3)
|
||||
|
||||
#define mtlo0(x) _umips_dsp_mtlo(x, 0)
|
||||
#define mtlo1(x) _umips_dsp_mtlo(x, 1)
|
||||
#define mtlo2(x) _umips_dsp_mtlo(x, 2)
|
||||
#define mtlo3(x) _umips_dsp_mtlo(x, 3)
|
||||
|
||||
#define mthi0(x) _umips_dsp_mthi(x, 0)
|
||||
#define mthi1(x) _umips_dsp_mthi(x, 1)
|
||||
#define mthi2(x) _umips_dsp_mthi(x, 2)
|
||||
#define mthi3(x) _umips_dsp_mthi(x, 3)
|
||||
|
||||
#else /* !CONFIG_CPU_MICROMIPS */
|
||||
#define rddsp(mask) \
|
||||
({ \
|
||||
unsigned int __res; \
|
||||
|
@ -1183,253 +1319,60 @@ do { \
|
|||
: "r" (val), "i" (mask)); \
|
||||
} while (0)
|
||||
|
||||
#if 0 /* Need DSP ASE capable assembler ... */
|
||||
#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
|
||||
#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
|
||||
#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
|
||||
#define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
|
||||
|
||||
#define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
|
||||
#define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
|
||||
#define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
|
||||
#define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
|
||||
|
||||
#define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
|
||||
#define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
|
||||
#define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
|
||||
#define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
|
||||
|
||||
#define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
|
||||
#define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
|
||||
#define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
|
||||
#define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
|
||||
|
||||
#else
|
||||
|
||||
#define mfhi0() \
|
||||
#define _dsp_mfxxx(ins) \
|
||||
({ \
|
||||
unsigned long __treg; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" # mfhi %0, $ac0 \n" \
|
||||
" .word 0x00000810 \n" \
|
||||
" .word (0x00000810 | %1) \n" \
|
||||
" move %0, $1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (__treg)); \
|
||||
: "=r" (__treg) \
|
||||
: "i" (ins)); \
|
||||
__treg; \
|
||||
})
|
||||
|
||||
#define mfhi1() \
|
||||
({ \
|
||||
unsigned long __treg; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" # mfhi %0, $ac1 \n" \
|
||||
" .word 0x00200810 \n" \
|
||||
" move %0, $1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (__treg)); \
|
||||
__treg; \
|
||||
})
|
||||
|
||||
#define mfhi2() \
|
||||
({ \
|
||||
unsigned long __treg; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" # mfhi %0, $ac2 \n" \
|
||||
" .word 0x00400810 \n" \
|
||||
" move %0, $1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (__treg)); \
|
||||
__treg; \
|
||||
})
|
||||
|
||||
#define mfhi3() \
|
||||
({ \
|
||||
unsigned long __treg; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" # mfhi %0, $ac3 \n" \
|
||||
" .word 0x00600810 \n" \
|
||||
" move %0, $1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (__treg)); \
|
||||
__treg; \
|
||||
})
|
||||
|
||||
#define mflo0() \
|
||||
({ \
|
||||
unsigned long __treg; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" # mflo %0, $ac0 \n" \
|
||||
" .word 0x00000812 \n" \
|
||||
" move %0, $1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (__treg)); \
|
||||
__treg; \
|
||||
})
|
||||
|
||||
#define mflo1() \
|
||||
({ \
|
||||
unsigned long __treg; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" # mflo %0, $ac1 \n" \
|
||||
" .word 0x00200812 \n" \
|
||||
" move %0, $1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (__treg)); \
|
||||
__treg; \
|
||||
})
|
||||
|
||||
#define mflo2() \
|
||||
({ \
|
||||
unsigned long __treg; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" # mflo %0, $ac2 \n" \
|
||||
" .word 0x00400812 \n" \
|
||||
" move %0, $1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (__treg)); \
|
||||
__treg; \
|
||||
})
|
||||
|
||||
#define mflo3() \
|
||||
({ \
|
||||
unsigned long __treg; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" # mflo %0, $ac3 \n" \
|
||||
" .word 0x00600812 \n" \
|
||||
" move %0, $1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (__treg)); \
|
||||
__treg; \
|
||||
})
|
||||
|
||||
#define mthi0(x) \
|
||||
#define _dsp_mtxxx(val, ins) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" move $1, %0 \n" \
|
||||
" # mthi $1, $ac0 \n" \
|
||||
" .word 0x00200011 \n" \
|
||||
" .word (0x00200011 | %1) \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (x)); \
|
||||
: "r" (val), "i" (ins)); \
|
||||
} while (0)
|
||||
|
||||
#define mthi1(x) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" move $1, %0 \n" \
|
||||
" # mthi $1, $ac1 \n" \
|
||||
" .word 0x00200811 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (x)); \
|
||||
} while (0)
|
||||
#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
|
||||
#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
|
||||
|
||||
#define mthi2(x) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" move $1, %0 \n" \
|
||||
" # mthi $1, $ac2 \n" \
|
||||
" .word 0x00201011 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (x)); \
|
||||
} while (0)
|
||||
#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
|
||||
#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
|
||||
|
||||
#define mthi3(x) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" move $1, %0 \n" \
|
||||
" # mthi $1, $ac3 \n" \
|
||||
" .word 0x00201811 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (x)); \
|
||||
} while (0)
|
||||
#define mflo0() _dsp_mflo(0)
|
||||
#define mflo1() _dsp_mflo(1)
|
||||
#define mflo2() _dsp_mflo(2)
|
||||
#define mflo3() _dsp_mflo(3)
|
||||
|
||||
#define mtlo0(x) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" move $1, %0 \n" \
|
||||
" # mtlo $1, $ac0 \n" \
|
||||
" .word 0x00200013 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (x)); \
|
||||
} while (0)
|
||||
#define mfhi0() _dsp_mfhi(0)
|
||||
#define mfhi1() _dsp_mfhi(1)
|
||||
#define mfhi2() _dsp_mfhi(2)
|
||||
#define mfhi3() _dsp_mfhi(3)
|
||||
|
||||
#define mtlo1(x) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" move $1, %0 \n" \
|
||||
" # mtlo $1, $ac1 \n" \
|
||||
" .word 0x00200813 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (x)); \
|
||||
} while (0)
|
||||
#define mtlo0(x) _dsp_mtlo(x, 0)
|
||||
#define mtlo1(x) _dsp_mtlo(x, 1)
|
||||
#define mtlo2(x) _dsp_mtlo(x, 2)
|
||||
#define mtlo3(x) _dsp_mtlo(x, 3)
|
||||
|
||||
#define mtlo2(x) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" move $1, %0 \n" \
|
||||
" # mtlo $1, $ac2 \n" \
|
||||
" .word 0x00201013 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (x)); \
|
||||
} while (0)
|
||||
|
||||
#define mtlo3(x) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set noat \n" \
|
||||
" move $1, %0 \n" \
|
||||
" # mtlo $1, $ac3 \n" \
|
||||
" .word 0x00201813 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (x)); \
|
||||
} while (0)
|
||||
#define mthi0(x) _dsp_mthi(x, 0)
|
||||
#define mthi1(x) _dsp_mthi(x, 1)
|
||||
#define mthi2(x) _dsp_mthi(x, 2)
|
||||
#define mthi3(x) _dsp_mthi(x, 3)
|
||||
|
||||
#endif /* CONFIG_CPU_MICROMIPS */
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
|
@ -68,6 +68,85 @@ do { \
|
|||
__write_64bit_c0_register($9, 7, (val)); \
|
||||
} while (0)
|
||||
|
||||
/*
|
||||
* Handling the 64 bit EIMR and EIRR registers in 32-bit mode with
|
||||
* standard functions will be very inefficient. This provides
|
||||
* optimized functions for the normal operations on the registers.
|
||||
*
|
||||
* Call with interrupts disabled.
|
||||
*/
|
||||
static inline void ack_c0_eirr(int irq)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
".set push\n\t"
|
||||
".set mips64\n\t"
|
||||
".set noat\n\t"
|
||||
"li $1, 1\n\t"
|
||||
"dsllv $1, $1, %0\n\t"
|
||||
"dmtc0 $1, $9, 6\n\t"
|
||||
".set pop"
|
||||
: : "r" (irq));
|
||||
}
|
||||
|
||||
static inline void set_c0_eimr(int irq)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
".set push\n\t"
|
||||
".set mips64\n\t"
|
||||
".set noat\n\t"
|
||||
"li $1, 1\n\t"
|
||||
"dsllv %0, $1, %0\n\t"
|
||||
"dmfc0 $1, $9, 7\n\t"
|
||||
"or $1, %0\n\t"
|
||||
"dmtc0 $1, $9, 7\n\t"
|
||||
".set pop"
|
||||
: "+r" (irq));
|
||||
}
|
||||
|
||||
static inline void clear_c0_eimr(int irq)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
".set push\n\t"
|
||||
".set mips64\n\t"
|
||||
".set noat\n\t"
|
||||
"li $1, 1\n\t"
|
||||
"dsllv %0, $1, %0\n\t"
|
||||
"dmfc0 $1, $9, 7\n\t"
|
||||
"or $1, %0\n\t"
|
||||
"xor $1, %0\n\t"
|
||||
"dmtc0 $1, $9, 7\n\t"
|
||||
".set pop"
|
||||
: "+r" (irq));
|
||||
}
|
||||
|
||||
/*
|
||||
* Read c0 eimr and c0 eirr, do AND of the two values, the result is
|
||||
* the interrupts which are raised and are not masked.
|
||||
*/
|
||||
static inline uint64_t read_c0_eirr_and_eimr(void)
|
||||
{
|
||||
uint64_t val;
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
val = read_c0_eimr() & read_c0_eirr();
|
||||
#else
|
||||
__asm__ __volatile__(
|
||||
".set push\n\t"
|
||||
".set mips64\n\t"
|
||||
".set noat\n\t"
|
||||
"dmfc0 %M0, $9, 6\n\t"
|
||||
"dmfc0 %L0, $9, 7\n\t"
|
||||
"and %M0, %L0\n\t"
|
||||
"dsll %L0, %M0, 32\n\t"
|
||||
"dsra %M0, %M0, 32\n\t"
|
||||
"dsra %L0, %L0, 32\n\t"
|
||||
".set pop"
|
||||
: "=r" (val));
|
||||
#endif
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline int hard_smp_processor_id(void)
|
||||
{
|
||||
return __read_32bit_c0_register($15, 1) & 0x3ff;
|
||||
|
|
|
@ -46,6 +46,8 @@
|
|||
#define CPU_BLOCKID_FPU 9
|
||||
#define CPU_BLOCKID_MAP 10
|
||||
|
||||
#define ICU_DEFEATURE 0x100
|
||||
|
||||
#define LSU_DEFEATURE 0x304
|
||||
#define LSU_DEBUG_ADDR 0x305
|
||||
#define LSU_DEBUG_DATA0 0x306
|
||||
|
|
|
@ -261,6 +261,8 @@
|
|||
#define PIC_LOCAL_SCHEDULING 1
|
||||
#define PIC_GLOBAL_SCHEDULING 0
|
||||
|
||||
#define PIC_CLK_HZ 133333333
|
||||
|
||||
#define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r)
|
||||
#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)
|
||||
#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node))
|
||||
|
@ -315,6 +317,12 @@ nlm_pic_read_timer(uint64_t base, int timer)
|
|||
return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer));
|
||||
}
|
||||
|
||||
static inline uint32_t
|
||||
nlm_pic_read_timer32(uint64_t base, int timer)
|
||||
{
|
||||
return (uint32_t)nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer));
|
||||
}
|
||||
|
||||
static inline void
|
||||
nlm_pic_write_timer(uint64_t base, int timer, uint64_t value)
|
||||
{
|
||||
|
@ -376,9 +384,9 @@ nlm_pic_ack(uint64_t base, int irt_num)
|
|||
}
|
||||
|
||||
static inline void
|
||||
nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt)
|
||||
nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt, int en)
|
||||
{
|
||||
nlm_pic_write_irt_direct(base, irt, 0, 0, 0, irq, hwt);
|
||||
nlm_pic_write_irt_direct(base, irt, en, 0, 0, irq, hwt);
|
||||
}
|
||||
|
||||
int nlm_irq_to_irt(int irq);
|
||||
|
|
|
@ -35,10 +35,11 @@
|
|||
#ifndef _ASM_NLM_XLR_PIC_H
|
||||
#define _ASM_NLM_XLR_PIC_H
|
||||
|
||||
#define PIC_CLKS_PER_SEC 66666666ULL
|
||||
#define PIC_CLK_HZ 66666666
|
||||
/* PIC hardware interrupt numbers */
|
||||
#define PIC_IRT_WD_INDEX 0
|
||||
#define PIC_IRT_TIMER_0_INDEX 1
|
||||
#define PIC_IRT_TIMER_INDEX(i) ((i) + PIC_IRT_TIMER_0_INDEX)
|
||||
#define PIC_IRT_TIMER_1_INDEX 2
|
||||
#define PIC_IRT_TIMER_2_INDEX 3
|
||||
#define PIC_IRT_TIMER_3_INDEX 4
|
||||
|
@ -99,6 +100,7 @@
|
|||
|
||||
/* PIC Registers */
|
||||
#define PIC_CTRL 0x00
|
||||
#define PIC_CTRL_STE 8 /* timer enable start bit */
|
||||
#define PIC_IPI 0x04
|
||||
#define PIC_INT_ACK 0x06
|
||||
|
||||
|
@ -251,12 +253,52 @@ nlm_pic_ack(uint64_t base, int irt)
|
|||
}
|
||||
|
||||
static inline void
|
||||
nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt)
|
||||
nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt, int en)
|
||||
{
|
||||
nlm_write_reg(base, PIC_IRT_0(irt), (1u << hwt));
|
||||
/* local scheduling, invalid, level by default */
|
||||
nlm_write_reg(base, PIC_IRT_1(irt),
|
||||
(1 << 30) | (1 << 6) | irq);
|
||||
(en << 30) | (1 << 6) | irq);
|
||||
}
|
||||
|
||||
static inline uint64_t
|
||||
nlm_pic_read_timer(uint64_t base, int timer)
|
||||
{
|
||||
uint32_t up1, up2, low;
|
||||
|
||||
up1 = nlm_read_reg(base, PIC_TIMER_COUNT_1(timer));
|
||||
low = nlm_read_reg(base, PIC_TIMER_COUNT_0(timer));
|
||||
up2 = nlm_read_reg(base, PIC_TIMER_COUNT_1(timer));
|
||||
|
||||
if (up1 != up2) /* wrapped, get the new low */
|
||||
low = nlm_read_reg(base, PIC_TIMER_COUNT_0(timer));
|
||||
return ((uint64_t)up2 << 32) | low;
|
||||
|
||||
}
|
||||
|
||||
static inline uint32_t
|
||||
nlm_pic_read_timer32(uint64_t base, int timer)
|
||||
{
|
||||
return nlm_read_reg(base, PIC_TIMER_COUNT_0(timer));
|
||||
}
|
||||
|
||||
static inline void
|
||||
nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu)
|
||||
{
|
||||
uint32_t up, low;
|
||||
uint64_t pic_ctrl = nlm_read_reg(base, PIC_CTRL);
|
||||
int en;
|
||||
|
||||
en = (irq > 0);
|
||||
up = value >> 32;
|
||||
low = value & 0xFFFFFFFF;
|
||||
nlm_write_reg(base, PIC_TIMER_MAXVAL_0(timer), low);
|
||||
nlm_write_reg(base, PIC_TIMER_MAXVAL_1(timer), up);
|
||||
nlm_pic_init_irt(base, PIC_IRT_TIMER_INDEX(timer), irq, cpu, 0);
|
||||
|
||||
/* enable the timer */
|
||||
pic_ctrl |= (1 << (PIC_CTRL_STE + timer));
|
||||
nlm_write_reg(base, PIC_CTRL, pic_ctrl);
|
||||
}
|
||||
#endif
|
||||
#endif /* _ASM_NLM_XLR_PIC_H */
|
||||
|
|
|
@ -144,8 +144,13 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
|
|||
|
||||
extern char * (*pcibios_plat_setup)(char *str);
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
/* this function parses memory ranges from a device node */
|
||||
extern void pci_load_of_ranges(struct pci_controller *hose,
|
||||
struct device_node *node);
|
||||
#else
|
||||
static inline void pci_load_of_ranges(struct pci_controller *hose,
|
||||
struct device_node *node) {}
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_PCI_H */
|
||||
|
|
|
@ -75,7 +75,7 @@ extern int init_r4k_clocksource(void);
|
|||
|
||||
static inline int init_mips_clocksource(void)
|
||||
{
|
||||
#ifdef CONFIG_CSRC_R4K
|
||||
#if defined(CONFIG_CSRC_R4K) && !defined(CONFIG_CSRC_GIC)
|
||||
return init_r4k_clocksource();
|
||||
#else
|
||||
return 0;
|
||||
|
|
|
@ -8,6 +8,7 @@ header-y += byteorder.h
|
|||
header-y += cachectl.h
|
||||
header-y += errno.h
|
||||
header-y += fcntl.h
|
||||
header-y += inst.h
|
||||
header-y += ioctl.h
|
||||
header-y += ioctls.h
|
||||
header-y += ipcbuf.h
|
||||
|
|
|
@ -6,8 +6,8 @@
|
|||
* Copyright (C) 1995, 2003 by Ralf Baechle
|
||||
* Copyright (C) 1999 Silicon Graphics, Inc.
|
||||
*/
|
||||
#ifndef __ASM_BREAK_H
|
||||
#define __ASM_BREAK_H
|
||||
#ifndef __UAPI_ASM_BREAK_H
|
||||
#define __UAPI_ASM_BREAK_H
|
||||
|
||||
/*
|
||||
* The following break codes are or were in use for specific purposes in
|
||||
|
@ -16,22 +16,14 @@
|
|||
* non-Linux/MIPS object files or make use of them in the future.
|
||||
*/
|
||||
#define BRK_USERBP 0 /* User bp (used by debuggers) */
|
||||
#define BRK_KERNELBP 1 /* Break in the kernel */
|
||||
#define BRK_ABORT 2 /* Sometimes used by abort(3) to SIGIOT */
|
||||
#define BRK_BD_TAKEN 3 /* For bd slot emulation - not implemented */
|
||||
#define BRK_BD_NOTTAKEN 4 /* For bd slot emulation - not implemented */
|
||||
#define BRK_SSTEPBP 5 /* User bp (used by debuggers) */
|
||||
#define BRK_OVERFLOW 6 /* Overflow check */
|
||||
#define BRK_DIVZERO 7 /* Divide by zero check */
|
||||
#define BRK_RANGE 8 /* Range error check */
|
||||
#define BRK_STACKOVERFLOW 9 /* For Ada stackchecking */
|
||||
#define BRK_NORLD 10 /* No rld found - not used by Linux/MIPS */
|
||||
#define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */
|
||||
#define BRK_BUG 512 /* Used by BUG() */
|
||||
#define BRK_KDB 513 /* Used in KDB_ENTER() */
|
||||
#define BRK_BUG 12 /* Used by BUG() */
|
||||
#define BRK_MEMU 514 /* Used by FPU emulator */
|
||||
#define BRK_KPROBE_BP 515 /* Kprobe break */
|
||||
#define BRK_KPROBE_SSTEPBP 516 /* Kprobe single step software implementation */
|
||||
#define BRK_MULOVF 1023 /* Multiply overflow */
|
||||
|
||||
#endif /* __ASM_BREAK_H */
|
||||
#endif /* __UAPI_ASM_BREAK_H */
|
||||
|
|
|
@ -0,0 +1,331 @@
|
|||
/*
|
||||
* Format of an instruction in memory.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 1996, 2000 by Ralf Baechle
|
||||
* Copyright (C) 2006 by Thiemo Seufer
|
||||
*/
|
||||
#ifndef _UAPI_ASM_INST_H
|
||||
#define _UAPI_ASM_INST_H
|
||||
|
||||
/*
|
||||
* Major opcodes; before MIPS IV cop1x was called cop3.
|
||||
*/
|
||||
enum major_op {
|
||||
spec_op, bcond_op, j_op, jal_op,
|
||||
beq_op, bne_op, blez_op, bgtz_op,
|
||||
addi_op, addiu_op, slti_op, sltiu_op,
|
||||
andi_op, ori_op, xori_op, lui_op,
|
||||
cop0_op, cop1_op, cop2_op, cop1x_op,
|
||||
beql_op, bnel_op, blezl_op, bgtzl_op,
|
||||
daddi_op, daddiu_op, ldl_op, ldr_op,
|
||||
spec2_op, jalx_op, mdmx_op, spec3_op,
|
||||
lb_op, lh_op, lwl_op, lw_op,
|
||||
lbu_op, lhu_op, lwr_op, lwu_op,
|
||||
sb_op, sh_op, swl_op, sw_op,
|
||||
sdl_op, sdr_op, swr_op, cache_op,
|
||||
ll_op, lwc1_op, lwc2_op, pref_op,
|
||||
lld_op, ldc1_op, ldc2_op, ld_op,
|
||||
sc_op, swc1_op, swc2_op, major_3b_op,
|
||||
scd_op, sdc1_op, sdc2_op, sd_op
|
||||
};
|
||||
|
||||
/*
|
||||
* func field of spec opcode.
|
||||
*/
|
||||
enum spec_op {
|
||||
sll_op, movc_op, srl_op, sra_op,
|
||||
sllv_op, pmon_op, srlv_op, srav_op,
|
||||
jr_op, jalr_op, movz_op, movn_op,
|
||||
syscall_op, break_op, spim_op, sync_op,
|
||||
mfhi_op, mthi_op, mflo_op, mtlo_op,
|
||||
dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
|
||||
mult_op, multu_op, div_op, divu_op,
|
||||
dmult_op, dmultu_op, ddiv_op, ddivu_op,
|
||||
add_op, addu_op, sub_op, subu_op,
|
||||
and_op, or_op, xor_op, nor_op,
|
||||
spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
|
||||
dadd_op, daddu_op, dsub_op, dsubu_op,
|
||||
tge_op, tgeu_op, tlt_op, tltu_op,
|
||||
teq_op, spec5_unused_op, tne_op, spec6_unused_op,
|
||||
dsll_op, spec7_unused_op, dsrl_op, dsra_op,
|
||||
dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
|
||||
};
|
||||
|
||||
/*
|
||||
* func field of spec2 opcode.
|
||||
*/
|
||||
enum spec2_op {
|
||||
madd_op, maddu_op, mul_op, spec2_3_unused_op,
|
||||
msub_op, msubu_op, /* more unused ops */
|
||||
clz_op = 0x20, clo_op,
|
||||
dclz_op = 0x24, dclo_op,
|
||||
sdbpp_op = 0x3f
|
||||
};
|
||||
|
||||
/*
|
||||
* func field of spec3 opcode.
|
||||
*/
|
||||
enum spec3_op {
|
||||
ext_op, dextm_op, dextu_op, dext_op,
|
||||
ins_op, dinsm_op, dinsu_op, dins_op,
|
||||
lx_op = 0x0a,
|
||||
bshfl_op = 0x20,
|
||||
dbshfl_op = 0x24,
|
||||
rdhwr_op = 0x3b
|
||||
};
|
||||
|
||||
/*
|
||||
* rt field of bcond opcodes.
|
||||
*/
|
||||
enum rt_op {
|
||||
bltz_op, bgez_op, bltzl_op, bgezl_op,
|
||||
spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
|
||||
tgei_op, tgeiu_op, tlti_op, tltiu_op,
|
||||
teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
|
||||
bltzal_op, bgezal_op, bltzall_op, bgezall_op,
|
||||
rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
|
||||
rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
|
||||
bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f
|
||||
};
|
||||
|
||||
/*
|
||||
* rs field of cop opcodes.
|
||||
*/
|
||||
enum cop_op {
|
||||
mfc_op = 0x00, dmfc_op = 0x01,
|
||||
cfc_op = 0x02, mtc_op = 0x04,
|
||||
dmtc_op = 0x05, ctc_op = 0x06,
|
||||
bc_op = 0x08, cop_op = 0x10,
|
||||
copm_op = 0x18
|
||||
};
|
||||
|
||||
/*
|
||||
* rt field of cop.bc_op opcodes
|
||||
*/
|
||||
enum bcop_op {
|
||||
bcf_op, bct_op, bcfl_op, bctl_op
|
||||
};
|
||||
|
||||
/*
|
||||
* func field of cop0 coi opcodes.
|
||||
*/
|
||||
enum cop0_coi_func {
|
||||
tlbr_op = 0x01, tlbwi_op = 0x02,
|
||||
tlbwr_op = 0x06, tlbp_op = 0x08,
|
||||
rfe_op = 0x10, eret_op = 0x18
|
||||
};
|
||||
|
||||
/*
|
||||
* func field of cop0 com opcodes.
|
||||
*/
|
||||
enum cop0_com_func {
|
||||
tlbr1_op = 0x01, tlbw_op = 0x02,
|
||||
tlbp1_op = 0x08, dctr_op = 0x09,
|
||||
dctw_op = 0x0a
|
||||
};
|
||||
|
||||
/*
|
||||
* fmt field of cop1 opcodes.
|
||||
*/
|
||||
enum cop1_fmt {
|
||||
s_fmt, d_fmt, e_fmt, q_fmt,
|
||||
w_fmt, l_fmt
|
||||
};
|
||||
|
||||
/*
|
||||
* func field of cop1 instructions using d, s or w format.
|
||||
*/
|
||||
enum cop1_sdw_func {
|
||||
fadd_op = 0x00, fsub_op = 0x01,
|
||||
fmul_op = 0x02, fdiv_op = 0x03,
|
||||
fsqrt_op = 0x04, fabs_op = 0x05,
|
||||
fmov_op = 0x06, fneg_op = 0x07,
|
||||
froundl_op = 0x08, ftruncl_op = 0x09,
|
||||
fceill_op = 0x0a, ffloorl_op = 0x0b,
|
||||
fround_op = 0x0c, ftrunc_op = 0x0d,
|
||||
fceil_op = 0x0e, ffloor_op = 0x0f,
|
||||
fmovc_op = 0x11, fmovz_op = 0x12,
|
||||
fmovn_op = 0x13, frecip_op = 0x15,
|
||||
frsqrt_op = 0x16, fcvts_op = 0x20,
|
||||
fcvtd_op = 0x21, fcvte_op = 0x22,
|
||||
fcvtw_op = 0x24, fcvtl_op = 0x25,
|
||||
fcmp_op = 0x30
|
||||
};
|
||||
|
||||
/*
|
||||
* func field of cop1x opcodes (MIPS IV).
|
||||
*/
|
||||
enum cop1x_func {
|
||||
lwxc1_op = 0x00, ldxc1_op = 0x01,
|
||||
pfetch_op = 0x07, swxc1_op = 0x08,
|
||||
sdxc1_op = 0x09, madd_s_op = 0x20,
|
||||
madd_d_op = 0x21, madd_e_op = 0x22,
|
||||
msub_s_op = 0x28, msub_d_op = 0x29,
|
||||
msub_e_op = 0x2a, nmadd_s_op = 0x30,
|
||||
nmadd_d_op = 0x31, nmadd_e_op = 0x32,
|
||||
nmsub_s_op = 0x38, nmsub_d_op = 0x39,
|
||||
nmsub_e_op = 0x3a
|
||||
};
|
||||
|
||||
/*
|
||||
* func field for mad opcodes (MIPS IV).
|
||||
*/
|
||||
enum mad_func {
|
||||
madd_fp_op = 0x08, msub_fp_op = 0x0a,
|
||||
nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e
|
||||
};
|
||||
|
||||
/*
|
||||
* func field for special3 lx opcodes (Cavium Octeon).
|
||||
*/
|
||||
enum lx_func {
|
||||
lwx_op = 0x00,
|
||||
lhx_op = 0x04,
|
||||
lbux_op = 0x06,
|
||||
ldx_op = 0x08,
|
||||
lwux_op = 0x10,
|
||||
lhux_op = 0x14,
|
||||
lbx_op = 0x16,
|
||||
};
|
||||
|
||||
/*
|
||||
* Damn ... bitfields depend from byteorder :-(
|
||||
*/
|
||||
#ifdef __MIPSEB__
|
||||
#define BITFIELD_FIELD(field, more) \
|
||||
field; \
|
||||
more
|
||||
|
||||
#elif defined(__MIPSEL__)
|
||||
|
||||
#define BITFIELD_FIELD(field, more) \
|
||||
more \
|
||||
field;
|
||||
|
||||
#else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */
|
||||
#error "MIPS but neither __MIPSEL__ nor __MIPSEB__?"
|
||||
#endif
|
||||
|
||||
struct j_format {
|
||||
BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */
|
||||
BITFIELD_FIELD(unsigned int target : 26,
|
||||
;))
|
||||
};
|
||||
|
||||
struct i_format { /* signed immediate format */
|
||||
BITFIELD_FIELD(unsigned int opcode : 6,
|
||||
BITFIELD_FIELD(unsigned int rs : 5,
|
||||
BITFIELD_FIELD(unsigned int rt : 5,
|
||||
BITFIELD_FIELD(signed int simmediate : 16,
|
||||
;))))
|
||||
};
|
||||
|
||||
struct u_format { /* unsigned immediate format */
|
||||
BITFIELD_FIELD(unsigned int opcode : 6,
|
||||
BITFIELD_FIELD(unsigned int rs : 5,
|
||||
BITFIELD_FIELD(unsigned int rt : 5,
|
||||
BITFIELD_FIELD(unsigned int uimmediate : 16,
|
||||
;))))
|
||||
};
|
||||
|
||||
struct c_format { /* Cache (>= R6000) format */
|
||||
BITFIELD_FIELD(unsigned int opcode : 6,
|
||||
BITFIELD_FIELD(unsigned int rs : 5,
|
||||
BITFIELD_FIELD(unsigned int c_op : 3,
|
||||
BITFIELD_FIELD(unsigned int cache : 2,
|
||||
BITFIELD_FIELD(unsigned int simmediate : 16,
|
||||
;)))))
|
||||
};
|
||||
|
||||
struct r_format { /* Register format */
|
||||
BITFIELD_FIELD(unsigned int opcode : 6,
|
||||
BITFIELD_FIELD(unsigned int rs : 5,
|
||||
BITFIELD_FIELD(unsigned int rt : 5,
|
||||
BITFIELD_FIELD(unsigned int rd : 5,
|
||||
BITFIELD_FIELD(unsigned int re : 5,
|
||||
BITFIELD_FIELD(unsigned int func : 6,
|
||||
;))))))
|
||||
};
|
||||
|
||||
struct p_format { /* Performance counter format (R10000) */
|
||||
BITFIELD_FIELD(unsigned int opcode : 6,
|
||||
BITFIELD_FIELD(unsigned int rs : 5,
|
||||
BITFIELD_FIELD(unsigned int rt : 5,
|
||||
BITFIELD_FIELD(unsigned int rd : 5,
|
||||
BITFIELD_FIELD(unsigned int re : 5,
|
||||
BITFIELD_FIELD(unsigned int func : 6,
|
||||
;))))))
|
||||
};
|
||||
|
||||
struct f_format { /* FPU register format */
|
||||
BITFIELD_FIELD(unsigned int opcode : 6,
|
||||
BITFIELD_FIELD(unsigned int : 1,
|
||||
BITFIELD_FIELD(unsigned int fmt : 4,
|
||||
BITFIELD_FIELD(unsigned int rt : 5,
|
||||
BITFIELD_FIELD(unsigned int rd : 5,
|
||||
BITFIELD_FIELD(unsigned int re : 5,
|
||||
BITFIELD_FIELD(unsigned int func : 6,
|
||||
;)))))))
|
||||
};
|
||||
|
||||
struct ma_format { /* FPU multiply and add format (MIPS IV) */
|
||||
BITFIELD_FIELD(unsigned int opcode : 6,
|
||||
BITFIELD_FIELD(unsigned int fr : 5,
|
||||
BITFIELD_FIELD(unsigned int ft : 5,
|
||||
BITFIELD_FIELD(unsigned int fs : 5,
|
||||
BITFIELD_FIELD(unsigned int fd : 5,
|
||||
BITFIELD_FIELD(unsigned int func : 4,
|
||||
BITFIELD_FIELD(unsigned int fmt : 2,
|
||||
;)))))))
|
||||
};
|
||||
|
||||
struct b_format { /* BREAK and SYSCALL */
|
||||
BITFIELD_FIELD(unsigned int opcode : 6,
|
||||
BITFIELD_FIELD(unsigned int code : 20,
|
||||
BITFIELD_FIELD(unsigned int func : 6,
|
||||
;)))
|
||||
};
|
||||
|
||||
struct ps_format { /* MIPS-3D / paired single format */
|
||||
BITFIELD_FIELD(unsigned int opcode : 6,
|
||||
BITFIELD_FIELD(unsigned int rs : 5,
|
||||
BITFIELD_FIELD(unsigned int ft : 5,
|
||||
BITFIELD_FIELD(unsigned int fs : 5,
|
||||
BITFIELD_FIELD(unsigned int fd : 5,
|
||||
BITFIELD_FIELD(unsigned int func : 6,
|
||||
;))))))
|
||||
};
|
||||
|
||||
struct v_format { /* MDMX vector format */
|
||||
BITFIELD_FIELD(unsigned int opcode : 6,
|
||||
BITFIELD_FIELD(unsigned int sel : 4,
|
||||
BITFIELD_FIELD(unsigned int fmt : 1,
|
||||
BITFIELD_FIELD(unsigned int vt : 5,
|
||||
BITFIELD_FIELD(unsigned int vs : 5,
|
||||
BITFIELD_FIELD(unsigned int vd : 5,
|
||||
BITFIELD_FIELD(unsigned int func : 6,
|
||||
;)))))))
|
||||
};
|
||||
|
||||
union mips_instruction {
|
||||
unsigned int word;
|
||||
unsigned short halfword[2];
|
||||
unsigned char byte[4];
|
||||
struct j_format j_format;
|
||||
struct i_format i_format;
|
||||
struct u_format u_format;
|
||||
struct c_format c_format;
|
||||
struct r_format r_format;
|
||||
struct p_format p_format;
|
||||
struct f_format f_format;
|
||||
struct ma_format ma_format;
|
||||
struct b_format b_format;
|
||||
struct ps_format ps_format;
|
||||
struct v_format v_format;
|
||||
};
|
||||
|
||||
#endif /* _UAPI_ASM_INST_H */
|
|
@ -27,6 +27,7 @@ obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o
|
|||
obj-$(CONFIG_CSRC_POWERTV) += csrc-powertv.o
|
||||
obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o
|
||||
obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o
|
||||
obj-$(CONFIG_CSRC_GIC) += csrc-gic.o
|
||||
obj-$(CONFIG_SYNC_R4K) += sync-r4k.o
|
||||
|
||||
obj-$(CONFIG_STACKTRACE) += stacktrace.o
|
||||
|
@ -98,4 +99,35 @@ obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_mipsxx.o
|
|||
|
||||
obj-$(CONFIG_JUMP_LABEL) += jump_label.o
|
||||
|
||||
#
|
||||
# DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only. It is safe
|
||||
# to enable DSP assembler support here even if the MIPS Release 2 CPU we
|
||||
# are targetting does not support DSP because all code-paths making use of
|
||||
# it properly check that the running CPU *actually does* support these
|
||||
# instructions.
|
||||
#
|
||||
ifeq ($(CONFIG_CPU_MIPSR2), y)
|
||||
CFLAGS_DSP = -DHAVE_AS_DSP
|
||||
|
||||
#
|
||||
# Check if assembler supports DSP ASE
|
||||
#
|
||||
ifeq ($(call cc-option-yn,-mdsp), y)
|
||||
CFLAGS_DSP += -mdsp
|
||||
endif
|
||||
|
||||
#
|
||||
# Check if assembler supports DSP ASE Rev2
|
||||
#
|
||||
ifeq ($(call cc-option-yn,-mdspr2), y)
|
||||
CFLAGS_DSP += -mdspr2
|
||||
endif
|
||||
|
||||
CFLAGS_signal.o = $(CFLAGS_DSP)
|
||||
CFLAGS_signal32.o = $(CFLAGS_DSP)
|
||||
CFLAGS_process.o = $(CFLAGS_DSP)
|
||||
CFLAGS_branch.o = $(CFLAGS_DSP)
|
||||
CFLAGS_ptrace.o = $(CFLAGS_DSP)
|
||||
endif
|
||||
|
||||
CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS)
|
||||
|
|
|
@ -201,6 +201,7 @@ void __init check_wait(void)
|
|||
break;
|
||||
|
||||
case CPU_M14KC:
|
||||
case CPU_M14KEC:
|
||||
case CPU_24K:
|
||||
case CPU_34K:
|
||||
case CPU_1004K:
|
||||
|
@ -331,6 +332,34 @@ static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
|
|||
#endif
|
||||
}
|
||||
|
||||
static void __cpuinit set_isa(struct cpuinfo_mips *c, unsigned int isa)
|
||||
{
|
||||
switch (isa) {
|
||||
case MIPS_CPU_ISA_M64R2:
|
||||
c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
|
||||
case MIPS_CPU_ISA_M64R1:
|
||||
c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
|
||||
case MIPS_CPU_ISA_V:
|
||||
c->isa_level |= MIPS_CPU_ISA_V;
|
||||
case MIPS_CPU_ISA_IV:
|
||||
c->isa_level |= MIPS_CPU_ISA_IV;
|
||||
case MIPS_CPU_ISA_III:
|
||||
c->isa_level |= MIPS_CPU_ISA_I | MIPS_CPU_ISA_II |
|
||||
MIPS_CPU_ISA_III;
|
||||
break;
|
||||
|
||||
case MIPS_CPU_ISA_M32R2:
|
||||
c->isa_level |= MIPS_CPU_ISA_M32R2;
|
||||
case MIPS_CPU_ISA_M32R1:
|
||||
c->isa_level |= MIPS_CPU_ISA_M32R1;
|
||||
case MIPS_CPU_ISA_II:
|
||||
c->isa_level |= MIPS_CPU_ISA_II;
|
||||
case MIPS_CPU_ISA_I:
|
||||
c->isa_level |= MIPS_CPU_ISA_I;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static char unknown_isa[] __cpuinitdata = KERN_ERR \
|
||||
"Unsupported ISA type, c0.config0: %d.";
|
||||
|
||||
|
@ -348,10 +377,10 @@ static inline unsigned int decode_config0(struct cpuinfo_mips *c)
|
|||
case 0:
|
||||
switch ((config0 & MIPS_CONF_AR) >> 10) {
|
||||
case 0:
|
||||
c->isa_level = MIPS_CPU_ISA_M32R1;
|
||||
set_isa(c, MIPS_CPU_ISA_M32R1);
|
||||
break;
|
||||
case 1:
|
||||
c->isa_level = MIPS_CPU_ISA_M32R2;
|
||||
set_isa(c, MIPS_CPU_ISA_M32R2);
|
||||
break;
|
||||
default:
|
||||
goto unknown;
|
||||
|
@ -360,10 +389,10 @@ static inline unsigned int decode_config0(struct cpuinfo_mips *c)
|
|||
case 2:
|
||||
switch ((config0 & MIPS_CONF_AR) >> 10) {
|
||||
case 0:
|
||||
c->isa_level = MIPS_CPU_ISA_M64R1;
|
||||
set_isa(c, MIPS_CPU_ISA_M64R1);
|
||||
break;
|
||||
case 1:
|
||||
c->isa_level = MIPS_CPU_ISA_M64R2;
|
||||
set_isa(c, MIPS_CPU_ISA_M64R2);
|
||||
break;
|
||||
default:
|
||||
goto unknown;
|
||||
|
@ -439,6 +468,10 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
|
|||
c->ases |= MIPS_ASE_MIPSMT;
|
||||
if (config3 & MIPS_CONF3_ULRI)
|
||||
c->options |= MIPS_CPU_ULRI;
|
||||
if (config3 & MIPS_CONF3_ISA)
|
||||
c->options |= MIPS_CPU_MICROMIPS;
|
||||
if (config3 & MIPS_CONF3_VZ)
|
||||
c->ases |= MIPS_ASE_VZ;
|
||||
|
||||
return config3 & MIPS_CONF_M;
|
||||
}
|
||||
|
@ -494,7 +527,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
case PRID_IMP_R2000:
|
||||
c->cputype = CPU_R2000;
|
||||
__cpu_name[cpu] = "R2000";
|
||||
c->isa_level = MIPS_CPU_ISA_I;
|
||||
set_isa(c, MIPS_CPU_ISA_I);
|
||||
c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
|
||||
MIPS_CPU_NOFPUEX;
|
||||
if (__cpu_has_fpu())
|
||||
|
@ -514,7 +547,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
c->cputype = CPU_R3000;
|
||||
__cpu_name[cpu] = "R3000";
|
||||
}
|
||||
c->isa_level = MIPS_CPU_ISA_I;
|
||||
set_isa(c, MIPS_CPU_ISA_I);
|
||||
c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
|
||||
MIPS_CPU_NOFPUEX;
|
||||
if (__cpu_has_fpu())
|
||||
|
@ -540,7 +573,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
}
|
||||
}
|
||||
|
||||
c->isa_level = MIPS_CPU_ISA_III;
|
||||
set_isa(c, MIPS_CPU_ISA_III);
|
||||
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
||||
MIPS_CPU_WATCH | MIPS_CPU_VCE |
|
||||
MIPS_CPU_LLSC;
|
||||
|
@ -580,14 +613,14 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
__cpu_name[cpu] = "NEC Vr41xx";
|
||||
break;
|
||||
}
|
||||
c->isa_level = MIPS_CPU_ISA_III;
|
||||
set_isa(c, MIPS_CPU_ISA_III);
|
||||
c->options = R4K_OPTS;
|
||||
c->tlbsize = 32;
|
||||
break;
|
||||
case PRID_IMP_R4300:
|
||||
c->cputype = CPU_R4300;
|
||||
__cpu_name[cpu] = "R4300";
|
||||
c->isa_level = MIPS_CPU_ISA_III;
|
||||
set_isa(c, MIPS_CPU_ISA_III);
|
||||
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
||||
MIPS_CPU_LLSC;
|
||||
c->tlbsize = 32;
|
||||
|
@ -595,7 +628,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
case PRID_IMP_R4600:
|
||||
c->cputype = CPU_R4600;
|
||||
__cpu_name[cpu] = "R4600";
|
||||
c->isa_level = MIPS_CPU_ISA_III;
|
||||
set_isa(c, MIPS_CPU_ISA_III);
|
||||
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
||||
MIPS_CPU_LLSC;
|
||||
c->tlbsize = 48;
|
||||
|
@ -610,13 +643,13 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
*/
|
||||
c->cputype = CPU_R4650;
|
||||
__cpu_name[cpu] = "R4650";
|
||||
c->isa_level = MIPS_CPU_ISA_III;
|
||||
set_isa(c, MIPS_CPU_ISA_III);
|
||||
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
|
||||
c->tlbsize = 48;
|
||||
break;
|
||||
#endif
|
||||
case PRID_IMP_TX39:
|
||||
c->isa_level = MIPS_CPU_ISA_I;
|
||||
set_isa(c, MIPS_CPU_ISA_I);
|
||||
c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
|
||||
|
||||
if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
|
||||
|
@ -641,7 +674,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
case PRID_IMP_R4700:
|
||||
c->cputype = CPU_R4700;
|
||||
__cpu_name[cpu] = "R4700";
|
||||
c->isa_level = MIPS_CPU_ISA_III;
|
||||
set_isa(c, MIPS_CPU_ISA_III);
|
||||
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
||||
MIPS_CPU_LLSC;
|
||||
c->tlbsize = 48;
|
||||
|
@ -649,7 +682,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
case PRID_IMP_TX49:
|
||||
c->cputype = CPU_TX49XX;
|
||||
__cpu_name[cpu] = "R49XX";
|
||||
c->isa_level = MIPS_CPU_ISA_III;
|
||||
set_isa(c, MIPS_CPU_ISA_III);
|
||||
c->options = R4K_OPTS | MIPS_CPU_LLSC;
|
||||
if (!(c->processor_id & 0x08))
|
||||
c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
|
||||
|
@ -658,7 +691,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
case PRID_IMP_R5000:
|
||||
c->cputype = CPU_R5000;
|
||||
__cpu_name[cpu] = "R5000";
|
||||
c->isa_level = MIPS_CPU_ISA_IV;
|
||||
set_isa(c, MIPS_CPU_ISA_IV);
|
||||
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
||||
MIPS_CPU_LLSC;
|
||||
c->tlbsize = 48;
|
||||
|
@ -666,7 +699,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
case PRID_IMP_R5432:
|
||||
c->cputype = CPU_R5432;
|
||||
__cpu_name[cpu] = "R5432";
|
||||
c->isa_level = MIPS_CPU_ISA_IV;
|
||||
set_isa(c, MIPS_CPU_ISA_IV);
|
||||
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
||||
MIPS_CPU_WATCH | MIPS_CPU_LLSC;
|
||||
c->tlbsize = 48;
|
||||
|
@ -674,7 +707,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
case PRID_IMP_R5500:
|
||||
c->cputype = CPU_R5500;
|
||||
__cpu_name[cpu] = "R5500";
|
||||
c->isa_level = MIPS_CPU_ISA_IV;
|
||||
set_isa(c, MIPS_CPU_ISA_IV);
|
||||
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
||||
MIPS_CPU_WATCH | MIPS_CPU_LLSC;
|
||||
c->tlbsize = 48;
|
||||
|
@ -682,7 +715,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
case PRID_IMP_NEVADA:
|
||||
c->cputype = CPU_NEVADA;
|
||||
__cpu_name[cpu] = "Nevada";
|
||||
c->isa_level = MIPS_CPU_ISA_IV;
|
||||
set_isa(c, MIPS_CPU_ISA_IV);
|
||||
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
||||
MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
|
||||
c->tlbsize = 48;
|
||||
|
@ -690,7 +723,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
case PRID_IMP_R6000:
|
||||
c->cputype = CPU_R6000;
|
||||
__cpu_name[cpu] = "R6000";
|
||||
c->isa_level = MIPS_CPU_ISA_II;
|
||||
set_isa(c, MIPS_CPU_ISA_II);
|
||||
c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
|
||||
MIPS_CPU_LLSC;
|
||||
c->tlbsize = 32;
|
||||
|
@ -698,7 +731,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
case PRID_IMP_R6000A:
|
||||
c->cputype = CPU_R6000A;
|
||||
__cpu_name[cpu] = "R6000A";
|
||||
c->isa_level = MIPS_CPU_ISA_II;
|
||||
set_isa(c, MIPS_CPU_ISA_II);
|
||||
c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
|
||||
MIPS_CPU_LLSC;
|
||||
c->tlbsize = 32;
|
||||
|
@ -706,7 +739,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
case PRID_IMP_RM7000:
|
||||
c->cputype = CPU_RM7000;
|
||||
__cpu_name[cpu] = "RM7000";
|
||||
c->isa_level = MIPS_CPU_ISA_IV;
|
||||
set_isa(c, MIPS_CPU_ISA_IV);
|
||||
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
||||
MIPS_CPU_LLSC;
|
||||
/*
|
||||
|
@ -722,7 +755,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
case PRID_IMP_RM9000:
|
||||
c->cputype = CPU_RM9000;
|
||||
__cpu_name[cpu] = "RM9000";
|
||||
c->isa_level = MIPS_CPU_ISA_IV;
|
||||
set_isa(c, MIPS_CPU_ISA_IV);
|
||||
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
||||
MIPS_CPU_LLSC;
|
||||
/*
|
||||
|
@ -737,7 +770,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
case PRID_IMP_R8000:
|
||||
c->cputype = CPU_R8000;
|
||||
__cpu_name[cpu] = "RM8000";
|
||||
c->isa_level = MIPS_CPU_ISA_IV;
|
||||
set_isa(c, MIPS_CPU_ISA_IV);
|
||||
c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
|
||||
MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
||||
MIPS_CPU_LLSC;
|
||||
|
@ -746,7 +779,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
case PRID_IMP_R10000:
|
||||
c->cputype = CPU_R10000;
|
||||
__cpu_name[cpu] = "R10000";
|
||||
c->isa_level = MIPS_CPU_ISA_IV;
|
||||
set_isa(c, MIPS_CPU_ISA_IV);
|
||||
c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
|
||||
MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
||||
MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
|
||||
|
@ -756,7 +789,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
case PRID_IMP_R12000:
|
||||
c->cputype = CPU_R12000;
|
||||
__cpu_name[cpu] = "R12000";
|
||||
c->isa_level = MIPS_CPU_ISA_IV;
|
||||
set_isa(c, MIPS_CPU_ISA_IV);
|
||||
c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
|
||||
MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
||||
MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
|
||||
|
@ -766,7 +799,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
case PRID_IMP_R14000:
|
||||
c->cputype = CPU_R14000;
|
||||
__cpu_name[cpu] = "R14000";
|
||||
c->isa_level = MIPS_CPU_ISA_IV;
|
||||
set_isa(c, MIPS_CPU_ISA_IV);
|
||||
c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
|
||||
MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
||||
MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
|
||||
|
@ -786,7 +819,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
break;
|
||||
}
|
||||
|
||||
c->isa_level = MIPS_CPU_ISA_III;
|
||||
set_isa(c, MIPS_CPU_ISA_III);
|
||||
c->options = R4K_OPTS |
|
||||
MIPS_CPU_FPU | MIPS_CPU_LLSC |
|
||||
MIPS_CPU_32FPR;
|
||||
|
@ -838,10 +871,13 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
__cpu_name[cpu] = "MIPS 20Kc";
|
||||
break;
|
||||
case PRID_IMP_24K:
|
||||
case PRID_IMP_24KE:
|
||||
c->cputype = CPU_24K;
|
||||
__cpu_name[cpu] = "MIPS 24Kc";
|
||||
break;
|
||||
case PRID_IMP_24KE:
|
||||
c->cputype = CPU_24K;
|
||||
__cpu_name[cpu] = "MIPS 24KEc";
|
||||
break;
|
||||
case PRID_IMP_25KF:
|
||||
c->cputype = CPU_25KF;
|
||||
__cpu_name[cpu] = "MIPS 25Kc";
|
||||
|
@ -858,6 +894,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
c->cputype = CPU_M14KC;
|
||||
__cpu_name[cpu] = "MIPS M14Kc";
|
||||
break;
|
||||
case PRID_IMP_M14KEC:
|
||||
c->cputype = CPU_M14KEC;
|
||||
__cpu_name[cpu] = "MIPS M14KEc";
|
||||
break;
|
||||
case PRID_IMP_1004K:
|
||||
c->cputype = CPU_1004K;
|
||||
__cpu_name[cpu] = "MIPS 1004Kc";
|
||||
|
@ -946,7 +986,7 @@ static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
case PRID_IMP_PR4450:
|
||||
c->cputype = CPU_PR4450;
|
||||
__cpu_name[cpu] = "Philips PR4450";
|
||||
c->isa_level = MIPS_CPU_ISA_M32R1;
|
||||
set_isa(c, MIPS_CPU_ISA_M32R1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
@ -1105,12 +1145,12 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
|
|||
}
|
||||
|
||||
if (c->cputype == CPU_XLP) {
|
||||
c->isa_level = MIPS_CPU_ISA_M64R2;
|
||||
set_isa(c, MIPS_CPU_ISA_M64R2);
|
||||
c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
|
||||
/* This will be updated again after all threads are woken up */
|
||||
c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
|
||||
} else {
|
||||
c->isa_level = MIPS_CPU_ISA_M64R1;
|
||||
set_isa(c, MIPS_CPU_ISA_M64R1);
|
||||
c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -107,6 +107,8 @@ static int loongson2_cpufreq_target(struct cpufreq_policy *policy,
|
|||
static int loongson2_cpufreq_cpu_init(struct cpufreq_policy *policy)
|
||||
{
|
||||
int i;
|
||||
unsigned long rate;
|
||||
int ret;
|
||||
|
||||
if (!cpu_online(policy->cpu))
|
||||
return -ENODEV;
|
||||
|
@ -117,15 +119,22 @@ static int loongson2_cpufreq_cpu_init(struct cpufreq_policy *policy)
|
|||
return PTR_ERR(cpuclk);
|
||||
}
|
||||
|
||||
cpuclk->rate = cpu_clock_freq / 1000;
|
||||
if (!cpuclk->rate)
|
||||
rate = cpu_clock_freq / 1000;
|
||||
if (!rate) {
|
||||
clk_put(cpuclk);
|
||||
return -EINVAL;
|
||||
}
|
||||
ret = clk_set_rate(cpuclk, rate);
|
||||
if (ret) {
|
||||
clk_put(cpuclk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* clock table init */
|
||||
for (i = 2;
|
||||
(loongson2_clockmod_table[i].frequency != CPUFREQ_TABLE_END);
|
||||
i++)
|
||||
loongson2_clockmod_table[i].frequency = (cpuclk->rate * i) / 8;
|
||||
loongson2_clockmod_table[i].frequency = (rate * i) / 8;
|
||||
|
||||
policy->cur = loongson2_cpufreq_get(policy->cpu);
|
||||
|
||||
|
|
|
@ -0,0 +1,49 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
|
||||
*/
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
#include <asm/time.h>
|
||||
#include <asm/gic.h>
|
||||
|
||||
static cycle_t gic_hpt_read(struct clocksource *cs)
|
||||
{
|
||||
unsigned int hi, hi2, lo;
|
||||
|
||||
do {
|
||||
GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi);
|
||||
GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), lo);
|
||||
GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi2);
|
||||
} while (hi2 != hi);
|
||||
|
||||
return (((cycle_t) hi) << 32) + lo;
|
||||
}
|
||||
|
||||
static struct clocksource gic_clocksource = {
|
||||
.name = "GIC",
|
||||
.read = gic_hpt_read,
|
||||
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
};
|
||||
|
||||
void __init gic_clocksource_init(unsigned int frequency)
|
||||
{
|
||||
unsigned int config, bits;
|
||||
|
||||
/* Calculate the clocksource mask. */
|
||||
GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), config);
|
||||
bits = 32 + ((config & GIC_SH_CONFIG_COUNTBITS_MSK) >>
|
||||
(GIC_SH_CONFIG_COUNTBITS_SHF - 2));
|
||||
|
||||
/* Set clocksource mask. */
|
||||
gic_clocksource.mask = CLOCKSOURCE_MASK(bits);
|
||||
|
||||
/* Calculate a somewhat reasonable rating value. */
|
||||
gic_clocksource.rating = 200 + frequency / 10000000;
|
||||
|
||||
clocksource_register_hz(&gic_clocksource, frequency);
|
||||
}
|
|
@ -14,8 +14,7 @@
|
|||
|
||||
extern void prom_putchar(char);
|
||||
|
||||
static void __init
|
||||
early_console_write(struct console *con, const char *s, unsigned n)
|
||||
static void early_console_write(struct console *con, const char *s, unsigned n)
|
||||
{
|
||||
while (n-- && *s) {
|
||||
if (*s == '\n')
|
||||
|
@ -25,7 +24,7 @@ early_console_write(struct console *con, const char *s, unsigned n)
|
|||
}
|
||||
}
|
||||
|
||||
static struct console early_console __initdata = {
|
||||
static struct console early_console = {
|
||||
.name = "early",
|
||||
.write = early_console_write,
|
||||
.flags = CON_PRINTBUFFER | CON_BOOT,
|
||||
|
|
|
@ -31,6 +31,7 @@
|
|||
#include <linux/interrupt.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqdomain.h>
|
||||
|
||||
#include <asm/irq_cpu.h>
|
||||
#include <asm/mipsregs.h>
|
||||
|
@ -113,3 +114,44 @@ void __init mips_cpu_irq_init(void)
|
|||
irq_set_chip_and_handler(i, &mips_cpu_irq_controller,
|
||||
handle_percpu_irq);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_IRQ_DOMAIN
|
||||
static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq,
|
||||
irq_hw_number_t hw)
|
||||
{
|
||||
static struct irq_chip *chip;
|
||||
|
||||
if (hw < 2 && cpu_has_mipsmt) {
|
||||
/* Software interrupts are used for MT/CMT IPI */
|
||||
chip = &mips_mt_cpu_irq_controller;
|
||||
} else {
|
||||
chip = &mips_cpu_irq_controller;
|
||||
}
|
||||
|
||||
irq_set_chip_and_handler(irq, chip, handle_percpu_irq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct irq_domain_ops mips_cpu_intc_irq_domain_ops = {
|
||||
.map = mips_cpu_intc_map,
|
||||
.xlate = irq_domain_xlate_onecell,
|
||||
};
|
||||
|
||||
int __init mips_cpu_intc_init(struct device_node *of_node,
|
||||
struct device_node *parent)
|
||||
{
|
||||
struct irq_domain *domain;
|
||||
|
||||
/* Mask interrupts. */
|
||||
clear_c0_status(ST0_IM);
|
||||
clear_c0_cause(CAUSEF_IP);
|
||||
|
||||
domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
|
||||
&mips_cpu_intc_irq_domain_ops, NULL);
|
||||
if (!domain)
|
||||
panic("Failed to add irqdomain for MIPS CPU\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_IRQ_DOMAIN */
|
||||
|
|
|
@ -64,6 +64,28 @@ static int show_cpuinfo(struct seq_file *m, void *v)
|
|||
cpu_data[n].watch_reg_masks[i]);
|
||||
seq_printf(m, "]\n");
|
||||
}
|
||||
if (cpu_has_mips_r) {
|
||||
seq_printf(m, "isa\t\t\t:");
|
||||
if (cpu_has_mips_1)
|
||||
seq_printf(m, "%s", "mips1");
|
||||
if (cpu_has_mips_2)
|
||||
seq_printf(m, "%s", " mips2");
|
||||
if (cpu_has_mips_3)
|
||||
seq_printf(m, "%s", " mips3");
|
||||
if (cpu_has_mips_4)
|
||||
seq_printf(m, "%s", " mips4");
|
||||
if (cpu_has_mips_5)
|
||||
seq_printf(m, "%s", " mips5");
|
||||
if (cpu_has_mips32r1)
|
||||
seq_printf(m, "%s", " mips32r1");
|
||||
if (cpu_has_mips32r2)
|
||||
seq_printf(m, "%s", " mips32r2");
|
||||
if (cpu_has_mips64r1)
|
||||
seq_printf(m, "%s", " mips64r1");
|
||||
if (cpu_has_mips64r2)
|
||||
seq_printf(m, "%s", " mips64r2");
|
||||
seq_printf(m, "\n");
|
||||
}
|
||||
|
||||
seq_printf(m, "ASEs implemented\t:");
|
||||
if (cpu_has_mips16) seq_printf(m, "%s", " mips16");
|
||||
|
@ -73,6 +95,8 @@ static int show_cpuinfo(struct seq_file *m, void *v)
|
|||
if (cpu_has_dsp) seq_printf(m, "%s", " dsp");
|
||||
if (cpu_has_dsp2) seq_printf(m, "%s", " dsp2");
|
||||
if (cpu_has_mipsmt) seq_printf(m, "%s", " mt");
|
||||
if (cpu_has_mmips) seq_printf(m, "%s", " micromips");
|
||||
if (cpu_has_vz) seq_printf(m, "%s", " vz");
|
||||
seq_printf(m, "\n");
|
||||
|
||||
seq_printf(m, "shadow register sets\t: %d\n",
|
||||
|
|
|
@ -480,34 +480,75 @@ static int __init early_parse_mem(char *p)
|
|||
}
|
||||
early_param("mem", early_parse_mem);
|
||||
|
||||
#ifdef CONFIG_PROC_VMCORE
|
||||
unsigned long setup_elfcorehdr, setup_elfcorehdr_size;
|
||||
static int __init early_parse_elfcorehdr(char *p)
|
||||
{
|
||||
int i;
|
||||
|
||||
setup_elfcorehdr = memparse(p, &p);
|
||||
|
||||
for (i = 0; i < boot_mem_map.nr_map; i++) {
|
||||
unsigned long start = boot_mem_map.map[i].addr;
|
||||
unsigned long end = (boot_mem_map.map[i].addr +
|
||||
boot_mem_map.map[i].size);
|
||||
if (setup_elfcorehdr >= start && setup_elfcorehdr < end) {
|
||||
/*
|
||||
* Reserve from the elf core header to the end of
|
||||
* the memory segment, that should all be kdump
|
||||
* reserved memory.
|
||||
*/
|
||||
setup_elfcorehdr_size = end - setup_elfcorehdr;
|
||||
break;
|
||||
}
|
||||
}
|
||||
/*
|
||||
* If we don't find it in the memory map, then we shouldn't
|
||||
* have to worry about it, as the new kernel won't use it.
|
||||
*/
|
||||
return 0;
|
||||
}
|
||||
early_param("elfcorehdr", early_parse_elfcorehdr);
|
||||
#endif
|
||||
|
||||
static void __init arch_mem_addpart(phys_t mem, phys_t end, int type)
|
||||
{
|
||||
phys_t size;
|
||||
int i;
|
||||
|
||||
size = end - mem;
|
||||
if (!size)
|
||||
return;
|
||||
|
||||
/* Make sure it is in the boot_mem_map */
|
||||
for (i = 0; i < boot_mem_map.nr_map; i++) {
|
||||
if (mem >= boot_mem_map.map[i].addr &&
|
||||
mem < (boot_mem_map.map[i].addr +
|
||||
boot_mem_map.map[i].size))
|
||||
return;
|
||||
}
|
||||
add_memory_region(mem, size, type);
|
||||
}
|
||||
|
||||
static void __init arch_mem_init(char **cmdline_p)
|
||||
{
|
||||
phys_t init_mem, init_end, init_size;
|
||||
|
||||
extern void plat_mem_setup(void);
|
||||
|
||||
/* call board setup routine */
|
||||
plat_mem_setup();
|
||||
|
||||
init_mem = PFN_UP(__pa_symbol(&__init_begin)) << PAGE_SHIFT;
|
||||
init_end = PFN_DOWN(__pa_symbol(&__init_end)) << PAGE_SHIFT;
|
||||
init_size = init_end - init_mem;
|
||||
if (init_size) {
|
||||
/* Make sure it is in the boot_mem_map */
|
||||
int i, found;
|
||||
found = 0;
|
||||
for (i = 0; i < boot_mem_map.nr_map; i++) {
|
||||
if (init_mem >= boot_mem_map.map[i].addr &&
|
||||
init_mem < (boot_mem_map.map[i].addr +
|
||||
boot_mem_map.map[i].size)) {
|
||||
found = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!found)
|
||||
add_memory_region(init_mem, init_size,
|
||||
/*
|
||||
* Make sure all kernel memory is in the maps. The "UP" and
|
||||
* "DOWN" are opposite for initdata since if it crosses over
|
||||
* into another memory section you don't want that to be
|
||||
* freed when the initdata is freed.
|
||||
*/
|
||||
arch_mem_addpart(PFN_DOWN(__pa_symbol(&_text)) << PAGE_SHIFT,
|
||||
PFN_UP(__pa_symbol(&_edata)) << PAGE_SHIFT,
|
||||
BOOT_MEM_RAM);
|
||||
arch_mem_addpart(PFN_UP(__pa_symbol(&__init_begin)) << PAGE_SHIFT,
|
||||
PFN_DOWN(__pa_symbol(&__init_end)) << PAGE_SHIFT,
|
||||
BOOT_MEM_INIT_RAM);
|
||||
}
|
||||
|
||||
pr_info("Determined physical RAM map:\n");
|
||||
print_memory_map();
|
||||
|
@ -537,6 +578,14 @@ static void __init arch_mem_init(char **cmdline_p)
|
|||
}
|
||||
|
||||
bootmem_init();
|
||||
#ifdef CONFIG_PROC_VMCORE
|
||||
if (setup_elfcorehdr && setup_elfcorehdr_size) {
|
||||
printk(KERN_INFO "kdump reserved memory at %lx-%lx\n",
|
||||
setup_elfcorehdr, setup_elfcorehdr_size);
|
||||
reserve_bootmem(setup_elfcorehdr, setup_elfcorehdr_size,
|
||||
BOOTMEM_DEFAULT);
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_KEXEC
|
||||
if (crashk_res.start != crashk_res.end)
|
||||
reserve_bootmem(crashk_res.start,
|
||||
|
|
|
@ -41,6 +41,7 @@
|
|||
#include <asm/addrspace.h>
|
||||
#include <asm/smtc.h>
|
||||
#include <asm/smtc_proc.h>
|
||||
#include <asm/setup.h>
|
||||
|
||||
/*
|
||||
* SMTC Kernel needs to manipulate low-level CPU interrupt mask
|
||||
|
|
|
@ -697,18 +697,7 @@ static int vpe_run(struct vpe * v)
|
|||
dmt_flag = dmt();
|
||||
vpeflags = dvpe();
|
||||
|
||||
if (!list_empty(&v->tc)) {
|
||||
if ((t = list_entry(v->tc.next, struct tc, tc)) == NULL) {
|
||||
evpe(vpeflags);
|
||||
emt(dmt_flag);
|
||||
local_irq_restore(flags);
|
||||
|
||||
printk(KERN_WARNING
|
||||
"VPE loader: TC %d is already in use.\n",
|
||||
v->tc->index);
|
||||
return -ENOEXEC;
|
||||
}
|
||||
} else {
|
||||
if (list_empty(&v->tc)) {
|
||||
evpe(vpeflags);
|
||||
emt(dmt_flag);
|
||||
local_irq_restore(flags);
|
||||
|
@ -720,6 +709,8 @@ static int vpe_run(struct vpe * v)
|
|||
return -ENOEXEC;
|
||||
}
|
||||
|
||||
t = list_first_entry(&v->tc, struct tc, tc);
|
||||
|
||||
/* Put MVPE's into 'configuration state' */
|
||||
set_c0_mvpcontrol(MVPCONTROL_VPC);
|
||||
|
||||
|
|
|
@ -26,13 +26,15 @@
|
|||
#include "prom.h"
|
||||
|
||||
/* lantiq socs have 3 static clocks */
|
||||
static struct clk cpu_clk_generic[3];
|
||||
static struct clk cpu_clk_generic[4];
|
||||
|
||||
void clkdev_add_static(unsigned long cpu, unsigned long fpi, unsigned long io)
|
||||
void clkdev_add_static(unsigned long cpu, unsigned long fpi,
|
||||
unsigned long io, unsigned long ppe)
|
||||
{
|
||||
cpu_clk_generic[0].rate = cpu;
|
||||
cpu_clk_generic[1].rate = fpi;
|
||||
cpu_clk_generic[2].rate = io;
|
||||
cpu_clk_generic[3].rate = ppe;
|
||||
}
|
||||
|
||||
struct clk *clk_get_cpu(void)
|
||||
|
@ -51,6 +53,12 @@ struct clk *clk_get_io(void)
|
|||
return &cpu_clk_generic[2];
|
||||
}
|
||||
|
||||
struct clk *clk_get_ppe(void)
|
||||
{
|
||||
return &cpu_clk_generic[3];
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_get_ppe);
|
||||
|
||||
static inline int clk_good(struct clk *clk)
|
||||
{
|
||||
return clk && !IS_ERR(clk);
|
||||
|
|
|
@ -27,12 +27,15 @@
|
|||
#define CLOCK_167M 166666667
|
||||
#define CLOCK_196_608M 196608000
|
||||
#define CLOCK_200M 200000000
|
||||
#define CLOCK_222M 222000000
|
||||
#define CLOCK_240M 240000000
|
||||
#define CLOCK_250M 250000000
|
||||
#define CLOCK_266M 266666666
|
||||
#define CLOCK_300M 300000000
|
||||
#define CLOCK_333M 333333333
|
||||
#define CLOCK_393M 393215332
|
||||
#define CLOCK_400M 400000000
|
||||
#define CLOCK_450M 450000000
|
||||
#define CLOCK_500M 500000000
|
||||
#define CLOCK_600M 600000000
|
||||
|
||||
|
@ -64,15 +67,17 @@ struct clk {
|
|||
};
|
||||
|
||||
extern void clkdev_add_static(unsigned long cpu, unsigned long fpi,
|
||||
unsigned long io);
|
||||
unsigned long io, unsigned long ppe);
|
||||
|
||||
extern unsigned long ltq_danube_cpu_hz(void);
|
||||
extern unsigned long ltq_danube_fpi_hz(void);
|
||||
extern unsigned long ltq_danube_pp32_hz(void);
|
||||
|
||||
extern unsigned long ltq_ar9_cpu_hz(void);
|
||||
extern unsigned long ltq_ar9_fpi_hz(void);
|
||||
|
||||
extern unsigned long ltq_vr9_cpu_hz(void);
|
||||
extern unsigned long ltq_vr9_fpi_hz(void);
|
||||
extern unsigned long ltq_vr9_pp32_hz(void);
|
||||
|
||||
#endif
|
||||
|
|
|
@ -241,9 +241,9 @@ void __init ltq_soc_init(void)
|
|||
|
||||
/* get our 3 static rates for cpu, fpi and io clocks */
|
||||
if (ltq_sys1_r32(SYS1_CPU0CC) & CPU0CC_CPUDIV)
|
||||
clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M);
|
||||
clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M, 0);
|
||||
else
|
||||
clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M);
|
||||
clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M, 0);
|
||||
|
||||
/* add our clock domains */
|
||||
clkdev_add_sys("1d810000.gpio", SYSCTL_SYSETH, ACTS_P0);
|
||||
|
|
|
@ -33,17 +33,10 @@
|
|||
/* register definitions - external irqs */
|
||||
#define LTQ_EIU_EXIN_C 0x0000
|
||||
#define LTQ_EIU_EXIN_INIC 0x0004
|
||||
#define LTQ_EIU_EXIN_INC 0x0008
|
||||
#define LTQ_EIU_EXIN_INEN 0x000C
|
||||
|
||||
/* irq numbers used by the external interrupt unit (EIU) */
|
||||
#define LTQ_EIU_IR0 (INT_NUM_IM4_IRL0 + 30)
|
||||
#define LTQ_EIU_IR1 (INT_NUM_IM3_IRL0 + 31)
|
||||
#define LTQ_EIU_IR2 (INT_NUM_IM1_IRL0 + 26)
|
||||
#define LTQ_EIU_IR3 INT_NUM_IM1_IRL0
|
||||
#define LTQ_EIU_IR4 (INT_NUM_IM1_IRL0 + 1)
|
||||
#define LTQ_EIU_IR5 (INT_NUM_IM1_IRL0 + 2)
|
||||
#define LTQ_EIU_IR6 (INT_NUM_IM2_IRL0 + 30)
|
||||
#define XWAY_EXIN_COUNT 3
|
||||
/* number of external interrupts */
|
||||
#define MAX_EIU 6
|
||||
|
||||
/* the performance counter */
|
||||
|
@ -72,20 +65,19 @@
|
|||
int gic_present;
|
||||
#endif
|
||||
|
||||
static unsigned short ltq_eiu_irq[MAX_EIU] = {
|
||||
LTQ_EIU_IR0,
|
||||
LTQ_EIU_IR1,
|
||||
LTQ_EIU_IR2,
|
||||
LTQ_EIU_IR3,
|
||||
LTQ_EIU_IR4,
|
||||
LTQ_EIU_IR5,
|
||||
};
|
||||
|
||||
static int exin_avail;
|
||||
static struct resource ltq_eiu_irq[MAX_EIU];
|
||||
static void __iomem *ltq_icu_membase[MAX_IM];
|
||||
static void __iomem *ltq_eiu_membase;
|
||||
static struct irq_domain *ltq_domain;
|
||||
|
||||
int ltq_eiu_get_irq(int exin)
|
||||
{
|
||||
if (exin < exin_avail)
|
||||
return ltq_eiu_irq[exin].start;
|
||||
return -1;
|
||||
}
|
||||
|
||||
void ltq_disable_irq(struct irq_data *d)
|
||||
{
|
||||
u32 ier = LTQ_ICU_IM0_IER;
|
||||
|
@ -128,19 +120,65 @@ void ltq_enable_irq(struct irq_data *d)
|
|||
ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier);
|
||||
}
|
||||
|
||||
static int ltq_eiu_settype(struct irq_data *d, unsigned int type)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < MAX_EIU; i++) {
|
||||
if (d->hwirq == ltq_eiu_irq[i].start) {
|
||||
int val = 0;
|
||||
int edge = 0;
|
||||
|
||||
switch (type) {
|
||||
case IRQF_TRIGGER_NONE:
|
||||
break;
|
||||
case IRQF_TRIGGER_RISING:
|
||||
val = 1;
|
||||
edge = 1;
|
||||
break;
|
||||
case IRQF_TRIGGER_FALLING:
|
||||
val = 2;
|
||||
edge = 1;
|
||||
break;
|
||||
case IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING:
|
||||
val = 3;
|
||||
edge = 1;
|
||||
break;
|
||||
case IRQF_TRIGGER_HIGH:
|
||||
val = 5;
|
||||
break;
|
||||
case IRQF_TRIGGER_LOW:
|
||||
val = 6;
|
||||
break;
|
||||
default:
|
||||
pr_err("invalid type %d for irq %ld\n",
|
||||
type, d->hwirq);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (edge)
|
||||
irq_set_handler(d->hwirq, handle_edge_irq);
|
||||
|
||||
ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) |
|
||||
(val << (i * 4)), LTQ_EIU_EXIN_C);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
|
||||
{
|
||||
int i;
|
||||
|
||||
ltq_enable_irq(d);
|
||||
for (i = 0; i < MAX_EIU; i++) {
|
||||
if (d->hwirq == ltq_eiu_irq[i]) {
|
||||
/* low level - we should really handle set_type */
|
||||
ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) |
|
||||
(0x6 << (i * 4)), LTQ_EIU_EXIN_C);
|
||||
if (d->hwirq == ltq_eiu_irq[i].start) {
|
||||
/* by default we are low level triggered */
|
||||
ltq_eiu_settype(d, IRQF_TRIGGER_LOW);
|
||||
/* clear all pending */
|
||||
ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INIC) & ~BIT(i),
|
||||
LTQ_EIU_EXIN_INIC);
|
||||
ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INC) & ~BIT(i),
|
||||
LTQ_EIU_EXIN_INC);
|
||||
/* enable */
|
||||
ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | BIT(i),
|
||||
LTQ_EIU_EXIN_INEN);
|
||||
|
@ -157,7 +195,7 @@ static void ltq_shutdown_eiu_irq(struct irq_data *d)
|
|||
|
||||
ltq_disable_irq(d);
|
||||
for (i = 0; i < MAX_EIU; i++) {
|
||||
if (d->hwirq == ltq_eiu_irq[i]) {
|
||||
if (d->hwirq == ltq_eiu_irq[i].start) {
|
||||
/* disable */
|
||||
ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i),
|
||||
LTQ_EIU_EXIN_INEN);
|
||||
|
@ -186,6 +224,7 @@ static struct irq_chip ltq_eiu_type = {
|
|||
.irq_ack = ltq_ack_irq,
|
||||
.irq_mask = ltq_disable_irq,
|
||||
.irq_mask_ack = ltq_mask_and_ack_irq,
|
||||
.irq_set_type = ltq_eiu_settype,
|
||||
};
|
||||
|
||||
static void ltq_hw_irqdispatch(int module)
|
||||
|
@ -301,7 +340,7 @@ static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
|
|||
return 0;
|
||||
|
||||
for (i = 0; i < exin_avail; i++)
|
||||
if (hw == ltq_eiu_irq[i])
|
||||
if (hw == ltq_eiu_irq[i].start)
|
||||
chip = <q_eiu_type;
|
||||
|
||||
irq_set_chip_and_handler(hw, chip, handle_level_irq);
|
||||
|
@ -323,7 +362,7 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
|
|||
{
|
||||
struct device_node *eiu_node;
|
||||
struct resource res;
|
||||
int i;
|
||||
int i, ret;
|
||||
|
||||
for (i = 0; i < MAX_IM; i++) {
|
||||
if (of_address_to_resource(node, i, &res))
|
||||
|
@ -340,17 +379,19 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
|
|||
}
|
||||
|
||||
/* the external interrupts are optional and xway only */
|
||||
eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu");
|
||||
eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway");
|
||||
if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
|
||||
/* find out how many external irq sources we have */
|
||||
const __be32 *count = of_get_property(node,
|
||||
"lantiq,count", NULL);
|
||||
exin_avail = of_irq_count(eiu_node);
|
||||
|
||||
if (count)
|
||||
exin_avail = *count;
|
||||
if (exin_avail > MAX_EIU)
|
||||
exin_avail = MAX_EIU;
|
||||
|
||||
ret = of_irq_to_resource_table(eiu_node,
|
||||
ltq_eiu_irq, exin_avail);
|
||||
if (ret != exin_avail)
|
||||
panic("failed to load external irq resources\n");
|
||||
|
||||
if (request_mem_region(res.start, resource_size(&res),
|
||||
res.name) < 0)
|
||||
pr_err("Failed to request eiu memory");
|
||||
|
|
|
@ -53,6 +53,29 @@ unsigned long ltq_danube_cpu_hz(void)
|
|||
}
|
||||
}
|
||||
|
||||
unsigned long ltq_danube_pp32_hz(void)
|
||||
{
|
||||
unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 7) & 3;
|
||||
unsigned long clk;
|
||||
|
||||
switch (clksys) {
|
||||
case 1:
|
||||
clk = CLOCK_240M;
|
||||
break;
|
||||
case 2:
|
||||
clk = CLOCK_222M;
|
||||
break;
|
||||
case 3:
|
||||
clk = CLOCK_133M;
|
||||
break;
|
||||
default:
|
||||
clk = CLOCK_266M;
|
||||
break;
|
||||
}
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
unsigned long ltq_ar9_sys_hz(void)
|
||||
{
|
||||
if (((ltq_cgu_r32(CGU_SYS) >> 3) & 0x3) == 0x2)
|
||||
|
@ -149,3 +172,23 @@ unsigned long ltq_vr9_fpi_hz(void)
|
|||
|
||||
return clk;
|
||||
}
|
||||
|
||||
unsigned long ltq_vr9_pp32_hz(void)
|
||||
{
|
||||
unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 16) & 3;
|
||||
unsigned long clk;
|
||||
|
||||
switch (clksys) {
|
||||
case 1:
|
||||
clk = CLOCK_450M;
|
||||
break;
|
||||
case 2:
|
||||
clk = CLOCK_300M;
|
||||
break;
|
||||
default:
|
||||
clk = CLOCK_500M;
|
||||
break;
|
||||
}
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
|
|
@ -78,10 +78,19 @@ static struct ltq_xrx200_gphy_reset {
|
|||
/* reset and boot a gphy. these phys only exist on xrx200 SoC */
|
||||
int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr)
|
||||
{
|
||||
struct clk *clk;
|
||||
|
||||
if (!of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200")) {
|
||||
dev_err(dev, "this SoC has no GPHY\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
clk = clk_get_sys("1f203000.rcu", "gphy");
|
||||
if (IS_ERR(clk))
|
||||
return PTR_ERR(clk);
|
||||
|
||||
clk_enable(clk);
|
||||
|
||||
if (id > 1) {
|
||||
dev_err(dev, "%u is an invalid gphy id\n", id);
|
||||
return -EINVAL;
|
||||
|
|
|
@ -305,7 +305,7 @@ void __init ltq_soc_init(void)
|
|||
|
||||
/* check if all the core register ranges are available */
|
||||
if (!np_pmu || !np_cgu || !np_ebu)
|
||||
panic("Failed to load core nodess from devicetree");
|
||||
panic("Failed to load core nodes from devicetree");
|
||||
|
||||
if (of_address_to_resource(np_pmu, 0, &res_pmu) ||
|
||||
of_address_to_resource(np_cgu, 0, &res_cgu) ||
|
||||
|
@ -356,14 +356,16 @@ void __init ltq_soc_init(void)
|
|||
|
||||
if (of_machine_is_compatible("lantiq,ase")) {
|
||||
if (ltq_cgu_r32(CGU_SYS) & (1 << 5))
|
||||
clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M);
|
||||
clkdev_add_static(CLOCK_266M, CLOCK_133M,
|
||||
CLOCK_133M, CLOCK_266M);
|
||||
else
|
||||
clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M);
|
||||
clkdev_add_static(CLOCK_133M, CLOCK_133M,
|
||||
CLOCK_133M, CLOCK_133M);
|
||||
clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY),
|
||||
clkdev_add_pmu("1e180000.etop", "ephy", 0, PMU_EPHY);
|
||||
} else if (of_machine_is_compatible("lantiq,vr9")) {
|
||||
clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
|
||||
ltq_vr9_fpi_hz());
|
||||
ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
|
||||
clkdev_add_pmu("1d900000.pcie", "phy", 1, PMU1_PCIE_PHY);
|
||||
clkdev_add_pmu("1d900000.pcie", "bus", 0, PMU_PCIE_CLK);
|
||||
clkdev_add_pmu("1d900000.pcie", "msi", 1, PMU1_PCIE_MSI);
|
||||
|
@ -374,12 +376,13 @@ void __init ltq_soc_init(void)
|
|||
PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
|
||||
PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
|
||||
PMU_PPE_QSB | PMU_PPE_TOP);
|
||||
clkdev_add_pmu("1f203000.rcu", "gphy", 0, PMU_GPHY);
|
||||
} else if (of_machine_is_compatible("lantiq,ar9")) {
|
||||
clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
|
||||
ltq_ar9_fpi_hz());
|
||||
ltq_ar9_fpi_hz(), CLOCK_250M);
|
||||
clkdev_add_pmu("1e180000.etop", "switch", 0, PMU_SWITCH);
|
||||
} else {
|
||||
clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
|
||||
ltq_danube_fpi_hz());
|
||||
ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
|
||||
}
|
||||
}
|
||||
|
|
|
@ -73,7 +73,7 @@ void __init prom_free_prom_memory(void)
|
|||
|
||||
#define PORT(offset) (u8 *)(KSEG1ADDR(LS1X_UART0_BASE + offset))
|
||||
|
||||
void __init prom_putchar(char c)
|
||||
void prom_putchar(char c)
|
||||
{
|
||||
int timeout;
|
||||
|
||||
|
|
|
@ -9,4 +9,3 @@ obj-y := cp1emu.o ieee754m.o ieee754d.o ieee754dp.o ieee754sp.o ieee754.o \
|
|||
sp_div.o sp_mul.o sp_sub.o sp_add.o sp_fdp.o sp_cmp.o sp_logb.o \
|
||||
sp_scalb.o sp_simple.o sp_tint.o sp_fint.o sp_tlong.o sp_flong.o \
|
||||
dp_sqrt.o sp_sqrt.o kernel_linkage.o dsemul.o
|
||||
|
||||
|
|
|
@ -1057,6 +1057,7 @@ static void __cpuinit probe_pcache(void)
|
|||
break;
|
||||
|
||||
case CPU_M14KC:
|
||||
case CPU_M14KEC:
|
||||
case CPU_24K:
|
||||
case CPU_34K:
|
||||
case CPU_74K:
|
||||
|
|
|
@ -581,6 +581,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
|
|||
case CPU_4KC:
|
||||
case CPU_4KEC:
|
||||
case CPU_M14KC:
|
||||
case CPU_M14KEC:
|
||||
case CPU_SB1:
|
||||
case CPU_SB1A:
|
||||
case CPU_4KSC:
|
||||
|
|
|
@ -17,7 +17,6 @@
|
|||
*
|
||||
* Setting up the clock on the MIPS boards.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/i8253.h>
|
||||
#include <linux/init.h>
|
||||
|
@ -25,7 +24,6 @@
|
|||
#include <linux/sched.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/time.h>
|
||||
#include <linux/timex.h>
|
||||
#include <linux/mc146818rtc.h>
|
||||
|
||||
|
@ -34,11 +32,11 @@
|
|||
#include <asm/hardirq.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/div64.h>
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/setup.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/mc146818-time.h>
|
||||
#include <asm/msc01_ic.h>
|
||||
#include <asm/gic.h>
|
||||
|
||||
#include <asm/mips-boards/generic.h>
|
||||
#include <asm/mips-boards/prom.h>
|
||||
|
@ -46,6 +44,7 @@
|
|||
#include <asm/mips-boards/maltaint.h>
|
||||
|
||||
unsigned long cpu_khz;
|
||||
int gic_frequency;
|
||||
|
||||
static int mips_cpu_timer_irq;
|
||||
static int mips_cpu_perf_irq;
|
||||
|
@ -61,44 +60,50 @@ static void mips_perf_dispatch(void)
|
|||
do_IRQ(mips_cpu_perf_irq);
|
||||
}
|
||||
|
||||
/*
|
||||
* Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
|
||||
*/
|
||||
static unsigned int __init estimate_cpu_frequency(void)
|
||||
static unsigned int freqround(unsigned int freq, unsigned int amount)
|
||||
{
|
||||
unsigned int prid = read_c0_prid() & 0xffff00;
|
||||
unsigned int count;
|
||||
freq += amount;
|
||||
freq -= freq % (amount*2);
|
||||
return freq;
|
||||
}
|
||||
|
||||
/*
|
||||
* Estimate CPU and GIC frequencies.
|
||||
*/
|
||||
static void __init estimate_frequencies(void)
|
||||
{
|
||||
unsigned long flags;
|
||||
unsigned int start;
|
||||
unsigned int count, start;
|
||||
unsigned int giccount = 0, gicstart = 0;
|
||||
|
||||
local_irq_save(flags);
|
||||
|
||||
/* Start counter exactly on falling edge of update flag */
|
||||
/* Start counter exactly on falling edge of update flag. */
|
||||
while (CMOS_READ(RTC_REG_A) & RTC_UIP);
|
||||
while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
|
||||
|
||||
/* Start r4k counter. */
|
||||
/* Initialize counters. */
|
||||
start = read_c0_count();
|
||||
if (gic_present)
|
||||
GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), gicstart);
|
||||
|
||||
/* Read counter exactly on falling edge of update flag */
|
||||
/* Read counter exactly on falling edge of update flag. */
|
||||
while (CMOS_READ(RTC_REG_A) & RTC_UIP);
|
||||
while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
|
||||
|
||||
count = read_c0_count() - start;
|
||||
count = read_c0_count();
|
||||
if (gic_present)
|
||||
GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), giccount);
|
||||
|
||||
/* restore interrupts */
|
||||
local_irq_restore(flags);
|
||||
|
||||
count -= start;
|
||||
if (gic_present)
|
||||
giccount -= gicstart;
|
||||
|
||||
mips_hpt_frequency = count;
|
||||
if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
|
||||
(prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
|
||||
count *= 2;
|
||||
|
||||
count += 5000; /* round */
|
||||
count -= count%10000;
|
||||
|
||||
return count;
|
||||
if (gic_present)
|
||||
gic_frequency = giccount;
|
||||
}
|
||||
|
||||
void read_persistent_clock(struct timespec *ts)
|
||||
|
@ -144,22 +149,34 @@ unsigned int __cpuinit get_c0_compare_int(void)
|
|||
|
||||
void __init plat_time_init(void)
|
||||
{
|
||||
unsigned int est_freq;
|
||||
unsigned int prid = read_c0_prid() & 0xffff00;
|
||||
unsigned int freq;
|
||||
|
||||
/* Set Data mode - binary. */
|
||||
CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
|
||||
estimate_frequencies();
|
||||
|
||||
est_freq = estimate_cpu_frequency();
|
||||
freq = mips_hpt_frequency;
|
||||
if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
|
||||
(prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
|
||||
freq *= 2;
|
||||
freq = freqround(freq, 5000);
|
||||
pr_debug("CPU frequency %d.%02d MHz\n", freq/1000000,
|
||||
(freq%1000000)*100/1000000);
|
||||
cpu_khz = freq / 1000;
|
||||
|
||||
printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
|
||||
(est_freq%1000000)*100/1000000);
|
||||
if (gic_present) {
|
||||
freq = freqround(gic_frequency, 5000);
|
||||
pr_debug("GIC frequency %d.%02d MHz\n", freq/1000000,
|
||||
(freq%1000000)*100/1000000);
|
||||
gic_clocksource_init(gic_frequency);
|
||||
} else
|
||||
init_r4k_clocksource();
|
||||
|
||||
cpu_khz = est_freq / 1000;
|
||||
|
||||
mips_scroll_message();
|
||||
#ifdef CONFIG_I8253 /* Only Malta has a PIT */
|
||||
#ifdef CONFIG_I8253
|
||||
/* Only Malta has a PIT. */
|
||||
setup_pit_timer();
|
||||
#endif
|
||||
|
||||
mips_scroll_message();
|
||||
|
||||
plat_perf_setup();
|
||||
}
|
||||
|
|
|
@ -5,10 +5,12 @@
|
|||
# Copyright (C) 2008 Wind River Systems, Inc.
|
||||
# written by Ralf Baechle <ralf@linux-mips.org>
|
||||
#
|
||||
# Copyright (C) 2012 MIPS Technoligies, Inc. All rights reserved.
|
||||
# Steven J. Hill <sjhill@mips.com>
|
||||
#
|
||||
obj-y := sead3-lcd.o sead3-cmdline.o \
|
||||
sead3-display.o sead3-init.o sead3-int.o \
|
||||
sead3-mtd.o sead3-net.o \
|
||||
sead3-memory.o sead3-platform.o \
|
||||
sead3-mtd.o sead3-net.o sead3-platform.o \
|
||||
sead3-reset.o sead3-setup.o sead3-time.o
|
||||
|
||||
obj-y += sead3-i2c-dev.o sead3-i2c.o \
|
||||
|
@ -17,3 +19,7 @@ obj-y += sead3-i2c-dev.o sead3-i2c.o \
|
|||
|
||||
obj-$(CONFIG_EARLY_PRINTK) += sead3-console.o
|
||||
obj-$(CONFIG_USB_EHCI_HCD) += sead3-ehci.o
|
||||
obj-$(CONFIG_OF) += sead3.dtb.o
|
||||
|
||||
$(obj)/%.dtb: $(obj)/%.dts
|
||||
$(call if_changed,dtc)
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue