myri10ge: update firmware headers
Update myri10ge firmware headers to latest upstream version with TSO6 and RSS support. Signed-off-by: Brice Goglin <brice@myri.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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@ -10,7 +10,7 @@ struct mcp_dma_addr {
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__be32 low;
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};
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/* 4 Bytes */
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/* 4 Bytes. 8 Bytes for NDIS drivers. */
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struct mcp_slot {
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__sum16 checksum;
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__be16 length;
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@ -205,8 +205,87 @@ enum myri10ge_mcp_cmd_type {
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/* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned
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* chipset */
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MXGEFW_CMD_UNALIGNED_STATUS
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/* return data = boolean, true if the chipset is known to be unaligned */
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MXGEFW_CMD_UNALIGNED_STATUS,
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/* return data = boolean, true if the chipset is known to be unaligned */
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MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS,
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/* data0 = number of big buffers to use. It must be 0 or a power of 2.
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* 0 indicates that the NIC consumes as many buffers as they are required
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* for packet. This is the default behavior.
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* A power of 2 number indicates that the NIC always uses the specified
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* number of buffers for each big receive packet.
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* It is up to the driver to ensure that this value is big enough for
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* the NIC to be able to receive maximum-sized packets.
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*/
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MXGEFW_CMD_GET_MAX_RSS_QUEUES,
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MXGEFW_CMD_ENABLE_RSS_QUEUES,
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/* data0 = number of slices n (0, 1, ..., n-1) to enable
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* data1 = interrupt mode. 0=share one INTx/MSI, 1=use one MSI-X per queue.
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* If all queues share one interrupt, the driver must have set
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* RSS_SHARED_INTERRUPT_DMA before enabling queues.
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*/
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MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET,
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MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA,
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/* data0, data1 = bus address lsw, msw */
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MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
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/* get the offset of the indirection table */
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MXGEFW_CMD_SET_RSS_TABLE_SIZE,
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/* set the size of the indirection table */
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MXGEFW_CMD_GET_RSS_KEY_OFFSET,
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/* get the offset of the secret key */
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MXGEFW_CMD_RSS_KEY_UPDATED,
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/* tell nic that the secret key's been updated */
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MXGEFW_CMD_SET_RSS_ENABLE,
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/* data0 = enable/disable rss
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* 0: disable rss. nic does not distribute receive packets.
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* 1: enable rss. nic distributes receive packets among queues.
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* data1 = hash type
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* 1: IPV4
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* 2: TCP_IPV4
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* 3: IPV4 | TCP_IPV4
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*/
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MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
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/* Return data = the max. size of the entire headers of a IPv6 TSO packet.
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* If the header size of a IPv6 TSO packet is larger than the specified
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* value, then the driver must not use TSO.
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* This size restriction only applies to IPv6 TSO.
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* For IPv4 TSO, the maximum size of the headers is fixed, and the NIC
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* always has enough header buffer to store maximum-sized headers.
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*/
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MXGEFW_CMD_SET_TSO_MODE,
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/* data0 = TSO mode.
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* 0: Linux/FreeBSD style (NIC default)
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* 1: NDIS/NetBSD style
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*/
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MXGEFW_CMD_MDIO_READ,
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/* data0 = dev_addr (PMA/PMD or PCS ...), data1 = register/addr */
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MXGEFW_CMD_MDIO_WRITE,
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/* data0 = dev_addr, data1 = register/addr, data2 = value */
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MXGEFW_CMD_XFP_I2C_READ,
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/* Starts to get a fresh copy of one byte or of the whole xfp i2c table, the
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* obtained data is cached inside the xaui-xfi chip :
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* data0 : "all" flag : 0 => get one byte, 1=> get 256 bytes,
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* data1 : if (data0 == 0): index of byte to refresh [ not used otherwise ]
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* The operation might take ~1ms for a single byte or ~65ms when refreshing all 256 bytes
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* During the i2c operation, MXGEFW_CMD_XFP_I2C_READ or MXGEFW_CMD_XFP_BYTE attempts
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* will return MXGEFW_CMD_ERROR_BUSY
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*/
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MXGEFW_CMD_XFP_BYTE,
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/* Return the last obtained copy of a given byte in the xfp i2c table
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* (copy cached during the last relevant MXGEFW_CMD_XFP_I2C_READ)
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* data0 : index of the desired table entry
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* Return data = the byte stored at the requested index in the table
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*/
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MXGEFW_CMD_GET_VPUMP_OFFSET,
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/* Return data = NIC memory offset of mcp_vpump_public_global */
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MXGEFW_CMD_RESET_VPUMP,
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/* Resets the VPUMP state */
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};
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enum myri10ge_mcp_cmd_status {
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@ -220,7 +299,10 @@ enum myri10ge_mcp_cmd_status {
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MXGEFW_CMD_ERROR_BAD_PORT,
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MXGEFW_CMD_ERROR_RESOURCES,
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MXGEFW_CMD_ERROR_MULTICAST,
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MXGEFW_CMD_ERROR_UNALIGNED
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MXGEFW_CMD_ERROR_UNALIGNED,
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MXGEFW_CMD_ERROR_NO_MDIO,
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MXGEFW_CMD_ERROR_XFP_FAILURE,
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MXGEFW_CMD_ERROR_XFP_ABSENT
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};
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#define MXGEFW_OLD_IRQ_DATA_LEN 40
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