pinctrl: sh-pfc: r8a77470: Add SDHI support
Add SH_PFC_PIN_CFG_IO_VOLTAGE definition for the SDHI pins capable of switching voltage, also add pin groups and functions for SDHI0 and SDHI1. Please note that with the RZ/G1C only 1 bit of the POC Control Register is used to control each interface. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Fabrizio Castro
Geert Uytterhoeven
parent
06bfbe089b
commit
b06a8b4387
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@ -10,14 +10,45 @@
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#include "sh_pfc.h"
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#define CPU_ALL_PORT(fn, sfx) \
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PORT_GP_23(0, fn, sfx), \
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PORT_GP_4(0, fn, sfx), \
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PORT_GP_1(0, 4, fn, sfx), \
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PORT_GP_CFG_1(0, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_CFG_1(0, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_CFG_1(0, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_CFG_1(0, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_CFG_1(0, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_CFG_1(0, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_1(0, 11, fn, sfx), \
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PORT_GP_1(0, 12, fn, sfx), \
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PORT_GP_CFG_1(0, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_CFG_1(0, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_CFG_1(0, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_CFG_1(0, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_CFG_1(0, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_CFG_1(0, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_CFG_1(0, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_CFG_1(0, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_CFG_1(0, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_CFG_1(0, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_23(1, fn, sfx), \
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PORT_GP_32(2, fn, sfx), \
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PORT_GP_17(3, fn, sfx), \
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PORT_GP_1(3, 27, fn, sfx), \
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PORT_GP_1(3, 28, fn, sfx), \
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PORT_GP_1(3, 29, fn, sfx), \
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PORT_GP_26(4, fn, sfx), \
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PORT_GP_14(4, fn, sfx), \
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PORT_GP_CFG_1(4, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_CFG_1(4, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_CFG_1(4, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_CFG_1(4, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_CFG_1(4, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_CFG_1(4, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_1(4, 20, fn, sfx), \
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PORT_GP_1(4, 21, fn, sfx), \
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PORT_GP_1(4, 22, fn, sfx), \
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PORT_GP_1(4, 23, fn, sfx), \
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PORT_GP_1(4, 24, fn, sfx), \
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PORT_GP_1(4, 25, fn, sfx), \
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PORT_GP_32(5, fn, sfx)
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enum {
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@ -1865,6 +1896,81 @@ static const unsigned int scif_clk_b_pins[] = {
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static const unsigned int scif_clk_b_mux[] = {
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SCIF_CLK_B_MARK,
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};
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/* - SDHI0 ------------------------------------------------------------------ */
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static const unsigned int sdhi0_data1_pins[] = {
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/* D0 */
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RCAR_GP_PIN(0, 7),
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};
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static const unsigned int sdhi0_data1_mux[] = {
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SD0_DAT0_MARK,
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};
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static const unsigned int sdhi0_data4_pins[] = {
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/* D[0:3] */
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RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
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RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
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};
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static const unsigned int sdhi0_data4_mux[] = {
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SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
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};
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static const unsigned int sdhi0_ctrl_pins[] = {
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/* CLK, CMD */
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RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
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};
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static const unsigned int sdhi0_ctrl_mux[] = {
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SD0_CLK_MARK, SD0_CMD_MARK,
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};
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static const unsigned int sdhi0_cd_pins[] = {
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/* CD */
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RCAR_GP_PIN(0, 11),
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};
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static const unsigned int sdhi0_cd_mux[] = {
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SD0_CD_MARK,
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};
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static const unsigned int sdhi0_wp_pins[] = {
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/* WP */
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RCAR_GP_PIN(0, 12),
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};
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static const unsigned int sdhi0_wp_mux[] = {
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SD0_WP_MARK,
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};
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/* - SDHI1 ------------------------------------------------------------------ */
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static const unsigned int sdhi1_data1_pins[] = {
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/* D0 */
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RCAR_GP_PIN(0, 15),
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};
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static const unsigned int sdhi1_data1_mux[] = {
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MMC0_D0_SDHI1_D0_MARK,
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};
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static const unsigned int sdhi1_data4_pins[] = {
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/* D[0:3] */
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RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
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RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
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};
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static const unsigned int sdhi1_data4_mux[] = {
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MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
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MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
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};
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static const unsigned int sdhi1_ctrl_pins[] = {
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/* CLK, CMD */
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RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
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};
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static const unsigned int sdhi1_ctrl_mux[] = {
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MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK,
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};
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static const unsigned int sdhi1_cd_pins[] = {
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/* CD */
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RCAR_GP_PIN(0, 19),
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};
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static const unsigned int sdhi1_cd_mux[] = {
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SD1_CD_MARK,
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};
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static const unsigned int sdhi1_wp_pins[] = {
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/* WP */
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RCAR_GP_PIN(0, 20),
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};
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static const unsigned int sdhi1_wp_mux[] = {
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SD1_WP_MARK,
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};
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/* - SDHI2 ------------------------------------------------------------------ */
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static const unsigned int sdhi2_data1_pins[] = {
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/* D0 */
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@ -2160,6 +2266,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
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SH_PFC_PIN_GROUP(scif5_data_f),
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SH_PFC_PIN_GROUP(scif_clk_a),
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SH_PFC_PIN_GROUP(scif_clk_b),
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SH_PFC_PIN_GROUP(sdhi0_data1),
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SH_PFC_PIN_GROUP(sdhi0_data4),
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SH_PFC_PIN_GROUP(sdhi0_ctrl),
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SH_PFC_PIN_GROUP(sdhi0_cd),
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SH_PFC_PIN_GROUP(sdhi0_wp),
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SH_PFC_PIN_GROUP(sdhi1_data1),
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SH_PFC_PIN_GROUP(sdhi1_data4),
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SH_PFC_PIN_GROUP(sdhi1_ctrl),
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SH_PFC_PIN_GROUP(sdhi1_cd),
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SH_PFC_PIN_GROUP(sdhi1_wp),
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SH_PFC_PIN_GROUP(sdhi2_data1),
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SH_PFC_PIN_GROUP(sdhi2_data4),
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SH_PFC_PIN_GROUP(sdhi2_ctrl),
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@ -2339,6 +2455,22 @@ static const char * const scif_clk_groups[] = {
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"scif_clk_b",
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};
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static const char * const sdhi0_groups[] = {
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"sdhi0_data1",
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"sdhi0_data4",
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"sdhi0_ctrl",
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"sdhi0_cd",
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"sdhi0_wp",
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};
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static const char * const sdhi1_groups[] = {
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"sdhi1_data1",
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"sdhi1_data4",
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"sdhi1_ctrl",
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"sdhi1_cd",
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"sdhi1_wp",
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};
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static const char * const sdhi2_groups[] = {
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"sdhi2_data1",
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"sdhi2_data4",
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@ -2398,6 +2530,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
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SH_PFC_FUNCTION(scif4),
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SH_PFC_FUNCTION(scif5),
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SH_PFC_FUNCTION(scif_clk),
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SH_PFC_FUNCTION(sdhi0),
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SH_PFC_FUNCTION(sdhi1),
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SH_PFC_FUNCTION(sdhi2),
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SH_PFC_FUNCTION(usb0),
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SH_PFC_FUNCTION(usb1),
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@ -3245,9 +3379,33 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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{ },
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};
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static int r8a77470_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
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u32 *pocctrl)
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{
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int bit = -EINVAL;
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*pocctrl = 0xe60600b0;
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if (pin >= RCAR_GP_PIN(0, 5) && pin <= RCAR_GP_PIN(0, 10))
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bit = 0;
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if (pin >= RCAR_GP_PIN(0, 13) && pin <= RCAR_GP_PIN(0, 22))
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bit = 2;
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if (pin >= RCAR_GP_PIN(4, 14) && pin <= RCAR_GP_PIN(4, 19))
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bit = 1;
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return bit;
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}
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static const struct sh_pfc_soc_operations r8a77470_pinmux_ops = {
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.pin_to_pocctrl = r8a77470_pin_to_pocctrl,
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};
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#ifdef CONFIG_PINCTRL_PFC_R8A77470
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const struct sh_pfc_soc_info r8a77470_pinmux_info = {
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.name = "r8a77470_pfc",
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.ops = &r8a77470_pinmux_ops,
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.unlock_reg = 0xe6060000, /* PMMR */
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.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
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