spi/pl022: add PrimeCell generic DMA support
This extends the PL022 SSP/SPI driver with generic DMA engine support using the PrimeCell DMA engine interface. Also fix up the test code for the U300 platform. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
This commit is contained in:
Linus Walleij
Grant Likely
parent
cdbc8f042f
commit
b1b6b9aa6f
@ -27,7 +27,6 @@
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/*
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* TODO:
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* - add timeout on polled transfers
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* - add generic DMA framework support
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*/
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#include <linux/init.h>
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@ -45,6 +44,9 @@
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#include <linux/amba/pl022.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/scatterlist.h>
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/*
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* This macro is used to define some register default values.
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@ -381,6 +383,14 @@ struct pl022 {
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enum ssp_reading read;
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enum ssp_writing write;
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u32 exp_fifo_level;
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/* DMA settings */
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#ifdef CONFIG_DMA_ENGINE
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struct dma_chan *dma_rx_channel;
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struct dma_chan *dma_tx_channel;
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struct sg_table sgt_rx;
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struct sg_table sgt_tx;
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char *dummypage;
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#endif
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};
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/**
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@ -406,7 +416,7 @@ struct chip_data {
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u16 dmacr;
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u16 cpsr;
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u8 n_bytes;
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u8 enable_dma:1;
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bool enable_dma;
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enum ssp_reading read;
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enum ssp_writing write;
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void (*cs_control) (u32 command);
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@ -763,6 +773,371 @@ static void *next_transfer(struct pl022 *pl022)
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}
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return STATE_DONE;
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}
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/*
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* This DMA functionality is only compiled in if we have
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* access to the generic DMA devices/DMA engine.
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*/
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#ifdef CONFIG_DMA_ENGINE
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static void unmap_free_dma_scatter(struct pl022 *pl022)
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{
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/* Unmap and free the SG tables */
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dma_unmap_sg(&pl022->adev->dev, pl022->sgt_tx.sgl,
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pl022->sgt_tx.nents, DMA_TO_DEVICE);
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dma_unmap_sg(&pl022->adev->dev, pl022->sgt_rx.sgl,
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pl022->sgt_rx.nents, DMA_FROM_DEVICE);
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sg_free_table(&pl022->sgt_rx);
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sg_free_table(&pl022->sgt_tx);
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}
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static void dma_callback(void *data)
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{
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struct pl022 *pl022 = data;
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struct spi_message *msg = pl022->cur_msg;
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BUG_ON(!pl022->sgt_rx.sgl);
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#ifdef VERBOSE_DEBUG
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/*
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* Optionally dump out buffers to inspect contents, this is
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* good if you want to convince yourself that the loopback
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* read/write contents are the same, when adopting to a new
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* DMA engine.
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*/
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{
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struct scatterlist *sg;
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unsigned int i;
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dma_sync_sg_for_cpu(&pl022->adev->dev,
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pl022->sgt_rx.sgl,
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pl022->sgt_rx.nents,
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DMA_FROM_DEVICE);
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for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) {
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dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i);
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print_hex_dump(KERN_ERR, "SPI RX: ",
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DUMP_PREFIX_OFFSET,
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16,
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1,
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sg_virt(sg),
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sg_dma_len(sg),
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1);
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}
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for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) {
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dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i);
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print_hex_dump(KERN_ERR, "SPI TX: ",
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DUMP_PREFIX_OFFSET,
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16,
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1,
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sg_virt(sg),
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sg_dma_len(sg),
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1);
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}
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}
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#endif
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unmap_free_dma_scatter(pl022);
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/* Update total bytes transfered */
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msg->actual_length += pl022->cur_transfer->len;
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if (pl022->cur_transfer->cs_change)
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pl022->cur_chip->
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cs_control(SSP_CHIP_DESELECT);
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/* Move to next transfer */
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msg->state = next_transfer(pl022);
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tasklet_schedule(&pl022->pump_transfers);
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}
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static void setup_dma_scatter(struct pl022 *pl022,
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void *buffer,
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unsigned int length,
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struct sg_table *sgtab)
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{
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struct scatterlist *sg;
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int bytesleft = length;
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void *bufp = buffer;
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int mapbytes;
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int i;
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if (buffer) {
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for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
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/*
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* If there are less bytes left than what fits
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* in the current page (plus page alignment offset)
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* we just feed in this, else we stuff in as much
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* as we can.
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*/
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if (bytesleft < (PAGE_SIZE - offset_in_page(bufp)))
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mapbytes = bytesleft;
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else
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mapbytes = PAGE_SIZE - offset_in_page(bufp);
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sg_set_page(sg, virt_to_page(bufp),
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mapbytes, offset_in_page(bufp));
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bufp += mapbytes;
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bytesleft -= mapbytes;
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dev_dbg(&pl022->adev->dev,
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"set RX/TX target page @ %p, %d bytes, %d left\n",
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bufp, mapbytes, bytesleft);
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}
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} else {
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/* Map the dummy buffer on every page */
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for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
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if (bytesleft < PAGE_SIZE)
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mapbytes = bytesleft;
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else
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mapbytes = PAGE_SIZE;
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sg_set_page(sg, virt_to_page(pl022->dummypage),
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mapbytes, 0);
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bytesleft -= mapbytes;
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dev_dbg(&pl022->adev->dev,
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"set RX/TX to dummy page %d bytes, %d left\n",
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mapbytes, bytesleft);
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}
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}
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BUG_ON(bytesleft);
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}
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/**
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* configure_dma - configures the channels for the next transfer
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* @pl022: SSP driver's private data structure
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*/
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static int configure_dma(struct pl022 *pl022)
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{
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struct dma_slave_config rx_conf = {
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.src_addr = SSP_DR(pl022->phybase),
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.direction = DMA_FROM_DEVICE,
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.src_maxburst = pl022->vendor->fifodepth >> 1,
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};
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struct dma_slave_config tx_conf = {
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.dst_addr = SSP_DR(pl022->phybase),
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.direction = DMA_TO_DEVICE,
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.dst_maxburst = pl022->vendor->fifodepth >> 1,
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};
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unsigned int pages;
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int ret;
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int sglen;
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struct dma_chan *rxchan = pl022->dma_rx_channel;
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struct dma_chan *txchan = pl022->dma_tx_channel;
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struct dma_async_tx_descriptor *rxdesc;
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struct dma_async_tx_descriptor *txdesc;
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dma_cookie_t cookie;
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/* Check that the channels are available */
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if (!rxchan || !txchan)
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return -ENODEV;
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switch (pl022->read) {
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case READING_NULL:
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/* Use the same as for writing */
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rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
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break;
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case READING_U8:
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rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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break;
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case READING_U16:
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rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
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break;
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case READING_U32:
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rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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break;
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}
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switch (pl022->write) {
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case WRITING_NULL:
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/* Use the same as for reading */
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tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
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break;
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case WRITING_U8:
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tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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break;
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case WRITING_U16:
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tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
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break;
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case WRITING_U32:
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tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;;
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break;
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}
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/* SPI pecularity: we need to read and write the same width */
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if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
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rx_conf.src_addr_width = tx_conf.dst_addr_width;
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if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
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tx_conf.dst_addr_width = rx_conf.src_addr_width;
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BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width);
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rxchan->device->device_control(rxchan, DMA_SLAVE_CONFIG,
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(unsigned long) &rx_conf);
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txchan->device->device_control(txchan, DMA_SLAVE_CONFIG,
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(unsigned long) &tx_conf);
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/* Create sglists for the transfers */
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pages = (pl022->cur_transfer->len >> PAGE_SHIFT) + 1;
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dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages);
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ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_KERNEL);
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if (ret)
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goto err_alloc_rx_sg;
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ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_KERNEL);
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if (ret)
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goto err_alloc_tx_sg;
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/* Fill in the scatterlists for the RX+TX buffers */
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setup_dma_scatter(pl022, pl022->rx,
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pl022->cur_transfer->len, &pl022->sgt_rx);
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setup_dma_scatter(pl022, pl022->tx,
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pl022->cur_transfer->len, &pl022->sgt_tx);
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/* Map DMA buffers */
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sglen = dma_map_sg(&pl022->adev->dev, pl022->sgt_rx.sgl,
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pl022->sgt_rx.nents, DMA_FROM_DEVICE);
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if (!sglen)
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goto err_rx_sgmap;
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sglen = dma_map_sg(&pl022->adev->dev, pl022->sgt_tx.sgl,
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pl022->sgt_tx.nents, DMA_TO_DEVICE);
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if (!sglen)
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goto err_tx_sgmap;
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/* Send both scatterlists */
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rxdesc = rxchan->device->device_prep_slave_sg(rxchan,
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pl022->sgt_rx.sgl,
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pl022->sgt_rx.nents,
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DMA_FROM_DEVICE,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!rxdesc)
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goto err_rxdesc;
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txdesc = txchan->device->device_prep_slave_sg(txchan,
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pl022->sgt_tx.sgl,
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pl022->sgt_tx.nents,
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DMA_TO_DEVICE,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!txdesc)
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goto err_txdesc;
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/* Put the callback on the RX transfer only, that should finish last */
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rxdesc->callback = dma_callback;
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rxdesc->callback_param = pl022;
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/* Submit and fire RX and TX with TX last so we're ready to read! */
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cookie = rxdesc->tx_submit(rxdesc);
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if (dma_submit_error(cookie))
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goto err_submit_rx;
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cookie = txdesc->tx_submit(txdesc);
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if (dma_submit_error(cookie))
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goto err_submit_tx;
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rxchan->device->device_issue_pending(rxchan);
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txchan->device->device_issue_pending(txchan);
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return 0;
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err_submit_tx:
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err_submit_rx:
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err_txdesc:
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txchan->device->device_control(txchan, DMA_TERMINATE_ALL, 0);
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err_rxdesc:
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rxchan->device->device_control(rxchan, DMA_TERMINATE_ALL, 0);
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dma_unmap_sg(&pl022->adev->dev, pl022->sgt_tx.sgl,
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pl022->sgt_tx.nents, DMA_TO_DEVICE);
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err_tx_sgmap:
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dma_unmap_sg(&pl022->adev->dev, pl022->sgt_rx.sgl,
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pl022->sgt_tx.nents, DMA_FROM_DEVICE);
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err_rx_sgmap:
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sg_free_table(&pl022->sgt_tx);
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err_alloc_tx_sg:
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sg_free_table(&pl022->sgt_rx);
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err_alloc_rx_sg:
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return -ENOMEM;
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}
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static int __init pl022_dma_probe(struct pl022 *pl022)
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{
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dma_cap_mask_t mask;
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/* Try to acquire a generic DMA engine slave channel */
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dma_cap_zero(mask);
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dma_cap_set(DMA_SLAVE, mask);
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/*
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* We need both RX and TX channels to do DMA, else do none
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* of them.
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*/
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pl022->dma_rx_channel = dma_request_channel(mask,
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pl022->master_info->dma_filter,
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pl022->master_info->dma_rx_param);
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if (!pl022->dma_rx_channel) {
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dev_err(&pl022->adev->dev, "no RX DMA channel!\n");
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goto err_no_rxchan;
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}
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pl022->dma_tx_channel = dma_request_channel(mask,
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pl022->master_info->dma_filter,
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pl022->master_info->dma_tx_param);
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if (!pl022->dma_tx_channel) {
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dev_err(&pl022->adev->dev, "no TX DMA channel!\n");
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goto err_no_txchan;
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}
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pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
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if (!pl022->dummypage) {
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dev_err(&pl022->adev->dev, "no DMA dummypage!\n");
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goto err_no_dummypage;
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}
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dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n",
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dma_chan_name(pl022->dma_rx_channel),
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dma_chan_name(pl022->dma_tx_channel));
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return 0;
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err_no_dummypage:
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dma_release_channel(pl022->dma_tx_channel);
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err_no_txchan:
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dma_release_channel(pl022->dma_rx_channel);
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pl022->dma_rx_channel = NULL;
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err_no_rxchan:
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return -ENODEV;
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}
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static void terminate_dma(struct pl022 *pl022)
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{
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struct dma_chan *rxchan = pl022->dma_rx_channel;
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struct dma_chan *txchan = pl022->dma_tx_channel;
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rxchan->device->device_control(rxchan, DMA_TERMINATE_ALL, 0);
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txchan->device->device_control(txchan, DMA_TERMINATE_ALL, 0);
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unmap_free_dma_scatter(pl022);
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}
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static void pl022_dma_remove(struct pl022 *pl022)
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{
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if (pl022->busy)
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terminate_dma(pl022);
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if (pl022->dma_tx_channel)
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dma_release_channel(pl022->dma_tx_channel);
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if (pl022->dma_rx_channel)
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dma_release_channel(pl022->dma_rx_channel);
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kfree(pl022->dummypage);
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}
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#else
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static inline int configure_dma(struct pl022 *pl022)
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{
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return -ENODEV;
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}
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static inline int pl022_dma_probe(struct pl022 *pl022)
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{
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return 0;
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}
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static inline void pl022_dma_remove(struct pl022 *pl022)
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{
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}
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#endif
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/**
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* pl022_interrupt_handler - Interrupt handler for SSP controller
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*
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@ -794,14 +1169,17 @@ static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)
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if (unlikely(!irq_status))
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return IRQ_NONE;
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/* This handles the error code interrupts */
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/*
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* This handles the FIFO interrupts, the timeout
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* interrupts are flatly ignored, they cannot be
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* trusted.
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*/
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if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) {
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/*
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* Overrun interrupt - bail out since our Data has been
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* corrupted
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*/
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dev_err(&pl022->adev->dev,
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"FIFO overrun\n");
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dev_err(&pl022->adev->dev, "FIFO overrun\n");
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if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
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dev_err(&pl022->adev->dev,
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"RXFIFO is full\n");
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@ -896,8 +1274,8 @@ static int set_up_next_transfer(struct pl022 *pl022,
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}
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/**
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* pump_transfers - Tasklet function which schedules next interrupt transfer
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* when running in interrupt transfer mode.
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* pump_transfers - Tasklet function which schedules next transfer
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* when running in interrupt or DMA transfer mode.
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* @data: SSP driver private data structure
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*
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*/
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@ -954,65 +1332,23 @@ static void pump_transfers(unsigned long data)
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}
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/* Flush the FIFOs and let's go! */
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flush(pl022);
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if (pl022->cur_chip->enable_dma) {
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if (configure_dma(pl022)) {
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dev_dbg(&pl022->adev->dev,
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"configuration of DMA failed, fall back to interrupt mode\n");
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goto err_config_dma;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
err_config_dma:
|
||||
writew(ENABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
|
||||
}
|
||||
|
||||
/**
|
||||
* NOT IMPLEMENTED
|
||||
* configure_dma - It configures the DMA pipes for DMA transfers
|
||||
* @data: SSP driver's private data structure
|
||||
*
|
||||
*/
|
||||
static int configure_dma(void *data)
|
||||
static void do_interrupt_dma_transfer(struct pl022 *pl022)
|
||||
{
|
||||
struct pl022 *pl022 = data;
|
||||
dev_dbg(&pl022->adev->dev, "configure DMA\n");
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
/**
|
||||
* do_dma_transfer - It handles transfers of the current message
|
||||
* if it is DMA xfer.
|
||||
* NOT FULLY IMPLEMENTED
|
||||
* @data: SSP driver's private data structure
|
||||
*/
|
||||
static void do_dma_transfer(void *data)
|
||||
{
|
||||
struct pl022 *pl022 = data;
|
||||
|
||||
if (configure_dma(data)) {
|
||||
dev_dbg(&pl022->adev->dev, "configuration of DMA Failed!\n");
|
||||
goto err_config_dma;
|
||||
}
|
||||
|
||||
/* TODO: Implememt DMA setup of pipes here */
|
||||
|
||||
/* Enable target chip, set up transfer */
|
||||
pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
|
||||
if (set_up_next_transfer(pl022, pl022->cur_transfer)) {
|
||||
/* Error path */
|
||||
pl022->cur_msg->state = STATE_ERROR;
|
||||
pl022->cur_msg->status = -EIO;
|
||||
giveback(pl022);
|
||||
return;
|
||||
}
|
||||
/* Enable SSP */
|
||||
writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
|
||||
SSP_CR1(pl022->virtbase));
|
||||
|
||||
/* TODO: Enable the DMA transfer here */
|
||||
return;
|
||||
|
||||
err_config_dma:
|
||||
pl022->cur_msg->state = STATE_ERROR;
|
||||
pl022->cur_msg->status = -EIO;
|
||||
giveback(pl022);
|
||||
return;
|
||||
}
|
||||
|
||||
static void do_interrupt_transfer(void *data)
|
||||
{
|
||||
struct pl022 *pl022 = data;
|
||||
u32 irqflags = ENABLE_ALL_INTERRUPTS;
|
||||
|
||||
/* Enable target chip */
|
||||
pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
|
||||
@ -1023,15 +1359,26 @@ static void do_interrupt_transfer(void *data)
|
||||
giveback(pl022);
|
||||
return;
|
||||
}
|
||||
/* If we're using DMA, set up DMA here */
|
||||
if (pl022->cur_chip->enable_dma) {
|
||||
/* Configure DMA transfer */
|
||||
if (configure_dma(pl022)) {
|
||||
dev_dbg(&pl022->adev->dev,
|
||||
"configuration of DMA failed, fall back to interrupt mode\n");
|
||||
goto err_config_dma;
|
||||
}
|
||||
/* Disable interrupts in DMA mode, IRQ from DMA controller */
|
||||
irqflags = DISABLE_ALL_INTERRUPTS;
|
||||
}
|
||||
err_config_dma:
|
||||
/* Enable SSP, turn on interrupts */
|
||||
writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
|
||||
SSP_CR1(pl022->virtbase));
|
||||
writew(ENABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
|
||||
writew(irqflags, SSP_IMSC(pl022->virtbase));
|
||||
}
|
||||
|
||||
static void do_polling_transfer(void *data)
|
||||
static void do_polling_transfer(struct pl022 *pl022)
|
||||
{
|
||||
struct pl022 *pl022 = data;
|
||||
struct spi_message *message = NULL;
|
||||
struct spi_transfer *transfer = NULL;
|
||||
struct spi_transfer *previous = NULL;
|
||||
@ -1101,7 +1448,7 @@ static void do_polling_transfer(void *data)
|
||||
*
|
||||
* This function checks if there is any spi message in the queue that
|
||||
* needs processing and delegate control to appropriate function
|
||||
* do_polling_transfer()/do_interrupt_transfer()/do_dma_transfer()
|
||||
* do_polling_transfer()/do_interrupt_dma_transfer()
|
||||
* based on the kind of the transfer
|
||||
*
|
||||
*/
|
||||
@ -1150,10 +1497,8 @@ static void pump_messages(struct work_struct *work)
|
||||
|
||||
if (pl022->cur_chip->xfer_type == POLLING_TRANSFER)
|
||||
do_polling_transfer(pl022);
|
||||
else if (pl022->cur_chip->xfer_type == INTERRUPT_TRANSFER)
|
||||
do_interrupt_transfer(pl022);
|
||||
else
|
||||
do_dma_transfer(pl022);
|
||||
do_interrupt_dma_transfer(pl022);
|
||||
}
|
||||
|
||||
|
||||
@ -1468,23 +1813,6 @@ static int calculate_effective_freq(struct pl022 *pl022,
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* NOT IMPLEMENTED
|
||||
* process_dma_info - Processes the DMA info provided by client drivers
|
||||
* @chip_info: chip info provided by client device
|
||||
* @chip: Runtime state maintained by the SSP controller for each spi device
|
||||
*
|
||||
* This function processes and stores DMA config provided by client driver
|
||||
* into the runtime state maintained by the SSP controller driver
|
||||
*/
|
||||
static int process_dma_info(struct pl022_config_chip *chip_info,
|
||||
struct chip_data *chip)
|
||||
{
|
||||
dev_err(chip_info->dev,
|
||||
"cannot process DMA info, DMA not implemented!\n");
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
/**
|
||||
* pl022_setup - setup function registered to SPI master framework
|
||||
* @spi: spi device which is requesting setup
|
||||
@ -1552,8 +1880,6 @@ static int pl022_setup(struct spi_device *spi)
|
||||
|
||||
dev_dbg(&spi->dev, "allocated memory for controller data\n");
|
||||
|
||||
/* Pointer back to the SPI device */
|
||||
chip_info->dev = &spi->dev;
|
||||
/*
|
||||
* Set controller data default values:
|
||||
* Polling is supported by default
|
||||
@ -1579,6 +1905,9 @@ static int pl022_setup(struct spi_device *spi)
|
||||
"using user supplied controller_data settings\n");
|
||||
}
|
||||
|
||||
/* Pointer back to the SPI device */
|
||||
chip_info->dev = &spi->dev;
|
||||
|
||||
/*
|
||||
* We can override with custom divisors, else we use the board
|
||||
* frequency setting
|
||||
@ -1637,9 +1966,8 @@ static int pl022_setup(struct spi_device *spi)
|
||||
chip->cpsr = 0;
|
||||
if ((chip_info->com_mode == DMA_TRANSFER)
|
||||
&& ((pl022->master_info)->enable_dma)) {
|
||||
chip->enable_dma = 1;
|
||||
chip->enable_dma = true;
|
||||
dev_dbg(&spi->dev, "DMA mode set in controller state\n");
|
||||
status = process_dma_info(chip_info, chip);
|
||||
if (status < 0)
|
||||
goto err_config_params;
|
||||
SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
|
||||
@ -1647,7 +1975,7 @@ static int pl022_setup(struct spi_device *spi)
|
||||
SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
|
||||
SSP_DMACR_MASK_TXDMAE, 1);
|
||||
} else {
|
||||
chip->enable_dma = 0;
|
||||
chip->enable_dma = false;
|
||||
dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n");
|
||||
SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
|
||||
SSP_DMACR_MASK_RXDMAE, 0);
|
||||
@ -1773,6 +2101,7 @@ pl022_probe(struct amba_device *adev, struct amba_id *id)
|
||||
if (status)
|
||||
goto err_no_ioregion;
|
||||
|
||||
pl022->phybase = adev->res.start;
|
||||
pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res));
|
||||
if (pl022->virtbase == NULL) {
|
||||
status = -ENOMEM;
|
||||
@ -1799,6 +2128,14 @@ pl022_probe(struct amba_device *adev, struct amba_id *id)
|
||||
dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status);
|
||||
goto err_no_irq;
|
||||
}
|
||||
|
||||
/* Get DMA channels */
|
||||
if (platform_info->enable_dma) {
|
||||
status = pl022_dma_probe(pl022);
|
||||
if (status != 0)
|
||||
goto err_no_dma;
|
||||
}
|
||||
|
||||
/* Initialize and start queue */
|
||||
status = init_queue(pl022);
|
||||
if (status != 0) {
|
||||
@ -1827,6 +2164,8 @@ pl022_probe(struct amba_device *adev, struct amba_id *id)
|
||||
err_start_queue:
|
||||
err_init_queue:
|
||||
destroy_queue(pl022);
|
||||
pl022_dma_remove(pl022);
|
||||
err_no_dma:
|
||||
free_irq(adev->irq[0], pl022);
|
||||
err_no_irq:
|
||||
clk_put(pl022->clk);
|
||||
@ -1857,6 +2196,7 @@ pl022_remove(struct amba_device *adev)
|
||||
return status;
|
||||
}
|
||||
load_ssp_default_config(pl022);
|
||||
pl022_dma_remove(pl022);
|
||||
free_irq(adev->irq[0], pl022);
|
||||
clk_disable(pl022->clk);
|
||||
clk_put(pl022->clk);
|
||||
|
||||
@ -228,6 +228,7 @@ enum ssp_chip_select {
|
||||
};
|
||||
|
||||
|
||||
struct dma_chan;
|
||||
/**
|
||||
* struct pl022_ssp_master - device.platform_data for SPI controller devices.
|
||||
* @num_chipselect: chipselects are used to distinguish individual
|
||||
@ -235,11 +236,16 @@ enum ssp_chip_select {
|
||||
* each slave has a chipselect signal, but it's common that not
|
||||
* every chipselect is connected to a slave.
|
||||
* @enable_dma: if true enables DMA driven transfers.
|
||||
* @dma_rx_param: parameter to locate an RX DMA channel.
|
||||
* @dma_tx_param: parameter to locate a TX DMA channel.
|
||||
*/
|
||||
struct pl022_ssp_controller {
|
||||
u16 bus_id;
|
||||
u8 num_chipselect;
|
||||
u8 enable_dma:1;
|
||||
bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
|
||||
void *dma_rx_param;
|
||||
void *dma_tx_param;
|
||||
};
|
||||
|
||||
/**
|
||||
|
||||
Loading…
Reference in New Issue
Block a user