[ARM] 4145/2: AT91: Add support for AT91SAM9263 processor
Add support for the Atmel AT91SAM9263 processor. It is similar to the AT91SAM9260 but with more integrated peripherals, 5 GPIO banks, etc. Original patch from Nicolas Ferre. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Andrew Victor
Russell King
parent
d0760b3bc8
commit
b2c6561605
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@ -14,6 +14,9 @@ config ARCH_AT91SAM9260
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config ARCH_AT91SAM9261
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bool "AT91SAM9261"
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config ARCH_AT91SAM9263
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bool "AT91SAM9263"
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endchoice
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# ----------------------------------------------------------
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@ -13,6 +13,7 @@ obj-$(CONFIG_PM) += pm.o
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obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o
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obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o
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obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o
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obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o
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# AT91RM9200 board-specific support
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obj-$(CONFIG_MACH_ONEARM) += board-1arm.o
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@ -0,0 +1,313 @@
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/*
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* arch/arm/mach-at91/at91sam9263.c
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*
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* Copyright (C) 2007 Atmel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <linux/module.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/arch/at91sam9263.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include "generic.h"
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#include "clock.h"
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static struct map_desc at91sam9263_io_desc[] __initdata = {
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{
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.virtual = AT91_VA_BASE_SYS,
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.pfn = __phys_to_pfn(AT91_BASE_SYS),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}, {
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.virtual = AT91_IO_VIRT_BASE - AT91SAM9263_SRAM0_SIZE,
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.pfn = __phys_to_pfn(AT91SAM9263_SRAM0_BASE),
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.length = AT91SAM9263_SRAM0_SIZE,
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.type = MT_DEVICE,
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}, {
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.virtual = AT91_IO_VIRT_BASE - AT91SAM9263_SRAM0_SIZE - AT91SAM9263_SRAM1_SIZE,
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.pfn = __phys_to_pfn(AT91SAM9263_SRAM1_BASE),
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.length = AT91SAM9263_SRAM1_SIZE,
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.type = MT_DEVICE,
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},
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};
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/* --------------------------------------------------------------------
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* Clocks
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* -------------------------------------------------------------------- */
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/*
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* The peripheral clocks.
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*/
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static struct clk pioA_clk = {
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.name = "pioA_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_PIOA,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioB_clk = {
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.name = "pioB_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_PIOB,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioCDE_clk = {
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.name = "pioCDE_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_PIOCDE,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart0_clk = {
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.name = "usart0_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_US0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart1_clk = {
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.name = "usart1_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_US1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart2_clk = {
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.name = "usart2_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_US2,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk mmc0_clk = {
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.name = "mci0_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_MCI0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk mmc1_clk = {
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.name = "mci1_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_MCI1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk twi_clk = {
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.name = "twi_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_TWI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk spi0_clk = {
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.name = "spi0_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_SPI0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk spi1_clk = {
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.name = "spi1_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_SPI1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tcb_clk = {
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.name = "tcb_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_TCB,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ether_clk = {
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.name = "ether_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_EMAC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk udc_clk = {
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.name = "udc_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_UDP,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk isi_clk = {
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.name = "isi_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_ISI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk lcdc_clk = {
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.name = "lcdc_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_ISI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ohci_clk = {
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.name = "ohci_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_UHP,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk *periph_clocks[] __initdata = {
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&pioA_clk,
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&pioB_clk,
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&pioCDE_clk,
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&usart0_clk,
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&usart1_clk,
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&usart2_clk,
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&mmc0_clk,
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&mmc1_clk,
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// can
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&twi_clk,
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&spi0_clk,
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&spi1_clk,
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// ssc0 .. ssc1
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// ac97
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&tcb_clk,
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// pwmc
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ðer_clk,
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// 2dge
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&udc_clk,
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&isi_clk,
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&lcdc_clk,
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// dma
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&ohci_clk,
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// irq0 .. irq1
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};
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/*
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* The four programmable clocks.
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* You must configure pin multiplexing to bring these signals out.
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*/
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static struct clk pck0 = {
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.name = "pck0",
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.pmc_mask = AT91_PMC_PCK0,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 0,
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};
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static struct clk pck1 = {
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.name = "pck1",
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.pmc_mask = AT91_PMC_PCK1,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 1,
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};
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static struct clk pck2 = {
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.name = "pck2",
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.pmc_mask = AT91_PMC_PCK2,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 2,
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};
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static struct clk pck3 = {
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.name = "pck3",
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.pmc_mask = AT91_PMC_PCK3,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 3,
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};
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static void __init at91sam9263_register_clocks(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
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clk_register(periph_clocks[i]);
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clk_register(&pck0);
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clk_register(&pck1);
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clk_register(&pck2);
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clk_register(&pck3);
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}
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/* --------------------------------------------------------------------
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* GPIO
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* -------------------------------------------------------------------- */
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static struct at91_gpio_bank at91sam9263_gpio[] = {
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{
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.id = AT91SAM9263_ID_PIOA,
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.offset = AT91_PIOA,
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.clock = &pioA_clk,
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}, {
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.id = AT91SAM9263_ID_PIOB,
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.offset = AT91_PIOB,
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.clock = &pioB_clk,
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}, {
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.id = AT91SAM9263_ID_PIOCDE,
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.offset = AT91_PIOC,
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.clock = &pioCDE_clk,
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}, {
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.id = AT91SAM9263_ID_PIOCDE,
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.offset = AT91_PIOD,
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.clock = &pioCDE_clk,
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}, {
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.id = AT91SAM9263_ID_PIOCDE,
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.offset = AT91_PIOE,
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.clock = &pioCDE_clk,
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}
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};
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static void at91sam9263_reset(void)
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{
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at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
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}
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/* --------------------------------------------------------------------
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* AT91SAM9263 processor initialization
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* -------------------------------------------------------------------- */
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void __init at91sam9263_initialize(unsigned long main_clock)
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{
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/* Map peripherals */
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iotable_init(at91sam9263_io_desc, ARRAY_SIZE(at91sam9263_io_desc));
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at91_arch_reset = at91sam9263_reset;
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at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
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/* Init clock subsystem */
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at91_clock_init(main_clock);
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/* Register the processor-specific clocks */
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at91sam9263_register_clocks();
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/* Register GPIO subsystem */
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at91_gpio_init(at91sam9263_gpio, 5);
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}
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/* --------------------------------------------------------------------
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* Interrupt initialization
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* -------------------------------------------------------------------- */
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/*
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* The default interrupt priority levels (0 = lowest, 7 = highest).
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*/
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static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
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7, /* Advanced Interrupt Controller (FIQ) */
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7, /* System Peripherals */
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0, /* Parallel IO Controller A */
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0, /* Parallel IO Controller B */
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0, /* Parallel IO Controller C, D and E */
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0,
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0,
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6, /* USART 0 */
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6, /* USART 1 */
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6, /* USART 2 */
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0, /* Multimedia Card Interface 0 */
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0, /* Multimedia Card Interface 1 */
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4, /* CAN */
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0, /* Two-Wire Interface */
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6, /* Serial Peripheral Interface 0 */
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6, /* Serial Peripheral Interface 1 */
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5, /* Serial Synchronous Controller 0 */
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5, /* Serial Synchronous Controller 1 */
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6, /* AC97 Controller */
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0, /* Timer Counter 0, 1 and 2 */
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0, /* Pulse Width Modulation Controller */
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3, /* Ethernet */
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0,
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0, /* 2D Graphic Engine */
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3, /* USB Device Port */
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0, /* Image Sensor Interface */
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3, /* LDC Controller */
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0, /* DMA Controller */
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0,
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3, /* USB Host port */
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0, /* Advanced Interrupt Controller (IRQ0) */
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0, /* Advanced Interrupt Controller (IRQ1) */
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};
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void __init at91sam9263_init_interrupts(unsigned int priority[NR_AIC_IRQS])
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{
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if (!priority)
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priority = at91sam9263_default_irq_priority;
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/* Initialize the AIC interrupt controller */
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at91_aic_init(priority);
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/* Enable GPIO interrupts */
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at91_gpio_irq_setup();
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}
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@ -0,0 +1,818 @@
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/*
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* arch/arm/mach-at91/at91sam9263_devices.c
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*
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* Copyright (C) 2007 Atmel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <linux/platform_device.h>
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#include <asm/arch/board.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/at91sam9263.h>
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#include <asm/arch/at91sam926x_mc.h>
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#include <asm/arch/at91sam9263_matrix.h>
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#include "generic.h"
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#define SZ_512 0x00000200
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#define SZ_256 0x00000100
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#define SZ_16 0x00000010
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/* --------------------------------------------------------------------
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* USB Host
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* -------------------------------------------------------------------- */
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#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
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static u64 ohci_dmamask = 0xffffffffUL;
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static struct at91_usbh_data usbh_data;
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static struct resource usbh_resources[] = {
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[0] = {
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.start = AT91SAM9263_UHP_BASE,
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.end = AT91SAM9263_UHP_BASE + SZ_1M - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = AT91SAM9263_ID_UHP,
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.end = AT91SAM9263_ID_UHP,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device at91_usbh_device = {
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.name = "at91_ohci",
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.id = -1,
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.dev = {
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.dma_mask = &ohci_dmamask,
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.coherent_dma_mask = 0xffffffff,
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.platform_data = &usbh_data,
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},
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.resource = usbh_resources,
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.num_resources = ARRAY_SIZE(usbh_resources),
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};
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void __init at91_add_device_usbh(struct at91_usbh_data *data)
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{
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int i;
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if (!data)
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return;
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/* Enable VBus control for UHP ports */
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for (i = 0; i < data->ports; i++) {
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if (data->vbus_pin[i])
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at91_set_gpio_output(data->vbus_pin[i], 0);
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}
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usbh_data = *data;
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platform_device_register(&at91_usbh_device);
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}
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#else
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void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
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#endif
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/* --------------------------------------------------------------------
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* USB Device (Gadget)
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* -------------------------------------------------------------------- */
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#ifdef CONFIG_USB_GADGET_AT91
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static struct at91_udc_data udc_data;
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static struct resource udc_resources[] = {
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[0] = {
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.start = AT91SAM9263_BASE_UDP,
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.end = AT91SAM9263_BASE_UDP + SZ_16K - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = AT91SAM9263_ID_UDP,
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.end = AT91SAM9263_ID_UDP,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device at91_udc_device = {
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.name = "at91_udc",
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.id = -1,
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.dev = {
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.platform_data = &udc_data,
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},
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.resource = udc_resources,
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.num_resources = ARRAY_SIZE(udc_resources),
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};
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void __init at91_add_device_udc(struct at91_udc_data *data)
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{
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if (!data)
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return;
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if (data->vbus_pin) {
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at91_set_gpio_input(data->vbus_pin, 0);
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at91_set_deglitch(data->vbus_pin, 1);
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}
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/* Pullup pin is handled internally by USB device peripheral */
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udc_data = *data;
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platform_device_register(&at91_udc_device);
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}
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#else
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void __init at91_add_device_udc(struct at91_udc_data *data) {}
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#endif
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/* --------------------------------------------------------------------
|
||||
* Ethernet
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
|
||||
static u64 eth_dmamask = 0xffffffffUL;
|
||||
static struct at91_eth_data eth_data;
|
||||
|
||||
static struct resource eth_resources[] = {
|
||||
[0] = {
|
||||
.start = AT91SAM9263_BASE_EMAC,
|
||||
.end = AT91SAM9263_BASE_EMAC + SZ_16K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = AT91SAM9263_ID_EMAC,
|
||||
.end = AT91SAM9263_ID_EMAC,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device at91sam9263_eth_device = {
|
||||
.name = "macb",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.dma_mask = ð_dmamask,
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
.platform_data = ð_data,
|
||||
},
|
||||
.resource = eth_resources,
|
||||
.num_resources = ARRAY_SIZE(eth_resources),
|
||||
};
|
||||
|
||||
void __init at91_add_device_eth(struct at91_eth_data *data)
|
||||
{
|
||||
if (!data)
|
||||
return;
|
||||
|
||||
if (data->phy_irq_pin) {
|
||||
at91_set_gpio_input(data->phy_irq_pin, 0);
|
||||
at91_set_deglitch(data->phy_irq_pin, 1);
|
||||
}
|
||||
|
||||
/* Pins used for MII and RMII */
|
||||
at91_set_A_periph(AT91_PIN_PE21, 0); /* ETXCK_EREFCK */
|
||||
at91_set_B_periph(AT91_PIN_PC25, 0); /* ERXDV */
|
||||
at91_set_A_periph(AT91_PIN_PE25, 0); /* ERX0 */
|
||||
at91_set_A_periph(AT91_PIN_PE26, 0); /* ERX1 */
|
||||
at91_set_A_periph(AT91_PIN_PE27, 0); /* ERXER */
|
||||
at91_set_A_periph(AT91_PIN_PE28, 0); /* ETXEN */
|
||||
at91_set_A_periph(AT91_PIN_PE23, 0); /* ETX0 */
|
||||
at91_set_A_periph(AT91_PIN_PE24, 0); /* ETX1 */
|
||||
at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */
|
||||
at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */
|
||||
|
||||
if (!data->is_rmii) {
|
||||
at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */
|
||||
at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
|
||||
at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
|
||||
at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
|
||||
at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
|
||||
at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
|
||||
at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
|
||||
at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
|
||||
}
|
||||
|
||||
eth_data = *data;
|
||||
platform_device_register(&at91sam9263_eth_device);
|
||||
}
|
||||
#else
|
||||
void __init at91_add_device_eth(struct at91_eth_data *data) {}
|
||||
#endif
|
||||
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* MMC / SD
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
|
||||
static u64 mmc_dmamask = 0xffffffffUL;
|
||||
static struct at91_mmc_data mmc0_data, mmc1_data;
|
||||
|
||||
static struct resource mmc0_resources[] = {
|
||||
[0] = {
|
||||
.start = AT91SAM9263_BASE_MCI0,
|
||||
.end = AT91SAM9263_BASE_MCI0 + SZ_16K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = AT91SAM9263_ID_MCI0,
|
||||
.end = AT91SAM9263_ID_MCI0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device at91sam9263_mmc0_device = {
|
||||
.name = "at91_mci",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.dma_mask = &mmc_dmamask,
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
.platform_data = &mmc0_data,
|
||||
},
|
||||
.resource = mmc0_resources,
|
||||
.num_resources = ARRAY_SIZE(mmc0_resources),
|
||||
};
|
||||
|
||||
static struct resource mmc1_resources[] = {
|
||||
[0] = {
|
||||
.start = AT91SAM9263_BASE_MCI1,
|
||||
.end = AT91SAM9263_BASE_MCI1 + SZ_16K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = AT91SAM9263_ID_MCI1,
|
||||
.end = AT91SAM9263_ID_MCI1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device at91sam9263_mmc1_device = {
|
||||
.name = "at91_mci",
|
||||
.id = 1,
|
||||
.dev = {
|
||||
.dma_mask = &mmc_dmamask,
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
.platform_data = &mmc1_data,
|
||||
},
|
||||
.resource = mmc1_resources,
|
||||
.num_resources = ARRAY_SIZE(mmc1_resources),
|
||||
};
|
||||
|
||||
void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
|
||||
{
|
||||
if (!data)
|
||||
return;
|
||||
|
||||
/* input/irq */
|
||||
if (data->det_pin) {
|
||||
at91_set_gpio_input(data->det_pin, 1);
|
||||
at91_set_deglitch(data->det_pin, 1);
|
||||
}
|
||||
if (data->wp_pin)
|
||||
at91_set_gpio_input(data->wp_pin, 1);
|
||||
if (data->vcc_pin)
|
||||
at91_set_gpio_output(data->vcc_pin, 0);
|
||||
|
||||
if (mmc_id == 0) { /* MCI0 */
|
||||
/* CLK */
|
||||
at91_set_A_periph(AT91_PIN_PA12, 0);
|
||||
|
||||
if (data->slot_b) {
|
||||
/* CMD */
|
||||
at91_set_A_periph(AT91_PIN_PA16, 1);
|
||||
|
||||
/* DAT0, maybe DAT1..DAT3 */
|
||||
at91_set_A_periph(AT91_PIN_PA17, 1);
|
||||
if (data->wire4) {
|
||||
at91_set_A_periph(AT91_PIN_PA18, 1);
|
||||
at91_set_A_periph(AT91_PIN_PA19, 1);
|
||||
at91_set_A_periph(AT91_PIN_PA20, 1);
|
||||
}
|
||||
} else {
|
||||
/* CMD */
|
||||
at91_set_A_periph(AT91_PIN_PA1, 1);
|
||||
|
||||
/* DAT0, maybe DAT1..DAT3 */
|
||||
at91_set_A_periph(AT91_PIN_PA0, 1);
|
||||
if (data->wire4) {
|
||||
at91_set_A_periph(AT91_PIN_PA3, 1);
|
||||
at91_set_A_periph(AT91_PIN_PA4, 1);
|
||||
at91_set_A_periph(AT91_PIN_PA5, 1);
|
||||
}
|
||||
}
|
||||
|
||||
mmc0_data = *data;
|
||||
at91_clock_associate("mci0_clk", &at91sam9263_mmc1_device.dev, "mci_clk");
|
||||
platform_device_register(&at91sam9263_mmc0_device);
|
||||
} else { /* MCI1 */
|
||||
/* CLK */
|
||||
at91_set_A_periph(AT91_PIN_PA6, 0);
|
||||
|
||||
if (data->slot_b) {
|
||||
/* CMD */
|
||||
at91_set_A_periph(AT91_PIN_PA21, 1);
|
||||
|
||||
/* DAT0, maybe DAT1..DAT3 */
|
||||
at91_set_A_periph(AT91_PIN_PA22, 1);
|
||||
if (data->wire4) {
|
||||
at91_set_A_periph(AT91_PIN_PA23, 1);
|
||||
at91_set_A_periph(AT91_PIN_PA24, 1);
|
||||
at91_set_A_periph(AT91_PIN_PA25, 1);
|
||||
}
|
||||
} else {
|
||||
/* CMD */
|
||||
at91_set_A_periph(AT91_PIN_PA7, 1);
|
||||
|
||||
/* DAT0, maybe DAT1..DAT3 */
|
||||
at91_set_A_periph(AT91_PIN_PA8, 1);
|
||||
if (data->wire4) {
|
||||
at91_set_A_periph(AT91_PIN_PA9, 1);
|
||||
at91_set_A_periph(AT91_PIN_PA10, 1);
|
||||
at91_set_A_periph(AT91_PIN_PA11, 1);
|
||||
}
|
||||
}
|
||||
|
||||
mmc1_data = *data;
|
||||
at91_clock_associate("mci1_clk", &at91sam9263_mmc1_device.dev, "mci_clk");
|
||||
platform_device_register(&at91sam9263_mmc1_device);
|
||||
}
|
||||
}
|
||||
#else
|
||||
void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
|
||||
#endif
|
||||
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* NAND / SmartMedia
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
|
||||
static struct at91_nand_data nand_data;
|
||||
|
||||
#define NAND_BASE AT91_CHIPSELECT_3
|
||||
|
||||
static struct resource nand_resources[] = {
|
||||
{
|
||||
.start = NAND_BASE,
|
||||
.end = NAND_BASE + SZ_256M - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device at91sam9263_nand_device = {
|
||||
.name = "at91_nand",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &nand_data,
|
||||
},
|
||||
.resource = nand_resources,
|
||||
.num_resources = ARRAY_SIZE(nand_resources),
|
||||
};
|
||||
|
||||
void __init at91_add_device_nand(struct at91_nand_data *data)
|
||||
{
|
||||
unsigned long csa, mode;
|
||||
|
||||
if (!data)
|
||||
return;
|
||||
|
||||
csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
|
||||
at91_sys_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC);
|
||||
|
||||
/* set the bus interface characteristics */
|
||||
at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
|
||||
| AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
|
||||
|
||||
at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)
|
||||
| AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
|
||||
|
||||
at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
|
||||
|
||||
if (data->bus_width_16)
|
||||
mode = AT91_SMC_DBW_16;
|
||||
else
|
||||
mode = AT91_SMC_DBW_8;
|
||||
at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2));
|
||||
|
||||
/* enable pin */
|
||||
if (data->enable_pin)
|
||||
at91_set_gpio_output(data->enable_pin, 1);
|
||||
|
||||
/* ready/busy pin */
|
||||
if (data->rdy_pin)
|
||||
at91_set_gpio_input(data->rdy_pin, 1);
|
||||
|
||||
/* card detect pin */
|
||||
if (data->det_pin)
|
||||
at91_set_gpio_input(data->det_pin, 1);
|
||||
|
||||
nand_data = *data;
|
||||
platform_device_register(&at91sam9263_nand_device);
|
||||
}
|
||||
#else
|
||||
void __init at91_add_device_nand(struct at91_nand_data *data) {}
|
||||
#endif
|
||||
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* TWI (i2c)
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
|
||||
|
||||
static struct resource twi_resources[] = {
|
||||
[0] = {
|
||||
.start = AT91SAM9263_BASE_TWI,
|
||||
.end = AT91SAM9263_BASE_TWI + SZ_16K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = AT91SAM9263_ID_TWI,
|
||||
.end = AT91SAM9263_ID_TWI,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device at91sam9263_twi_device = {
|
||||
.name = "at91_i2c",
|
||||
.id = -1,
|
||||
.resource = twi_resources,
|
||||
.num_resources = ARRAY_SIZE(twi_resources),
|
||||
};
|
||||
|
||||
void __init at91_add_device_i2c(void)
|
||||
{
|
||||
/* pins used for TWI interface */
|
||||
at91_set_A_periph(AT91_PIN_PB4, 0); /* TWD */
|
||||
at91_set_multi_drive(AT91_PIN_PB4, 1);
|
||||
|
||||
at91_set_A_periph(AT91_PIN_PB5, 0); /* TWCK */
|
||||
at91_set_multi_drive(AT91_PIN_PB5, 1);
|
||||
|
||||
platform_device_register(&at91sam9263_twi_device);
|
||||
}
|
||||
#else
|
||||
void __init at91_add_device_i2c(void) {}
|
||||
#endif
|
||||
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* SPI
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
|
||||
static u64 spi_dmamask = 0xffffffffUL;
|
||||
|
||||
static struct resource spi0_resources[] = {
|
||||
[0] = {
|
||||
.start = AT91SAM9263_BASE_SPI0,
|
||||
.end = AT91SAM9263_BASE_SPI0 + SZ_16K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = AT91SAM9263_ID_SPI0,
|
||||
.end = AT91SAM9263_ID_SPI0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device at91sam9263_spi0_device = {
|
||||
.name = "atmel_spi",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.dma_mask = &spi_dmamask,
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
},
|
||||
.resource = spi0_resources,
|
||||
.num_resources = ARRAY_SIZE(spi0_resources),
|
||||
};
|
||||
|
||||
static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA5, AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PB11 };
|
||||
|
||||
static struct resource spi1_resources[] = {
|
||||
[0] = {
|
||||
.start = AT91SAM9263_BASE_SPI1,
|
||||
.end = AT91SAM9263_BASE_SPI1 + SZ_16K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = AT91SAM9263_ID_SPI1,
|
||||
.end = AT91SAM9263_ID_SPI1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device at91sam9263_spi1_device = {
|
||||
.name = "atmel_spi",
|
||||
.id = 1,
|
||||
.dev = {
|
||||
.dma_mask = &spi_dmamask,
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
},
|
||||
.resource = spi1_resources,
|
||||
.num_resources = ARRAY_SIZE(spi1_resources),
|
||||
};
|
||||
|
||||
static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB15, AT91_PIN_PB16, AT91_PIN_PB17, AT91_PIN_PB18 };
|
||||
|
||||
void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
|
||||
{
|
||||
int i;
|
||||
unsigned long cs_pin;
|
||||
short enable_spi0 = 0;
|
||||
short enable_spi1 = 0;
|
||||
|
||||
/* Choose SPI chip-selects */
|
||||
for (i = 0; i < nr_devices; i++) {
|
||||
if (devices[i].controller_data)
|
||||
cs_pin = (unsigned long) devices[i].controller_data;
|
||||
else if (devices[i].bus_num == 0)
|
||||
cs_pin = spi0_standard_cs[devices[i].chip_select];
|
||||
else
|
||||
cs_pin = spi1_standard_cs[devices[i].chip_select];
|
||||
|
||||
if (devices[i].bus_num == 0)
|
||||
enable_spi0 = 1;
|
||||
else
|
||||
enable_spi1 = 1;
|
||||
|
||||
/* enable chip-select pin */
|
||||
at91_set_gpio_output(cs_pin, 1);
|
||||
|
||||
/* pass chip-select pin to driver */
|
||||
devices[i].controller_data = (void *) cs_pin;
|
||||
}
|
||||
|
||||
spi_register_board_info(devices, nr_devices);
|
||||
|
||||
/* Configure SPI bus(es) */
|
||||
if (enable_spi0) {
|
||||
at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
|
||||
at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
|
||||
at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI1_SPCK */
|
||||
|
||||
at91_clock_associate("spi0_clk", &at91sam9263_spi0_device.dev, "spi_clk");
|
||||
platform_device_register(&at91sam9263_spi0_device);
|
||||
}
|
||||
if (enable_spi1) {
|
||||
at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */
|
||||
at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */
|
||||
at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */
|
||||
|
||||
at91_clock_associate("spi1_clk", &at91sam9263_spi1_device.dev, "spi_clk");
|
||||
platform_device_register(&at91sam9263_spi1_device);
|
||||
}
|
||||
}
|
||||
#else
|
||||
void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
|
||||
#endif
|
||||
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* LEDs
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#if defined(CONFIG_LEDS)
|
||||
u8 at91_leds_cpu;
|
||||
u8 at91_leds_timer;
|
||||
|
||||
void __init at91_init_leds(u8 cpu_led, u8 timer_led)
|
||||
{
|
||||
/* Enable GPIO to access the LEDs */
|
||||
at91_set_gpio_output(cpu_led, 1);
|
||||
at91_set_gpio_output(timer_led, 1);
|
||||
|
||||
at91_leds_cpu = cpu_led;
|
||||
at91_leds_timer = timer_led;
|
||||
}
|
||||
#else
|
||||
void __init at91_init_leds(u8 cpu_led, u8 timer_led) {}
|
||||
#endif
|
||||
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* UART
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#if defined(CONFIG_SERIAL_ATMEL)
|
||||
|
||||
static struct resource dbgu_resources[] = {
|
||||
[0] = {
|
||||
.start = AT91_VA_BASE_SYS + AT91_DBGU,
|
||||
.end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = AT91_ID_SYS,
|
||||
.end = AT91_ID_SYS,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct atmel_uart_data dbgu_data = {
|
||||
.use_dma_tx = 0,
|
||||
.use_dma_rx = 0, /* DBGU not capable of receive DMA */
|
||||
.regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
|
||||
};
|
||||
|
||||
static struct platform_device at91sam9263_dbgu_device = {
|
||||
.name = "atmel_usart",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &dbgu_data,
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
},
|
||||
.resource = dbgu_resources,
|
||||
.num_resources = ARRAY_SIZE(dbgu_resources),
|
||||
};
|
||||
|
||||
static inline void configure_dbgu_pins(void)
|
||||
{
|
||||
at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
|
||||
at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
|
||||
}
|
||||
|
||||
static struct resource uart0_resources[] = {
|
||||
[0] = {
|
||||
.start = AT91SAM9263_BASE_US0,
|
||||
.end = AT91SAM9263_BASE_US0 + SZ_16K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = AT91SAM9263_ID_US0,
|
||||
.end = AT91SAM9263_ID_US0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct atmel_uart_data uart0_data = {
|
||||
.use_dma_tx = 1,
|
||||
.use_dma_rx = 1,
|
||||
};
|
||||
|
||||
static struct platform_device at91sam9263_uart0_device = {
|
||||
.name = "atmel_usart",
|
||||
.id = 1,
|
||||
.dev = {
|
||||
.platform_data = &uart0_data,
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
},
|
||||
.resource = uart0_resources,
|
||||
.num_resources = ARRAY_SIZE(uart0_resources),
|
||||
};
|
||||
|
||||
static inline void configure_usart0_pins(void)
|
||||
{
|
||||
at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */
|
||||
at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */
|
||||
at91_set_A_periph(AT91_PIN_PA28, 0); /* RTS0 */
|
||||
at91_set_A_periph(AT91_PIN_PA29, 0); /* CTS0 */
|
||||
}
|
||||
|
||||
static struct resource uart1_resources[] = {
|
||||
[0] = {
|
||||
.start = AT91SAM9263_BASE_US1,
|
||||
.end = AT91SAM9263_BASE_US1 + SZ_16K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = AT91SAM9263_ID_US1,
|
||||
.end = AT91SAM9263_ID_US1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct atmel_uart_data uart1_data = {
|
||||
.use_dma_tx = 1,
|
||||
.use_dma_rx = 1,
|
||||
};
|
||||
|
||||
static struct platform_device at91sam9263_uart1_device = {
|
||||
.name = "atmel_usart",
|
||||
.id = 2,
|
||||
.dev = {
|
||||
.platform_data = &uart1_data,
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
},
|
||||
.resource = uart1_resources,
|
||||
.num_resources = ARRAY_SIZE(uart1_resources),
|
||||
};
|
||||
|
||||
static inline void configure_usart1_pins(void)
|
||||
{
|
||||
at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
|
||||
at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
|
||||
at91_set_B_periph(AT91_PIN_PD7, 0); /* RTS1 */
|
||||
at91_set_B_periph(AT91_PIN_PD8, 0); /* CTS1 */
|
||||
}
|
||||
|
||||
static struct resource uart2_resources[] = {
|
||||
[0] = {
|
||||
.start = AT91SAM9263_BASE_US2,
|
||||
.end = AT91SAM9263_BASE_US2 + SZ_16K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = AT91SAM9263_ID_US2,
|
||||
.end = AT91SAM9263_ID_US2,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct atmel_uart_data uart2_data = {
|
||||
.use_dma_tx = 1,
|
||||
.use_dma_rx = 1,
|
||||
};
|
||||
|
||||
static struct platform_device at91sam9263_uart2_device = {
|
||||
.name = "atmel_usart",
|
||||
.id = 3,
|
||||
.dev = {
|
||||
.platform_data = &uart2_data,
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
},
|
||||
.resource = uart2_resources,
|
||||
.num_resources = ARRAY_SIZE(uart2_resources),
|
||||
};
|
||||
|
||||
static inline void configure_usart2_pins(void)
|
||||
{
|
||||
at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
|
||||
at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
|
||||
at91_set_B_periph(AT91_PIN_PD5, 0); /* RTS2 */
|
||||
at91_set_B_periph(AT91_PIN_PD6, 0); /* CTS2 */
|
||||
}
|
||||
|
||||
struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
|
||||
struct platform_device *atmel_default_console_device; /* the serial console device */
|
||||
|
||||
void __init at91_init_serial(struct at91_uart_config *config)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Fill in list of supported UARTs */
|
||||
for (i = 0; i < config->nr_tty; i++) {
|
||||
switch (config->tty_map[i]) {
|
||||
case 0:
|
||||
configure_usart0_pins();
|
||||
at91_uarts[i] = &at91sam9263_uart0_device;
|
||||
at91_clock_associate("usart0_clk", &at91sam9263_uart0_device.dev, "usart");
|
||||
break;
|
||||
case 1:
|
||||
configure_usart1_pins();
|
||||
at91_uarts[i] = &at91sam9263_uart1_device;
|
||||
at91_clock_associate("usart1_clk", &at91sam9263_uart1_device.dev, "usart");
|
||||
break;
|
||||
case 2:
|
||||
configure_usart2_pins();
|
||||
at91_uarts[i] = &at91sam9263_uart2_device;
|
||||
at91_clock_associate("usart2_clk", &at91sam9263_uart2_device.dev, "usart");
|
||||
break;
|
||||
case 3:
|
||||
configure_dbgu_pins();
|
||||
at91_uarts[i] = &at91sam9263_dbgu_device;
|
||||
at91_clock_associate("mck", &at91sam9263_dbgu_device.dev, "usart");
|
||||
break;
|
||||
default:
|
||||
continue;
|
||||
}
|
||||
at91_uarts[i]->id = i; /* update ID number to mapped ID */
|
||||
}
|
||||
|
||||
/* Set serial console device */
|
||||
if (config->console_tty < ATMEL_MAX_UART)
|
||||
atmel_default_console_device = at91_uarts[config->console_tty];
|
||||
if (!atmel_default_console_device)
|
||||
printk(KERN_INFO "AT91: No default serial console defined.\n");
|
||||
}
|
||||
|
||||
void __init at91_add_device_serial(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ATMEL_MAX_UART; i++) {
|
||||
if (at91_uarts[i])
|
||||
platform_device_register(at91_uarts[i]);
|
||||
}
|
||||
}
|
||||
#else
|
||||
void __init at91_init_serial(struct at91_uart_config *config) {}
|
||||
void __init at91_add_device_serial(void) {}
|
||||
#endif
|
||||
|
||||
|
||||
/* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* These devices are always present and don't need any board-specific
|
||||
* setup.
|
||||
*/
|
||||
static int __init at91_add_standard_devices(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(at91_add_standard_devices);
|
||||
|
|
@ -598,7 +598,7 @@ int __init at91_clock_init(unsigned long main_clock)
|
|||
udpck.pmc_mask = AT91RM9200_PMC_UDP;
|
||||
at91_sys_write(AT91_PMC_SCDR, AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP);
|
||||
at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
|
||||
} else if (cpu_is_at91sam9260()) {
|
||||
} else if (cpu_is_at91sam9260() || cpu_is_at91sam9263()) {
|
||||
uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
|
||||
udpck.pmc_mask = AT91SAM926x_PMC_UDP;
|
||||
at91_sys_write(AT91_PMC_SCDR, AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP);
|
||||
|
|
|
|||
|
|
@ -12,11 +12,13 @@
|
|||
extern void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banks);
|
||||
extern void __init at91sam9260_initialize(unsigned long main_clock);
|
||||
extern void __init at91sam9261_initialize(unsigned long main_clock);
|
||||
extern void __init at91sam9263_initialize(unsigned long main_clock);
|
||||
|
||||
/* Interrupts */
|
||||
extern void __init at91rm9200_init_interrupts(unsigned int priority[]);
|
||||
extern void __init at91sam9260_init_interrupts(unsigned int priority[]);
|
||||
extern void __init at91sam9261_init_interrupts(unsigned int priority[]);
|
||||
extern void __init at91sam9263_init_interrupts(unsigned int priority[]);
|
||||
extern void __init at91_aic_init(unsigned int priority[]);
|
||||
|
||||
/* Timer */
|
||||
|
|
|
|||
|
|
@ -80,6 +80,8 @@ static int at91_pm_verify_clocks(void)
|
|||
#warning "Check SAM9260 USB clocks"
|
||||
} else if (cpu_is_at91sam9261()) {
|
||||
#warning "Check SAM9261 USB clocks"
|
||||
} else if (cpu_is_at91sam9263()) {
|
||||
#warning "Check SAM9263 USB clocks"
|
||||
}
|
||||
|
||||
#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
|
||||
|
|
|
|||
|
|
@ -171,8 +171,8 @@ config CPU_ARM925T
|
|||
# ARM926T
|
||||
config CPU_ARM926T
|
||||
bool "Support ARM926T processor"
|
||||
depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261
|
||||
default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261
|
||||
depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263
|
||||
default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263
|
||||
select CPU_32v5
|
||||
select CPU_ABRT_EV5TJ
|
||||
select CPU_CACHE_VIVT
|
||||
|
|
|
|||
|
|
@ -913,7 +913,7 @@ static void pullup(struct at91_udc *udc, int is_on)
|
|||
at91_udp_write(udc, AT91_UDP_TXVC, 0);
|
||||
if (cpu_is_at91rm9200())
|
||||
at91_set_gpio_value(udc->board.pullup_pin, 1);
|
||||
else if (cpu_is_at91sam9260()) {
|
||||
else if (cpu_is_at91sam9260() || cpu_is_at91sam9263()) {
|
||||
u32 txvc = at91_udp_read(udc, AT91_UDP_TXVC);
|
||||
|
||||
txvc |= AT91_UDP_TXVC_PUON;
|
||||
|
|
@ -930,7 +930,7 @@ static void pullup(struct at91_udc *udc, int is_on)
|
|||
at91_udp_write(udc, AT91_UDP_TXVC, AT91_UDP_TXVC_TXVDIS);
|
||||
if (cpu_is_at91rm9200())
|
||||
at91_set_gpio_value(udc->board.pullup_pin, 0);
|
||||
else if (cpu_is_at91sam9260()) {
|
||||
else if (cpu_is_at91sam9260() || cpu_is_at91sam9263()) {
|
||||
u32 txvc = at91_udp_read(udc, AT91_UDP_TXVC);
|
||||
|
||||
txvc &= ~AT91_UDP_TXVC_PUON;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,131 @@
|
|||
/*
|
||||
* include/asm-arm/arch-at91/at91sam9263.h
|
||||
*
|
||||
* (C) 2007 Atmel Corporation.
|
||||
*
|
||||
* Common definitions.
|
||||
* Based on AT91SAM9263 datasheet revision B (Preliminary).
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9263_H
|
||||
#define AT91SAM9263_H
|
||||
|
||||
/*
|
||||
* Peripheral identifiers/interrupts.
|
||||
*/
|
||||
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
|
||||
#define AT91_ID_SYS 1 /* System Peripherals */
|
||||
#define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */
|
||||
#define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */
|
||||
#define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */
|
||||
#define AT91SAM9263_ID_US0 7 /* USART 0 */
|
||||
#define AT91SAM9263_ID_US1 8 /* USART 1 */
|
||||
#define AT91SAM9263_ID_US2 9 /* USART 2 */
|
||||
#define AT91SAM9263_ID_MCI0 10 /* Multimedia Card Interface 0 */
|
||||
#define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */
|
||||
#define AT91SAM9263_ID_CAN 12 /* CAN */
|
||||
#define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */
|
||||
#define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */
|
||||
#define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */
|
||||
#define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */
|
||||
#define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */
|
||||
#define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */
|
||||
#define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */
|
||||
#define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */
|
||||
#define AT91SAM9263_ID_EMAC 21 /* Ethernet */
|
||||
#define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */
|
||||
#define AT91SAM9263_ID_UDP 24 /* USB Device Port */
|
||||
#define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */
|
||||
#define AT91SAM9263_ID_LCDC 26 /* LCD Controller */
|
||||
#define AT91SAM9263_ID_DMA 27 /* DMA Controller */
|
||||
#define AT91SAM9263_ID_UHP 29 /* USB Host port */
|
||||
#define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
|
||||
#define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
|
||||
|
||||
|
||||
/*
|
||||
* User Peripheral physical base addresses.
|
||||
*/
|
||||
#define AT91SAM9263_BASE_UDP 0xfff78000
|
||||
#define AT91SAM9263_BASE_TCB0 0xfff7c000
|
||||
#define AT91SAM9263_BASE_TC0 0xfff7c000
|
||||
#define AT91SAM9263_BASE_TC1 0xfff7c040
|
||||
#define AT91SAM9263_BASE_TC2 0xfff7c080
|
||||
#define AT91SAM9263_BASE_MCI0 0xfff80000
|
||||
#define AT91SAM9263_BASE_MCI1 0xfff84000
|
||||
#define AT91SAM9263_BASE_TWI 0xfff88000
|
||||
#define AT91SAM9263_BASE_US0 0xfff8c000
|
||||
#define AT91SAM9263_BASE_US1 0xfff90000
|
||||
#define AT91SAM9263_BASE_US2 0xfff94000
|
||||
#define AT91SAM9263_BASE_SSC0 0xfff98000
|
||||
#define AT91SAM9263_BASE_SSC1 0xfff9c000
|
||||
#define AT91SAM9263_BASE_AC97C 0xfffa0000
|
||||
#define AT91SAM9263_BASE_SPI0 0xfffa4000
|
||||
#define AT91SAM9263_BASE_SPI1 0xfffa8000
|
||||
#define AT91SAM9263_BASE_CAN 0xfffac000
|
||||
#define AT91SAM9263_BASE_PWMC 0xfffb8000
|
||||
#define AT91SAM9263_BASE_EMAC 0xfffbc000
|
||||
#define AT91SAM9263_BASE_ISI 0xfffc4000
|
||||
#define AT91SAM9263_BASE_2DGE 0xfffc8000
|
||||
#define AT91_BASE_SYS 0xffffe000
|
||||
|
||||
/*
|
||||
* System Peripherals (offset from AT91_BASE_SYS)
|
||||
*/
|
||||
#define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS)
|
||||
#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS)
|
||||
#define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS)
|
||||
#define AT91_ECC1 (0xffffe600 - AT91_BASE_SYS)
|
||||
#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS)
|
||||
#define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS)
|
||||
#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
|
||||
#define AT91_CCFG (0xffffed10 - AT91_BASE_SYS)
|
||||
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
|
||||
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
|
||||
#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
|
||||
#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
|
||||
#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
|
||||
#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
|
||||
#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS)
|
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
||||
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
|
||||
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
|
||||
#define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS)
|
||||
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
|
||||
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
|
||||
#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS)
|
||||
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
|
||||
|
||||
#define AT91_SMC AT91_SMC0
|
||||
|
||||
/*
|
||||
* Internal Memory.
|
||||
*/
|
||||
#define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */
|
||||
#define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */
|
||||
|
||||
#define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */
|
||||
#define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
|
||||
|
||||
#define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */
|
||||
#define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */
|
||||
|
||||
#define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */
|
||||
#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */
|
||||
#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */
|
||||
|
||||
#if 0
|
||||
/*
|
||||
* PIO pin definitions (peripheral A/B multiplexing).
|
||||
*/
|
||||
|
||||
// TODO: Add
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,129 @@
|
|||
/*
|
||||
* include/asm-arm/arch-at91/at91sam9263_matrix.h
|
||||
*
|
||||
* Copyright (C) 2006 Atmel Corporation.
|
||||
*
|
||||
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
|
||||
* Based on AT91SAM9263 datasheet revision B (Preliminary).
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9263_MATRIX_H
|
||||
#define AT91SAM9263_MATRIX_H
|
||||
|
||||
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
|
||||
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
|
||||
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
|
||||
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
|
||||
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
|
||||
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
|
||||
#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
|
||||
#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
|
||||
#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
|
||||
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
|
||||
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
|
||||
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
|
||||
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
|
||||
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
|
||||
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
|
||||
|
||||
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
|
||||
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
|
||||
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
|
||||
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
|
||||
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
|
||||
#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
|
||||
#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
|
||||
#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
|
||||
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
|
||||
#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
|
||||
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
|
||||
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
|
||||
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
|
||||
|
||||
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
|
||||
#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
|
||||
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
|
||||
#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
|
||||
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
|
||||
#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
|
||||
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
|
||||
#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
|
||||
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
|
||||
#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
|
||||
#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
|
||||
#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
|
||||
#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
|
||||
#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
|
||||
#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
|
||||
#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
|
||||
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
|
||||
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
|
||||
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
|
||||
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
|
||||
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
|
||||
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
|
||||
#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
|
||||
#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
|
||||
#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
|
||||
|
||||
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
|
||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
||||
#define AT91_MATRIX_RCB2 (1 << 2)
|
||||
#define AT91_MATRIX_RCB3 (1 << 3)
|
||||
#define AT91_MATRIX_RCB4 (1 << 4)
|
||||
#define AT91_MATRIX_RCB5 (1 << 5)
|
||||
#define AT91_MATRIX_RCB6 (1 << 6)
|
||||
#define AT91_MATRIX_RCB7 (1 << 7)
|
||||
#define AT91_MATRIX_RCB8 (1 << 8)
|
||||
|
||||
#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */
|
||||
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
|
||||
#define AT91_MATRIX_ITCM_0 (0 << 0)
|
||||
#define AT91_MATRIX_ITCM_16 (5 << 0)
|
||||
#define AT91_MATRIX_ITCM_32 (6 << 0)
|
||||
#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
|
||||
#define AT91_MATRIX_DTCM_0 (0 << 4)
|
||||
#define AT91_MATRIX_DTCM_16 (5 << 4)
|
||||
#define AT91_MATRIX_DTCM_32 (6 << 4)
|
||||
|
||||
#define AT91_MATRIX_EBI0CSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1)
|
||||
#define AT91_MATRIX_EBI0_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_EBI0_CS3A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA (1 << 3)
|
||||
#define AT91_MATRIX_EBI0_CS4A (1 << 4) /* Chip Select 4 Assignment */
|
||||
#define AT91_MATRIX_EBI0_CS4A_SMC (0 << 4)
|
||||
#define AT91_MATRIX_EBI0_CS4A_SMC_CF1 (1 << 4)
|
||||
#define AT91_MATRIX_EBI0_CS5A (1 << 5) /* Chip Select 5 Assignment */
|
||||
#define AT91_MATRIX_EBI0_CS5A_SMC (0 << 5)
|
||||
#define AT91_MATRIX_EBI0_CS5A_SMC_CF2 (1 << 5)
|
||||
#define AT91_MATRIX_EBI0_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
#define AT91_MATRIX_EBI0_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
||||
#define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16)
|
||||
#define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16)
|
||||
|
||||
#define AT91_MATRIX_EBI1CSA (AT91_MATRIX + 0x124) /* EBI1 Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1)
|
||||
#define AT91_MATRIX_EBI1_CS2A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_EBI1_CS2A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA (1 << 3)
|
||||
#define AT91_MATRIX_EBI1_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
#define AT91_MATRIX_EBI1_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
||||
#define AT91_MATRIX_EBI1_VDDIOMSEL_1_8V (0 << 16)
|
||||
#define AT91_MATRIX_EBI1_VDDIOMSEL_3_3V (1 << 16)
|
||||
|
||||
#endif
|
||||
|
|
@ -131,4 +131,11 @@
|
|||
#define AT91_SMC_PS_16 (2 << 28)
|
||||
#define AT91_SMC_PS_32 (3 << 28)
|
||||
|
||||
#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */
|
||||
#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
|
||||
#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
|
||||
#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
|
||||
#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
#define ARCH_ID_AT91RM9200 0x09290780
|
||||
#define ARCH_ID_AT91SAM9260 0x019803a0
|
||||
#define ARCH_ID_AT91SAM9261 0x019703a0
|
||||
#define ARCH_ID_AT91SAM9263 0x019607a0
|
||||
|
||||
|
||||
static inline unsigned long at91_cpu_identify(void)
|
||||
|
|
@ -46,4 +47,10 @@ static inline unsigned long at91_cpu_identify(void)
|
|||
#define cpu_is_at91sam9261() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_AT91SAM9263
|
||||
#define cpu_is_at91sam9263() (at91_cpu_identify() == ARCH_ID_AT91SAM9263)
|
||||
#else
|
||||
#define cpu_is_at91sam9263() (0)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -22,6 +22,8 @@
|
|||
#include <asm/arch/at91sam9260.h>
|
||||
#elif defined(CONFIG_ARCH_AT91SAM9261)
|
||||
#include <asm/arch/at91sam9261.h>
|
||||
#elif defined(CONFIG_ARCH_AT91SAM9263)
|
||||
#include <asm/arch/at91sam9263.h>
|
||||
#else
|
||||
#error "Unsupported AT91 processor"
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -32,6 +32,11 @@
|
|||
#define AT91SAM9_MASTER_CLOCK 99300000
|
||||
#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
|
||||
|
||||
#elif defined(CONFIG_ARCH_AT91SAM9263)
|
||||
|
||||
#define AT91SAM9_MASTER_CLOCK 99959500
|
||||
#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue