rdc321x: GPIO routines bugfixes
This patch fixes the use of GPIO routines which are in the PCI configuration space of the RDC321x, therefore reading/writing to this space without spinlock protection can be problematic. We also now request and free GPIOs and support the MGB100 board, previous code was very AR525W-centric. Signed-off-by: Volker Weiss <volker@tintuc.de> Signed-off-by: Florian Fainelli <florian.fainelli@telecomint.eu> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Florian Fainelli
Ingo Molnar
parent
d8d4f157b8
commit
b2ef749720
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@ -1,91 +1,194 @@
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/*
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* Copyright (C) 2007, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
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* RDC321x architecture specific GPIO support
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* GPIO support for RDC SoC R3210/R8610
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*
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* Copyright (C) 2007, Florian Fainelli <florian@openwrt.org>
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* Copyright (C) 2008, Volker Weiss <dev@tintuc.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/autoconf.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <asm/gpio.h>
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#include <asm/mach-rdc321x/rdc321x_defs.h>
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static inline int rdc_gpio_is_valid(unsigned gpio)
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/* spin lock to protect our private copy of GPIO data register plus
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the access to PCI conf registers. */
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static DEFINE_SPINLOCK(gpio_lock);
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/* copy of GPIO data registers */
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static u32 gpio_data_reg1;
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static u32 gpio_data_reg2;
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static u32 gpio_request_data[2];
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static inline void rdc321x_conf_write(unsigned addr, u32 value)
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{
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return (gpio <= RDC_MAX_GPIO);
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outl((1 << 31) | (7 << 11) | addr, RDC3210_CFGREG_ADDR);
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outl(value, RDC3210_CFGREG_DATA);
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}
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static unsigned int rdc_gpio_read(unsigned gpio)
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static inline void rdc321x_conf_or(unsigned addr, u32 value)
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{
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unsigned int val;
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val = 0x80000000 | (7 << 11) | ((gpio&0x20?0x84:0x48));
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outl(val, RDC3210_CFGREG_ADDR);
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udelay(10);
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val = inl(RDC3210_CFGREG_DATA);
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val |= (0x1 << (gpio & 0x1F));
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outl(val, RDC3210_CFGREG_DATA);
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udelay(10);
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val = 0x80000000 | (7 << 11) | ((gpio&0x20?0x88:0x4C));
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outl(val, RDC3210_CFGREG_ADDR);
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udelay(10);
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val = inl(RDC3210_CFGREG_DATA);
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return val;
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outl((1 << 31) | (7 << 11) | addr, RDC3210_CFGREG_ADDR);
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value |= inl(RDC3210_CFGREG_DATA);
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outl(value, RDC3210_CFGREG_DATA);
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}
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static void rdc_gpio_write(unsigned int val)
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static inline u32 rdc321x_conf_read(unsigned addr)
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{
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if (val) {
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outl(val, RDC3210_CFGREG_DATA);
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udelay(10);
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}
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outl((1 << 31) | (7 << 11) | addr, RDC3210_CFGREG_ADDR);
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return inl(RDC3210_CFGREG_DATA);
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}
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/* configure pin as GPIO */
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static void rdc321x_configure_gpio(unsigned gpio)
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{
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unsigned long flags;
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spin_lock_irqsave(&gpio_lock, flags);
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rdc321x_conf_or(gpio < 32
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? RDC321X_GPIO_CTRL_REG1 : RDC321X_GPIO_CTRL_REG2,
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1 << (gpio & 0x1f));
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spin_unlock_irqrestore(&gpio_lock, flags);
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}
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/* initially setup the 2 copies of the gpio data registers.
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This function must be called by the platform setup code. */
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void __init rdc321x_gpio_setup()
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{
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/* this might not be, what others (BIOS, bootloader, etc.)
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wrote to these registers before, but it's a good guess. Still
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better than just using 0xffffffff. */
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gpio_data_reg1 = rdc321x_conf_read(RDC321X_GPIO_DATA_REG1);
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gpio_data_reg2 = rdc321x_conf_read(RDC321X_GPIO_DATA_REG2);
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}
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/* determine, if gpio number is valid */
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static inline int rdc321x_is_gpio(unsigned gpio)
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{
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return gpio <= RDC321X_MAX_GPIO;
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}
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/* request GPIO */
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int rdc_gpio_request(unsigned gpio, const char *label)
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{
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unsigned long flags;
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if (!rdc321x_is_gpio(gpio))
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return -EINVAL;
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spin_lock_irqsave(&gpio_lock, flags);
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if (gpio_request_data[(gpio & 0x20) ? 1 : 0] & (1 << (gpio & 0x1f)))
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goto inuse;
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gpio_request_data[(gpio & 0x20) ? 1 : 0] |= (1 << (gpio & 0x1f));
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spin_unlock_irqrestore(&gpio_lock, flags);
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return 0;
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inuse:
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spin_unlock_irqrestore(&gpio_lock, flags);
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return -EINVAL;
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}
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EXPORT_SYMBOL(rdc_gpio_request);
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/* release previously-claimed GPIO */
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void rdc_gpio_free(unsigned gpio)
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{
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unsigned long flags;
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if (!rdc321x_is_gpio(gpio))
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return;
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spin_lock_irqsave(&gpio_lock, flags);
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gpio_request_data[(gpio & 0x20) ? 1 : 0] &= ~(1 << (gpio & 0x1f));
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spin_unlock_irqrestore(&gpio_lock, flags);
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}
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EXPORT_SYMBOL(rdc_gpio_free);
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/* read GPIO pin */
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int rdc_gpio_get_value(unsigned gpio)
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{
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if (rdc_gpio_is_valid(gpio))
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return (int)rdc_gpio_read(gpio);
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else
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return -EINVAL;
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u32 reg;
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unsigned long flags;
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spin_lock_irqsave(&gpio_lock, flags);
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reg = rdc321x_conf_read(gpio < 32
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? RDC321X_GPIO_DATA_REG1 : RDC321X_GPIO_DATA_REG2);
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spin_unlock_irqrestore(&gpio_lock, flags);
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return (1 << (gpio & 0x1f)) & reg ? 1 : 0;
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}
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EXPORT_SYMBOL(rdc_gpio_get_value);
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/* set GPIO pin to value */
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void rdc_gpio_set_value(unsigned gpio, int value)
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{
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unsigned int val;
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unsigned long flags;
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u32 reg;
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if (!rdc_gpio_is_valid(gpio))
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return;
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val = rdc_gpio_read(gpio);
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if (value)
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val &= ~(0x1 << (gpio & 0x1F));
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else
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val |= (0x1 << (gpio & 0x1F));
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rdc_gpio_write(val);
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reg = 1 << (gpio & 0x1f);
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if (gpio < 32) {
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spin_lock_irqsave(&gpio_lock, flags);
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if (value)
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gpio_data_reg1 |= reg;
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else
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gpio_data_reg1 &= ~reg;
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rdc321x_conf_write(RDC321X_GPIO_DATA_REG1, gpio_data_reg1);
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spin_unlock_irqrestore(&gpio_lock, flags);
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} else {
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spin_lock_irqsave(&gpio_lock, flags);
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if (value)
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gpio_data_reg2 |= reg;
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else
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gpio_data_reg2 &= ~reg;
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rdc321x_conf_write(RDC321X_GPIO_DATA_REG2, gpio_data_reg2);
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spin_unlock_irqrestore(&gpio_lock, flags);
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}
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}
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EXPORT_SYMBOL(rdc_gpio_set_value);
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/* configure GPIO pin as input */
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int rdc_gpio_direction_input(unsigned gpio)
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{
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if (!rdc321x_is_gpio(gpio))
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return -EINVAL;
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rdc321x_configure_gpio(gpio);
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return 0;
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}
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EXPORT_SYMBOL(rdc_gpio_direction_input);
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/* configure GPIO pin as output and set value */
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int rdc_gpio_direction_output(unsigned gpio, int value)
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{
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if (!rdc321x_is_gpio(gpio))
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return -EINVAL;
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gpio_set_value(gpio, value);
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rdc321x_configure_gpio(gpio);
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return 0;
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}
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EXPORT_SYMBOL(rdc_gpio_direction_output);
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@ -62,6 +62,8 @@ static struct platform_device *rdc321x_devs[] = {
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static int __init rdc_board_setup(void)
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{
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rdc321x_gpio_setup();
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return platform_add_devices(rdc321x_devs, ARRAY_SIZE(rdc321x_devs));
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}
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@ -5,19 +5,20 @@ extern int rdc_gpio_get_value(unsigned gpio);
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extern void rdc_gpio_set_value(unsigned gpio, int value);
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extern int rdc_gpio_direction_input(unsigned gpio);
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extern int rdc_gpio_direction_output(unsigned gpio, int value);
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extern int rdc_gpio_request(unsigned gpio, const char *label);
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extern void rdc_gpio_free(unsigned gpio);
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extern void __init rdc321x_gpio_setup(void);
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/* Wrappers for the arch-neutral GPIO API */
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static inline int gpio_request(unsigned gpio, const char *label)
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{
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/* Not yet implemented */
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return 0;
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return rdc_gpio_request(gpio, label);
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}
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static inline void gpio_free(unsigned gpio)
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{
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/* Not yet implemented */
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rdc_gpio_free(gpio);
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}
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static inline int gpio_direction_input(unsigned gpio)
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@ -3,4 +3,10 @@
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/* General purpose configuration and data registers */
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#define RDC3210_CFGREG_ADDR 0x0CF8
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#define RDC3210_CFGREG_DATA 0x0CFC
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#define RDC_MAX_GPIO 0x3A
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#define RDC321X_GPIO_CTRL_REG1 0x48
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#define RDC321X_GPIO_CTRL_REG2 0x84
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#define RDC321X_GPIO_DATA_REG1 0x4c
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#define RDC321X_GPIO_DATA_REG2 0x88
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#define RDC321X_MAX_GPIO 58
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