clk: renesas: rz: Select EXTAL vs USB clock
Check the MD_CLK pin to determine the current clock mode in order to set the pll clock parent correctly. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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@ -25,10 +25,31 @@ struct rz_cpg {
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#define CPG_FRQCR 0x10
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#define CPG_FRQCR2 0x14
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#define PPR0 0xFCFE3200
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#define PIBC0 0xFCFE7000
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#define MD_CLK(x) ((x >> 2) & 1) /* P0_2 */
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/* -----------------------------------------------------------------------------
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* Initialization
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*/
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static u16 __init rz_cpg_read_mode_pins(void)
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{
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void __iomem *ppr0, *pibc0;
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u16 modes;
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ppr0 = ioremap_nocache(PPR0, 2);
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pibc0 = ioremap_nocache(PIBC0, 2);
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BUG_ON(!ppr0 || !pibc0);
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iowrite16(4, pibc0); /* enable input buffer */
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modes = ioread16(ppr0);
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iounmap(ppr0);
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iounmap(pibc0);
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return modes;
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}
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static struct clk * __init
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rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *name)
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{
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@ -37,8 +58,7 @@ rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *na
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static const unsigned frqcr_tab[4] = { 3, 2, 0, 1 };
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if (strcmp(name, "pll") == 0) {
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/* FIXME: cpg_mode should be read from GPIO. But no GPIO support yet */
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unsigned cpg_mode = 0; /* hardcoded to EXTAL for now */
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unsigned int cpg_mode = MD_CLK(rz_cpg_read_mode_pins());
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const char *parent_name = of_clk_get_parent_name(np, cpg_mode);
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mult = cpg_mode ? (32 / 4) : 30;
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