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Documentation sysfs-bus-usb: Add rx_lanes and tx_lanes introduced in USB 3.2 

rx_lanes and tx_lanes sysfs entries show the number of lanes in use by a
device.
USB 3.2 adds support for Dual-lane (symmetrical), using 2 rx lanes and
2 tx lanes for normal non Inter-Chip SSIC devices.
USB 3.1 and older are all single lane.

SSIC devices can have up to 4 lanes per direction in use,
with different number of rx and tx lanes.

Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Mathias Nyman 2018-04-19 19:05:55 +03:00 committed by Greg Kroah-Hartman
parent 460fd21618
commit b462e2e0d6
1 changed files with 18 additions and 0 deletions
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Documentation/ABI/testing/sysfs-bus-usb
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@ -236,3 +236,21 @@ Description:
Supported values are 0 - 15. Supported values are 0 - 15.
More information on how besl values map to microseconds can be found in More information on how besl values map to microseconds can be found in
USB 2.0 ECN Errata for Link Power Management, section 4.10) USB 2.0 ECN Errata for Link Power Management, section 4.10)
What: /sys/bus/usb/devices/.../rx_lanes
Date: March 2018
Contact: Mathias Nyman <mathias.nyman@linux.intel.com>
Description:
Number of rx lanes the device is using.
USB 3.2 adds Dual-lane support, 2 rx and 2 tx lanes over Type-C.
Inter-Chip SSIC devices support asymmetric lanes up to 4 lanes per
direction. Devices before USB 3.2 are single lane (rx_lanes = 1)
What: /sys/bus/usb/devices/.../tx_lanes
Date: March 2018
Contact: Mathias Nyman <mathias.nyman@linux.intel.com>
Description:
Number of tx lanes the device is using.
USB 3.2 adds Dual-lane support, 2 rx and 2 tx -lanes over Type-C.
Inter-Chip SSIC devices support asymmetric lanes up to 4 lanes per
direction. Devices before USB 3.2 are single lane (tx_lanes = 1)